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cleanup

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This commit is contained in:
Blaise Tine 2023-11-03 08:09:59 -04:00
parent 1c100c4cf5
commit 970cbf066a
7 changed files with 20 additions and 61 deletions
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5
sim/simx/cluster.cpp
View file

@ -208,10 +208,7 @@ ProcessorImpl* Cluster::processor() const {
Cluster::PerfStats Cluster::perf_stats() const {
Cluster::PerfStats perf;
perf.icache = icaches_->perf_stats();
perf.dcache = dcaches_->perf_stats();
perf.tcache = tcaches_->perf_stats();
perf.ocache = ocaches_->perf_stats();
perf.rcache = rcaches_->perf_stats();
perf.dcache = dcaches_->perf_stats();
perf.l2cache = l2cache_->perf_stats();
for (auto sharedmem : sharedmems_) {

6
sim/simx/cluster.h
View file

@ -32,18 +32,12 @@ public:
CacheSim::PerfStats dcache;
SharedMem::PerfStats sharedmem;
CacheSim::PerfStats l2cache;
CacheSim::PerfStats tcache;
CacheSim::PerfStats ocache;
CacheSim::PerfStats rcache;
PerfStats& operator+=(const PerfStats& rhs) {
this->icache += rhs.icache;
this->dcache += rhs.dcache;
this->sharedmem += rhs.sharedmem;
this->l2cache += rhs.l2cache;
this->tcache += rhs.tcache;
this->ocache += rhs.ocache;
this->rcache += rhs.rcache;
return *this;
}
};

4
sim/simx/core.h
View file

@ -197,10 +197,6 @@ private:
friend class AluUnit;
friend class FpuUnit;
friend class SfuUnit;
friend class TexUnit;
friend class RasterAgent;
friend class RopAgent;
friend class TexAgent;
};
} // namespace vortex

9
sim/simx/decode.cpp
View file

@ -553,15 +553,6 @@ std::shared_ptr<Instr> Decoder::decode(uint32_t code) const {
std::abort();
}
break;
case 1:
switch (func3) {
case 0: // RASTER
instr->setDestReg(rd, RegType::Integer);
break;
default:
std::abort();
}
break;
default:
std::abort();
}

14
sim/simx/exe_unit.cpp
View file

@ -271,22 +271,10 @@ void LsuUnit::tick() {
SfuUnit::SfuUnit(const SimContext& ctx, Core* core)
: ExeUnit(ctx, core, "SFU")
, input_idx_(0)
{}
void SfuUnit::tick() {
// handle pending responses
for (auto pending_rsp : pending_rsps_) {
if (pending_rsp->empty())
continue;
auto trace = pending_rsp->front();
if (trace->cid != core_->id())
continue;
int iw = trace->wid % ISSUE_WIDTH;
auto& output = Outputs.at(iw);
output.send(trace, 1);
pending_rsp->pop();
}
// check input queue
for (uint32_t i = 0; i < ISSUE_WIDTH; ++i) {
int iw = (input_idx_ + i) % ISSUE_WIDTH;

37
sim/simx/exe_unit.h
View file

@ -45,6 +45,24 @@ protected:
///////////////////////////////////////////////////////////////////////////////
class AluUnit : public ExeUnit {
public:
AluUnit(const SimContext& ctx, Core*);
void tick();
};
///////////////////////////////////////////////////////////////////////////////
class FpuUnit : public ExeUnit {
public:
FpuUnit(const SimContext& ctx, Core*);
void tick();
};
///////////////////////////////////////////////////////////////////////////////
class LsuUnit : public ExeUnit {
public:
LsuUnit(const SimContext& ctx, Core*);
@ -68,24 +86,6 @@ private:
///////////////////////////////////////////////////////////////////////////////
class AluUnit : public ExeUnit {
public:
AluUnit(const SimContext& ctx, Core*);
void tick();
};
///////////////////////////////////////////////////////////////////////////////
class FpuUnit : public ExeUnit {
public:
FpuUnit(const SimContext& ctx, Core*);
void tick();
};
///////////////////////////////////////////////////////////////////////////////
class SfuUnit : public ExeUnit {
public:
SfuUnit(const SimContext& ctx, Core*);
@ -93,7 +93,6 @@ public:
void tick();
private:
std::vector<SimPort<pipeline_trace_t*>*> pending_rsps_;
uint32_t input_idx_;
};

6
sim/simx/types.h
View file

@ -190,9 +190,6 @@ enum class SfuType {
CSRRW,
CSRRS,
CSRRC,
TEX,
RASTER,
ROP,
CMOV
};
@ -207,9 +204,6 @@ inline std::ostream &operator<<(std::ostream &os, const SfuType& type) {
case SfuType::CSRRW: os << "CSRRW"; break;
case SfuType::CSRRS: os << "CSRRS"; break;
case SfuType::CSRRC: os << "CSRRC"; break;
case SfuType::TEX: os << "TEX"; break;
case SfuType::RASTER: os << "RASTER"; break;
case SfuType::ROP: os << "ROP"; break;
case SfuType::CMOV: os << "CMOV"; break;
}
return os;