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fpu timing optimization
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Blaise Tine
parent
51719f69bb
commit
9718a5b405
3 changed files with 51 additions and 56 deletions
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@ -54,51 +54,25 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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localparam NUM_FPCORES = 4;
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localparam FPCORES_BITS = `LOG2UP(NUM_FPCORES);
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localparam RSP_DATAW = (NUM_LANES * 32) + 1 + $bits(fflags_t) + TAG_WIDTH;
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localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAG_WIDTH;
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`UNUSED_VAR (fmt)
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wire [NUM_FPCORES-1:0] per_core_ready_in;
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wire [NUM_FPCORES-1:0][NUM_LANES-1:0][31:0] per_core_result;
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wire [NUM_FPCORES-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result;
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wire [NUM_FPCORES-1:0][TAG_WIDTH-1:0] per_core_tag_out;
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wire [NUM_FPCORES-1:0] per_core_ready_out;
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wire [NUM_FPCORES-1:0] per_core_valid_out;
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wire [NUM_FPCORES-1:0] per_core_has_fflags;
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fflags_t [NUM_FPCORES-1:0] per_core_fflags;
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wire div_ready_in, sqrt_ready_in;
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wire [NUM_LANES-1:0][31:0] div_result, sqrt_result;
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wire [TAG_WIDTH-1:0] div_tag_out, sqrt_tag_out;
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wire div_ready_out, sqrt_ready_out;
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wire div_valid_out, sqrt_valid_out;
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wire div_has_fflags, sqrt_has_fflags;
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fflags_t div_fflags, sqrt_fflags;
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reg is_madd, is_sub, is_neg, is_div, is_itof, is_signed;
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wire [FPCORES_BITS-1:0] core_select = op_type[3:2];
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always @(*) begin
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is_madd = 'x;
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is_sub = 'x;
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is_neg = 'x;
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is_div = 'x;
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is_itof = 'x;
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is_signed = 'x;
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case (op_type)
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`INST_FPU_ADD: begin is_madd = 0; is_neg = 0; is_sub = fmt[1]; end
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`INST_FPU_MUL: begin is_madd = 0; is_neg = 1; is_sub = 0; end
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`INST_FPU_MADD: begin is_madd = 1; is_neg = 0; is_sub = fmt[1]; end
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`INST_FPU_NMADD: begin is_madd = 1; is_neg = 1; is_sub = fmt[1]; end
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`INST_FPU_DIV: begin is_div = 1; end
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`INST_FPU_SQRT: begin is_div = 0; end
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`INST_FPU_F2I: begin is_itof = 0; is_signed = 1; end
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`INST_FPU_F2U: begin is_itof = 0; is_signed = 0; end
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`INST_FPU_I2F: begin is_itof = 1; is_signed = 1; end
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`INST_FPU_U2F: begin is_itof = 1; is_signed = 0; end
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default: begin end
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endcase
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end
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wire [1:0] div_sqrt_ready_in;
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wire [1:0][NUM_LANES*`XLEN-1:0] div_sqrt_result;
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wire [1:0][TAG_WIDTH-1:0] div_sqrt_tag_out;
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wire [1:0] div_sqrt_ready_out;
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wire [1:0] div_sqrt_valid_out;
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wire [1:0] div_sqrt_has_fflags;
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fflags_t [1:0] div_sqrt_fflags;
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`RESET_RELAY (fma_reset, reset);
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`RESET_RELAY (div_reset, reset);
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@ -120,7 +94,17 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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`UNUSED_VAR (datab)
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`UNUSED_VAR (datac)
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// Decode instruction type
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wire [FPCORES_BITS-1:0] core_select = op_type[3:2];
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wire is_sqrt = op_type[0];
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wire is_itof = op_type[1];
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wire is_signed = ~op_type[0];
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wire is_madd = op_type[1];
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wire is_neg = op_type[0];
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wire is_sub = fmt[1];
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// can accept new request?
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assign per_core_ready_in[FPU_DIVSQRT] = div_sqrt_ready_in[is_sqrt];
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assign ready_in = per_core_ready_in[core_select];
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VX_fpu_fma #(
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@ -154,19 +138,19 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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) fpu_div (
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.clk (clk),
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.reset (div_reset),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && is_div),
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.ready_in (div_ready_in),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && ~is_sqrt),
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.ready_in (div_sqrt_ready_in[0]),
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.mask_in (mask_in),
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.tag_in (tag_in),
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.frm (frm),
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.dataa (dataa_s),
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.datab (datab_s),
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.has_fflags (div_has_fflags),
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.fflags (div_fflags),
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.result (div_result),
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.tag_out (div_tag_out),
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.valid_out (div_valid_out),
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.ready_out (div_ready_out)
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.has_fflags (div_sqrt_has_fflags[0]),
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.fflags (div_sqrt_fflags[0]),
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.result (div_sqrt_result[0]),
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.tag_out (div_sqrt_tag_out[0]),
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.valid_out (div_sqrt_valid_out[0]),
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.ready_out (div_sqrt_ready_out[0])
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);
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VX_fpu_sqrt #(
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@ -175,18 +159,18 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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) fpu_sqrt (
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.clk (clk),
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.reset (sqrt_reset),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && ~is_div),
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.ready_in (sqrt_ready_in),
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.valid_in (valid_in && (core_select == FPU_DIVSQRT) && is_sqrt),
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.ready_in (div_sqrt_ready_in[1]),
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.mask_in (mask_in),
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.tag_in (tag_in),
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.frm (frm),
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.dataa (dataa_s),
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.has_fflags (sqrt_has_fflags),
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.fflags (sqrt_fflags),
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.result (sqrt_result),
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.tag_out (sqrt_tag_out),
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.valid_out (sqrt_valid_out),
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.ready_out (sqrt_ready_out)
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.has_fflags (div_sqrt_has_fflags[1]),
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.fflags (div_sqrt_fflags[1]),
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.result (div_sqrt_result[1]),
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.tag_out (div_sqrt_tag_out[1]),
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.valid_out (div_sqrt_valid_out[1]),
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.ready_out (div_sqrt_ready_out[1])
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);
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wire cvt_ret_int_in = ~is_itof;
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@ -246,7 +230,15 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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///////////////////////////////////////////////////////////////////////////
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assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in;
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wire [1:0][RSP_DATAW-1:0] div_sqrt_arb_data_in;
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for (genvar i = 0; i < 2; ++i) begin
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assign div_sqrt_arb_data_in[i] = {
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div_sqrt_result[i],
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div_sqrt_has_fflags[i],
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div_sqrt_fflags[i],
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div_sqrt_tag_out[i]
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};
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end
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VX_stream_arb #(
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.NUM_INPUTS (2),
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@ -256,10 +248,9 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
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) div_sqrt_arb (
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.clk (clk),
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.reset (reset),
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.valid_in ({sqrt_valid_out, div_valid_out}),
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.ready_in ({sqrt_ready_out, div_ready_out}),
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.data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out},
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{div_result, div_has_fflags, div_fflags, div_tag_out}}),
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.valid_in (div_sqrt_valid_out),
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.ready_in (div_sqrt_ready_out),
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.data_in (div_sqrt_arb_data_in),
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.data_out ({
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per_core_result[FPU_DIVSQRT],
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per_core_has_fflags[FPU_DIVSQRT],
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@ -13,6 +13,7 @@
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_onehot_shift #(
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parameter N = 1,
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parameter M = 1
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@ -28,3 +29,4 @@ module VX_onehot_shift #(
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end
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endmodule
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`TRACING_ON
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@ -13,6 +13,7 @@
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_transpose #(
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parameter N = 1,
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parameter M = 1
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@ -27,3 +28,4 @@ module VX_transpose #(
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end
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endmodule
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`TRACING_ON
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