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Browse source
This commit is contained in:
tinebp 2025-02-20 03:14:58 -08:00
parent 34121429ad
commit 983a848467
4 changed files with 109 additions and 109 deletions
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168
hw/rtl/core/VX_gpr_unit.sv
View file

@ -33,7 +33,7 @@ module VX_gpr_unit import VX_gpu_pkg::*; #(
`endif
VX_writeback_if.slave writeback_if,
VX_opc_if.slave opc_if [NUM_REQS]
VX_gpr_if.slave gpr_if [NUM_REQS]
);
`UNUSED_SPARAM (INSTANCE_ID)
@ -50,52 +50,52 @@ module VX_gpr_unit import VX_gpu_pkg::*; #(
localparam PER_BANK_REG_BITS = NR_BITS - BANKID_REG_BITS;
localparam PER_BANK_WIS_WIDTH = `UP(PER_BANK_WIS_BITS);
localparam PER_BANK_REG_WIDTH = `UP(PER_BANK_REG_BITS);
localparam OPC_REQ_DATAW = SRC_OPD_WIDTH + SIMD_IDX_W + PER_BANK_WIS_WIDTH + PER_BANK_REG_BITS;
localparam OPC_RSP_DATAW = SRC_OPD_WIDTH + `SIMD_WIDTH * `XLEN;
localparam GPR_REQ_DATAW = SRC_OPD_WIDTH + SIMD_IDX_W + PER_BANK_WIS_WIDTH + PER_BANK_REG_BITS;
localparam GPR_RSP_DATAW = SRC_OPD_WIDTH + `SIMD_WIDTH * `XLEN;
localparam BYTEENW = `SIMD_WIDTH * XLENB;
wire [NUM_REQS-1:0] opc_req_valid, opc_req_ready;
wire [NUM_REQS-1:0][OPC_REQ_DATAW-1:0] opc_req_data;
wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] opc_req_bank_idx;
wire [NUM_REQS-1:0] gpr_req_valid, gpr_req_ready;
wire [NUM_REQS-1:0][GPR_REQ_DATAW-1:0] gpr_req_data;
wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] gpr_req_bank_idx;
wire [NUM_BANKS-1:0] gpr_req_valid;
wire [NUM_BANKS-1:0][OPC_REQ_DATAW-1:0] gpr_req_data;
wire [NUM_BANKS-1:0][1:0] gpr_req_opd_id;
wire [NUM_BANKS-1:0][SIMD_IDX_W-1:0] gpr_req_sid;
wire [NUM_BANKS-1:0][PER_BANK_WIS_WIDTH-1:0] gpr_req_wis;
wire [NUM_BANKS-1:0][PER_BANK_REG_WIDTH-1:0] gpr_reg_id;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_req_idx;
wire [NUM_BANKS-1:0] bank_req_valid;
wire [NUM_BANKS-1:0][GPR_REQ_DATAW-1:0] bank_req_data;
wire [NUM_BANKS-1:0][1:0] bank_req_opd_id;
wire [NUM_BANKS-1:0][SIMD_IDX_W-1:0] bank_req_sid;
wire [NUM_BANKS-1:0][PER_BANK_WIS_WIDTH-1:0] bank_req_wis;
wire [NUM_BANKS-1:0][PER_BANK_REG_WIDTH-1:0] bank_req_id;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] bank_req_idx;
wire [NUM_BANKS-1:0][`SIMD_WIDTH-1:0][`XLEN-1:0] gpr_rd_data;
wire [NUM_BANKS-1:0][`SIMD_WIDTH-1:0][`XLEN-1:0] bank_rd_data;
wire [NUM_BANKS-1:0] gpr_rsp_valid;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rsp_idx;
wire [NUM_BANKS-1:0][1:0] gpr_rsp_opd_id;
wire [NUM_BANKS-1:0][OPC_RSP_DATAW-1:0] gpr_rsp_data;
wire [NUM_BANKS-1:0] bank_rsp_valid;
wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] bank_rsp_idx;
wire [NUM_BANKS-1:0][1:0] bank_rsp_opd_id;
wire [NUM_BANKS-1:0][GPR_RSP_DATAW-1:0] bank_rsp_data;
`ifdef PERF_ENABLE
wire [PERF_CTR_BITS-1:0] collisions;
`endif
`UNUSED_VAR (gpr_req_sid)
`UNUSED_VAR (gpr_req_wis)
`UNUSED_VAR (bank_req_sid)
`UNUSED_VAR (bank_req_wis)
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_opc_req
assign opc_req_valid[i] = opc_if[i].req_valid;
assign opc_req_data[i] = {
opc_if[i].req_data.opd_id,
opc_if[i].req_data.sid,
opc_if[i].req_data.wis[ISSUE_WIS_W-1:BANKID_WIS_BITS],
opc_if[i].req_data.reg_id[NR_BITS-1:BANKID_REG_BITS]
for (genvar i = 0; i < NUM_REQS; ++i) begin : g_gpr_req
assign gpr_req_valid[i] = gpr_if[i].req_valid;
assign gpr_req_data[i] = {
gpr_if[i].req_data.opd_id,
gpr_if[i].req_data.sid,
gpr_if[i].req_data.wis[ISSUE_WIS_W-1:BANKID_WIS_BITS],
gpr_if[i].req_data.reg_id[NR_BITS-1:BANKID_REG_BITS]
};
`CONCAT(opc_req_bank_idx[i], opc_if[i].req_data.wis[BANKID_WIS_BITS-1:0], opc_if[i].req_data.reg_id[BANKID_REG_BITS-1:0], BANKID_WIS_BITS, BANKID_REG_BITS)
assign opc_if[i].req_ready = opc_req_ready[i];
`CONCAT(gpr_req_bank_idx[i], gpr_if[i].req_data.wis[BANKID_WIS_BITS-1:0], gpr_if[i].req_data.reg_id[BANKID_REG_BITS-1:0], BANKID_WIS_BITS, BANKID_REG_BITS)
assign gpr_if[i].req_ready = gpr_req_ready[i];
end
VX_stream_xbar #(
.NUM_INPUTS (NUM_REQS),
.NUM_OUTPUTS (NUM_BANKS),
.DATAW (OPC_REQ_DATAW),
.DATAW (GPR_REQ_DATAW),
.ARBITER ("P"),
.OUT_BUF (1),
.PERF_CTR_BITS (PERF_CTR_BITS)
@ -105,56 +105,56 @@ module VX_gpr_unit import VX_gpu_pkg::*; #(
`ifdef PERF_ENABLE
.collisions(collisions),
`endif
.valid_in (opc_req_valid),
.data_in (opc_req_data),
.sel_in (opc_req_bank_idx),
.ready_in (opc_req_ready),
.valid_out (gpr_req_valid),
.data_out (gpr_req_data),
.sel_out (gpr_req_idx),
.valid_in (gpr_req_valid),
.data_in (gpr_req_data),
.sel_in (gpr_req_bank_idx),
.ready_in (gpr_req_ready),
.valid_out (bank_req_valid),
.data_out (bank_req_data),
.sel_out (bank_req_idx),
.ready_out ('1)
);
wire [GPR_BANK_ADDRW-1:0] gpr_wr_addr;
if (SIMD_IDX_BITS != 0 || PER_BANK_WIS_BITS != 0) begin : g_gpr_wr_addr
wire [GPR_BANK_ADDRW-1:0] bank_wr_addr;
if (SIMD_IDX_BITS != 0 || PER_BANK_WIS_BITS != 0) begin : g_bank_wr_addr
wire [SIMD_IDX_BITS + PER_BANK_WIS_BITS-1:0] tmp;
`CONCAT(tmp, writeback_if.data.sid, writeback_if.data.wis[ISSUE_WIS_W-1:BANKID_WIS_BITS], SIMD_IDX_BITS, PER_BANK_WIS_BITS);
assign gpr_wr_addr = {tmp, writeback_if.data.rd[NR_BITS-1:BANKID_REG_BITS]};
end else begin : g_gpr_wr_addr_reg
assign gpr_wr_addr = writeback_if.data.rd[NR_BITS-1:BANKID_REG_BITS];
assign bank_wr_addr = {tmp, writeback_if.data.rd[NR_BITS-1:BANKID_REG_BITS]};
end else begin : g_bank_wr_addr_reg
assign bank_wr_addr = writeback_if.data.rd[NR_BITS-1:BANKID_REG_BITS];
end
wire [BANK_SEL_WIDTH-1:0] gpr_wr_bank_idx;
if (NUM_BANKS != 1) begin : g_gpr_wr_bank_idx
`CONCAT(gpr_wr_bank_idx, writeback_if.data.wis[BANKID_WIS_BITS-1:0], writeback_if.data.rd[BANKID_REG_BITS-1:0], BANKID_WIS_BITS, BANKID_REG_BITS)
end else begin : g_gpr_wr_bank_idx_0
assign gpr_wr_bank_idx = '0;
wire [BANK_SEL_WIDTH-1:0] bank_wr_id;
if (NUM_BANKS != 1) begin : g_bank_wr_id
`CONCAT(bank_wr_id, writeback_if.data.wis[BANKID_WIS_BITS-1:0], writeback_if.data.rd[BANKID_REG_BITS-1:0], BANKID_WIS_BITS, BANKID_REG_BITS)
end else begin : g_bank_wr_id_0
assign bank_wr_id = '0;
end
wire [BYTEENW-1:0] gpr_wr_byteen;
for (genvar i = 0; i < `SIMD_WIDTH; ++i) begin : g_gpr_wr_byteen
assign gpr_wr_byteen[i*XLENB+:XLENB] = {XLENB{writeback_if.data.tmask[i]}};
wire [BYTEENW-1:0] bank_wr_byteen;
for (genvar i = 0; i < `SIMD_WIDTH; ++i) begin : g_bank_wr_byteen
assign bank_wr_byteen[i*XLENB+:XLENB] = {XLENB{writeback_if.data.tmask[i]}};
end
for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_gpr_req_data
assign {gpr_req_opd_id[b], gpr_req_sid[b], gpr_req_wis[b], gpr_reg_id[b]} = gpr_req_data[b];
for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_bank_req_data
assign {bank_req_opd_id[b], bank_req_sid[b], bank_req_wis[b], bank_req_id[b]} = bank_req_data[b];
end
for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_gpr_rams
wire gpr_wr_enabled;
if (BANK_SEL_BITS != 0) begin : g_gpr_wr_enabled_multibanks
assign gpr_wr_enabled = writeback_if.valid && (gpr_wr_bank_idx == BANK_SEL_BITS'(b));
end else begin : g_gpr_wr_enabled
assign gpr_wr_enabled = writeback_if.valid;
for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_banks
wire bank_wr_enabled;
if (BANK_SEL_BITS != 0) begin : g_bank_wr_enabled_multibanks
assign bank_wr_enabled = writeback_if.valid && (bank_wr_id == BANK_SEL_BITS'(b));
end else begin : g_bank_wr_enabled
assign bank_wr_enabled = writeback_if.valid;
end
wire [GPR_BANK_ADDRW-1:0] gpr_rd_addr;
if (SIMD_IDX_BITS != 0 || PER_BANK_WIS_BITS != 0) begin : g_gpr_rd_addr
wire [GPR_BANK_ADDRW-1:0] bank_rd_addr;
if (SIMD_IDX_BITS != 0 || PER_BANK_WIS_BITS != 0) begin : g_bank_rd_addr
wire [(SIMD_IDX_BITS + PER_BANK_WIS_BITS)-1:0] tmp;
`CONCAT(tmp, gpr_req_sid[b], gpr_req_wis[b], SIMD_IDX_BITS, PER_BANK_WIS_BITS);
assign gpr_rd_addr = {tmp, gpr_reg_id[b]};
end else begin : g_gpr_rd_addr_reg
assign gpr_rd_addr = gpr_reg_id[b];
`CONCAT(tmp, bank_req_sid[b], bank_req_wis[b], SIMD_IDX_BITS, PER_BANK_WIS_BITS);
assign bank_rd_addr = {tmp, bank_req_id[b]};
end else begin : g_bank_rd_addr_reg
assign bank_rd_addr = bank_req_id[b];
end
VX_dp_ram #(
@ -169,13 +169,13 @@ module VX_gpr_unit import VX_gpu_pkg::*; #(
) gpr_ram (
.clk (clk),
.reset (reset),
.read (gpr_req_valid[b]),
.wren (gpr_wr_byteen),
.write (gpr_wr_enabled),
.waddr (gpr_wr_addr),
.read (bank_req_valid[b]),
.write (bank_wr_enabled),
.wren (bank_wr_byteen),
.waddr (bank_wr_addr),
.wdata (writeback_if.data.data),
.raddr (gpr_rd_addr),
.rdata (gpr_rd_data[b])
.raddr (bank_rd_addr),
.rdata (bank_rd_data[b])
);
VX_pipe_buffer #(
@ -183,34 +183,34 @@ module VX_gpr_unit import VX_gpu_pkg::*; #(
) pipe_reg1 (
.clk (clk),
.reset (reset),
.valid_in (gpr_req_valid[b]),
.data_in ({gpr_req_idx[b], gpr_req_opd_id[b]}),
.valid_in (bank_req_valid[b]),
.data_in ({bank_req_idx[b], bank_req_opd_id[b]}),
`UNUSED_PIN (ready_in),
.valid_out(gpr_rsp_valid[b]),
.data_out ({gpr_rsp_idx[b], gpr_rsp_opd_id[b]}),
`UNUSED_PIN (ready_out)
.valid_out(bank_rsp_valid[b]),
.data_out ({bank_rsp_idx[b], bank_rsp_opd_id[b]}),
.ready_out('1)
);
assign gpr_rsp_data[b] = {gpr_rsp_opd_id[b], gpr_rd_data[b]};
assign bank_rsp_data[b] = {bank_rsp_opd_id[b], bank_rd_data[b]};
end
`AOS_TO_ITF_RSP_V (opc, opc_if, NUM_REQS, OPC_RSP_DATAW)
`AOS_TO_ITF_RSP_V (gpr, gpr_if, NUM_REQS, GPR_RSP_DATAW)
VX_stream_xpoint #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
.DATAW (OPC_RSP_DATAW),
.DATAW (GPR_RSP_DATAW),
.OUT_BUF (0) // no output buffering
) rsp_xpoint (
.clk (clk),
.reset (reset),
.valid_in (gpr_rsp_valid),
.data_in (gpr_rsp_data),
.sel_in (gpr_rsp_idx),
.valid_in (bank_rsp_valid),
.data_in (bank_rsp_data),
.sel_in (bank_rsp_idx),
`UNUSED_PIN (ready_in),
.valid_out (opc_rsp_valid),
.data_out (opc_rsp_data),
`UNUSED_PIN (ready_out)
.valid_out (gpr_rsp_valid),
.data_out (gpr_rsp_data),
.ready_out ('1)
);
`ifdef PERF_ENABLE

36
hw/rtl/core/VX_opc_unit.sv
View file

@ -26,12 +26,12 @@ module VX_opc_unit import VX_gpu_pkg::*; #(
input wire clk,
input wire reset,
output wire [SIMD_IDX_W-1:0] sid,
output wire [ISSUE_WIS_W-1:0] wis,
output wire [SIMD_IDX_W-1:0] pending_sid,
output wire [ISSUE_WIS_W-1:0] pending_wis,
output reg [NUM_REGS-1:0] pending_regs,
VX_scoreboard_if.slave scoreboard_if,
VX_opc_if.master opc_if,
VX_gpr_if.master gpr_if,
VX_operands_if.master operands_if
);
`UNUSED_SPARAM (INSTANCE_ID)
@ -52,8 +52,8 @@ module VX_opc_unit import VX_gpu_pkg::*; #(
reg [SIMD_IDX_W-1:0] simd_index, simd_index_n;
wire scboard_fire = scoreboard_if.valid && scoreboard_if.ready;
wire col_req_fire = opc_if.req_valid && opc_if.req_ready;
wire col_rsp_fire = opc_if.rsp_valid;
wire gpr_req_fire = gpr_if.req_valid && gpr_if.req_ready;
wire gpr_rsp_fire = gpr_if.rsp_valid;
VX_pipe_buffer #(
.DATAW (SCB_DATAW)
@ -97,11 +97,11 @@ module VX_opc_unit import VX_gpu_pkg::*; #(
end
end
STATE_FETCH: begin
if (col_req_fire) begin
opds_needed_n[opc_if.req_data.opd_id] = 0;
if (gpr_req_fire) begin
opds_needed_n[gpr_if.req_data.opd_id] = 0;
end
if (col_rsp_fire) begin
opds_busy_n[opc_if.rsp_data.opd_id] = 0;
if (gpr_rsp_fire) begin
opds_busy_n[gpr_if.rsp_data.opd_id] = 0;
end
if (opds_busy_n == 0) begin
state_n = STATE_DISPATCH;
@ -149,11 +149,11 @@ module VX_opc_unit import VX_gpu_pkg::*; #(
);
// operands fetch request
assign opc_if.req_valid = opd_fetch_valid;
assign opc_if.req_data.opd_id = opd_id;
assign opc_if.req_data.sid = simd_index;
assign opc_if.req_data.wis = staging_if.data.wis;
assign opc_if.req_data.reg_id = src_regs[opd_id];
assign gpr_if.req_valid = opd_fetch_valid;
assign gpr_if.req_data.opd_id = opd_id;
assign gpr_if.req_data.sid = simd_index;
assign gpr_if.req_data.wis = staging_if.data.wis;
assign gpr_if.req_data.reg_id = src_regs[opd_id];
// operands fetch response
reg [NUM_SRC_OPDS-1:0][`SIMD_WIDTH-1:0][`XLEN-1:0] opd_values;
@ -163,15 +163,15 @@ module VX_opc_unit import VX_gpu_pkg::*; #(
opd_values[i] <= '0;
end
end else begin
if (col_rsp_fire) begin
opd_values[opc_if.rsp_data.opd_id] <= opc_if.rsp_data.value;
if (gpr_rsp_fire) begin
opd_values[gpr_if.rsp_data.opd_id] <= gpr_if.rsp_data.value;
end
end
end
// output scheduler info
assign sid = simd_index;
assign wis = staging_if.data.wis;
assign pending_sid = simd_index;
assign pending_wis = staging_if.data.wis;
always @(*) begin
pending_regs = '0;
for (integer i = 0; i < NUM_SRC_OPDS; ++i) begin

12
hw/rtl/core/VX_operands.sv
View file

@ -36,11 +36,11 @@ module VX_operands import VX_gpu_pkg::*; #(
);
`UNUSED_SPARAM (INSTANCE_ID)
localparam NUM_OPDS = NUM_SRC_OPDS + 1;
localparam NUM_OPDS = NUM_SRC_OPDS + 1;
localparam SCB_DATAW = UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + PC_BITS + EX_BITS + INST_OP_BITS + INST_ARGS_BITS + NUM_OPDS + (REG_IDX_BITS * NUM_OPDS);
localparam OPD_DATAW = UUID_WIDTH + ISSUE_WIS_W + SIMD_IDX_W + `SIMD_WIDTH + PC_BITS + EX_BITS + INST_OP_BITS + INST_ARGS_BITS + 1 + NR_BITS + (NUM_SRC_OPDS * `SIMD_WIDTH * `XLEN);
VX_opc_if opc_if[`NUM_OPCS]();
VX_gpr_if per_opc_gpr_if[`NUM_OPCS]();
VX_scoreboard_if per_opc_scoreboard_if[`NUM_OPCS]();
VX_operands_if per_opc_operands_if[`NUM_OPCS]();
@ -72,11 +72,11 @@ module VX_operands import VX_gpu_pkg::*; #(
) opc_unit (
.clk (clk),
.reset (reset),
.sid (per_opc_sid[i]),
.wis (per_opc_wis[i]),
.pending_sid (per_opc_sid[i]),
.pending_wis (per_opc_wis[i]),
.pending_regs (per_opc_pending_regs[i]),
.scoreboard_if(per_opc_scoreboard_if[i]),
.opc_if (opc_if[i]),
.gpr_if (per_opc_gpr_if[i]),
.operands_if (per_opc_operands_if[i])
);
end
@ -116,7 +116,7 @@ module VX_operands import VX_gpu_pkg::*; #(
.perf_stalls (perf_stalls),
`endif
.writeback_if (writeback_if_s),
.opc_if (opc_if)
.gpr_if (per_opc_gpr_if)
);
`ITF_TO_AOS (per_opc_operands_if, per_opc_operands, `NUM_OPCS, OPD_DATAW)

2
hw/rtl/interfaces/VX_opc_if.sv → hw/rtl/interfaces/VX_gpr_if.sv
View file

@ -13,7 +13,7 @@
`include "VX_define.vh"
interface VX_opc_if import VX_gpu_pkg::*; ();
interface VX_gpr_if import VX_gpu_pkg::*; ();
typedef struct packed {
logic [SRC_OPD_WIDTH-1:0] opd_id;