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rtl tree refactoring

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This commit is contained in:
Blaise Tine 2023-05-28 22:31:51 -04:00
parent a4b3ba93e0
commit 9a37ab130a
100 changed files with 92 additions and 97 deletions
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16
docs/codebase.md
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@ -6,10 +6,10 @@ The directory/file layout of the Vortex codebase is as followed:
- `rtl`: hardware rtl sources
- `core`: core pipeline
- `cache`: cache subsystem
- `fpu_unit`: floating point unit
- `raster_unit`: graphics rasterizer unit
- `rop_unit`: graphics render output unit
- `tex_unit`: graphics texture sampling unit
- `fpu`: floating point unit
- `raster`: graphics rasterizer unit
- `rop`: graphics render output unit
- `tex`: graphics texture sampling unit
- `interfaces`: interfaces for inter-module communication
- `libs`: general-purpose RTL modules
- `syn`: synthesis directory
@ -19,14 +19,14 @@ The directory/file layout of the Vortex codebase is as followed:
- `modelsim`: Modelsim synthesis scripts
- `yosys`: Yosys synthesis scripts
- `unit_tests`: unit tests for some hardware components
- `runtime`: host runtime software API
- `runtime`: host runtime software APIs
- `include`: Vortex driver public headers
- `stub`: Vortex stub driver library
- `opae`: software driver that uses Intel OPAE API with device targets=fpga|asesim|opaesim
- `xrt`: software driver that uses Xilinx XRT API with device targets=hw|hw_emu|sw_emu
- `rtlsim`: software driver that uses rtlsim simulator
- `simx`: software driver that uses simX simulator
- `kernel`: GPU kernel software API
- `kernel`: GPU kernel software APIs
- `include`: Vortex runtime public headers
- `linker`: linker file for compiling kernels
- `src`: runtime implementation
@ -35,9 +35,9 @@ The directory/file layout of the Vortex codebase is as followed:
- `rtlsim`: processor RTL simulator
- `simX`: cycle approximate simulator for vortex
- `tests`: tests repository.
- `riscv`: RISC-V conformance tests
- `kernel`: kernel tests
- `regression`: regression tests
- `riscv`: RISC-V standard tests
- `regression`: regression tests
- `opencl`: opencl benchmarks and tests
- `ci`: continuous integration scripts
- `miscs`: miscellaneous resources.

0
hw/rtl/fpu_unit/VX_fpu_agent.sv → hw/rtl/fpu/VX_fpu_agent.sv
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hw/rtl/fpu_unit/VX_fpu_agent_if.sv → hw/rtl/fpu/VX_fpu_agent_if.sv
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hw/rtl/fpu_unit/VX_fpu_arb.sv → hw/rtl/fpu/VX_fpu_arb.sv
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hw/rtl/fpu_unit/VX_fpu_class.sv → hw/rtl/fpu/VX_fpu_class.sv
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hw/rtl/fpu_unit/VX_fpu_cvt.sv → hw/rtl/fpu/VX_fpu_cvt.sv
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hw/rtl/fpu_unit/VX_fpu_define.vh → hw/rtl/fpu/VX_fpu_define.vh
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hw/rtl/fpu_unit/VX_fpu_div.sv → hw/rtl/fpu/VX_fpu_div.sv
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hw/rtl/fpu_unit/VX_fpu_dpi.sv → hw/rtl/fpu/VX_fpu_dpi.sv
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hw/rtl/fpu_unit/VX_fpu_fma.sv → hw/rtl/fpu/VX_fpu_fma.sv
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hw/rtl/fpu_unit/VX_fpu_fpga.sv → hw/rtl/fpu/VX_fpu_fpga.sv
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hw/rtl/fpu_unit/VX_fpu_fpnew.sv → hw/rtl/fpu/VX_fpu_fpnew.sv
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hw/rtl/fpu_unit/VX_fpu_ncomp.sv → hw/rtl/fpu/VX_fpu_ncomp.sv
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hw/rtl/fpu_unit/VX_fpu_req_if.sv → hw/rtl/fpu/VX_fpu_req_if.sv
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hw/rtl/fpu_unit/VX_fpu_rounding.sv → hw/rtl/fpu/VX_fpu_rounding.sv
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hw/rtl/fpu_unit/VX_fpu_rsp_if.sv → hw/rtl/fpu/VX_fpu_rsp_if.sv
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hw/rtl/fpu_unit/VX_fpu_sqrt.sv → hw/rtl/fpu/VX_fpu_sqrt.sv
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hw/rtl/fpu_unit/VX_fpu_to_csr_if.sv → hw/rtl/fpu/VX_fpu_to_csr_if.sv
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hw/rtl/fpu_unit/VX_fpu_types.vh → hw/rtl/fpu/VX_fpu_types.vh
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hw/rtl/fpu_unit/VX_fpu_unit.sv → hw/rtl/fpu/VX_fpu_unit.sv
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hw/rtl/raster_unit/VX_raster_agent.sv → hw/rtl/raster/VX_raster_agent.sv
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hw/rtl/raster_unit/VX_raster_agent_if.sv → hw/rtl/raster/VX_raster_agent_if.sv
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hw/rtl/raster_unit/VX_raster_arb.sv → hw/rtl/raster/VX_raster_arb.sv
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hw/rtl/raster_unit/VX_raster_be.sv → hw/rtl/raster/VX_raster_be.sv
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hw/rtl/raster_unit/VX_raster_csr.sv → hw/rtl/raster/VX_raster_csr.sv
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hw/rtl/raster_unit/VX_raster_dcr.sv → hw/rtl/raster/VX_raster_dcr.sv
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hw/rtl/raster_unit/VX_raster_define.vh → hw/rtl/raster/VX_raster_define.vh
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hw/rtl/raster_unit/VX_raster_edge.sv → hw/rtl/raster/VX_raster_edge.sv
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hw/rtl/raster_unit/VX_raster_extents.sv → hw/rtl/raster/VX_raster_extents.sv
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hw/rtl/raster_unit/VX_raster_mem.sv → hw/rtl/raster/VX_raster_mem.sv
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hw/rtl/raster_unit/VX_raster_perf_if.sv → hw/rtl/raster/VX_raster_perf_if.sv
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hw/rtl/raster_unit/VX_raster_qe.sv → hw/rtl/raster/VX_raster_qe.sv
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hw/rtl/raster_unit/VX_raster_req_if.sv → hw/rtl/raster/VX_raster_req_if.sv
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hw/rtl/raster_unit/VX_raster_slice.sv → hw/rtl/raster/VX_raster_slice.sv
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hw/rtl/raster_unit/VX_raster_te.sv → hw/rtl/raster/VX_raster_te.sv
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hw/rtl/raster_unit/VX_raster_types.vh → hw/rtl/raster/VX_raster_types.vh
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hw/rtl/raster_unit/VX_raster_unit.sv → hw/rtl/raster/VX_raster_unit.sv
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hw/rtl/rop_unit/VX_rop_agent.sv → hw/rtl/rop/VX_rop_agent.sv
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hw/rtl/rop_unit/VX_rop_agent_if.sv → hw/rtl/rop/VX_rop_agent_if.sv
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hw/rtl/rop_unit/VX_rop_arb.sv → hw/rtl/rop/VX_rop_arb.sv
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hw/rtl/rop_unit/VX_rop_blend.sv → hw/rtl/rop/VX_rop_blend.sv
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hw/rtl/rop_unit/VX_rop_blend_func.sv → hw/rtl/rop/VX_rop_blend_func.sv
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hw/rtl/rop_unit/VX_rop_blend_minmax.sv → hw/rtl/rop/VX_rop_blend_minmax.sv
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hw/rtl/rop_unit/VX_rop_blend_multadd.sv → hw/rtl/rop/VX_rop_blend_multadd.sv
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hw/rtl/rop_unit/VX_rop_compare.sv → hw/rtl/rop/VX_rop_compare.sv
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hw/rtl/rop_unit/VX_rop_csr.sv → hw/rtl/rop/VX_rop_csr.sv
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hw/rtl/rop_unit/VX_rop_dcr.sv → hw/rtl/rop/VX_rop_dcr.sv
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hw/rtl/rop_unit/VX_rop_define.vh → hw/rtl/rop/VX_rop_define.vh
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hw/rtl/rop_unit/VX_rop_ds.sv → hw/rtl/rop/VX_rop_ds.sv
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hw/rtl/rop_unit/VX_rop_logic_op.sv → hw/rtl/rop/VX_rop_logic_op.sv
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hw/rtl/rop_unit/VX_rop_mem.sv → hw/rtl/rop/VX_rop_mem.sv
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hw/rtl/rop_unit/VX_rop_perf_if.sv → hw/rtl/rop/VX_rop_perf_if.sv
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hw/rtl/rop_unit/VX_rop_req_if.sv → hw/rtl/rop/VX_rop_req_if.sv
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hw/rtl/rop_unit/VX_rop_stencil_op.sv → hw/rtl/rop/VX_rop_stencil_op.sv
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hw/rtl/rop_unit/VX_rop_types.vh → hw/rtl/rop/VX_rop_types.vh
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hw/rtl/rop_unit/VX_rop_unit.sv → hw/rtl/rop/VX_rop_unit.sv
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hw/rtl/tex_unit/VX_tex_addr.sv → hw/rtl/tex/VX_tex_addr.sv
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hw/rtl/tex_unit/VX_tex_agent.sv → hw/rtl/tex/VX_tex_agent.sv
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hw/rtl/tex_unit/VX_tex_agent_if.sv → hw/rtl/tex/VX_tex_agent_if.sv
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hw/rtl/tex_unit/VX_tex_arb.sv → hw/rtl/tex/VX_tex_arb.sv
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hw/rtl/tex_unit/VX_tex_csr.sv → hw/rtl/tex/VX_tex_csr.sv
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hw/rtl/tex_unit/VX_tex_dcr.sv → hw/rtl/tex/VX_tex_dcr.sv
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hw/rtl/tex_unit/VX_tex_define.vh → hw/rtl/tex/VX_tex_define.vh
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hw/rtl/tex_unit/VX_tex_format.sv → hw/rtl/tex/VX_tex_format.sv
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hw/rtl/tex_unit/VX_tex_lerp.sv → hw/rtl/tex/VX_tex_lerp.sv
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hw/rtl/tex_unit/VX_tex_mem.sv → hw/rtl/tex/VX_tex_mem.sv
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hw/rtl/tex_unit/VX_tex_perf_if.sv → hw/rtl/tex/VX_tex_perf_if.sv
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hw/rtl/tex_unit/VX_tex_req_if.sv → hw/rtl/tex/VX_tex_req_if.sv
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hw/rtl/tex_unit/VX_tex_rsp_if.sv → hw/rtl/tex/VX_tex_rsp_if.sv
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hw/rtl/tex_unit/VX_tex_sampler.sv → hw/rtl/tex/VX_tex_sampler.sv
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hw/rtl/tex_unit/VX_tex_sat.sv → hw/rtl/tex/VX_tex_sat.sv
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hw/rtl/tex_unit/VX_tex_stride.sv → hw/rtl/tex/VX_tex_stride.sv
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hw/rtl/tex_unit/VX_tex_types.vh → hw/rtl/tex/VX_tex_types.vh
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hw/rtl/tex_unit/VX_tex_unit.sv → hw/rtl/tex/VX_tex_unit.sv
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hw/rtl/tex_unit/VX_tex_wrap.sv → hw/rtl/tex/VX_tex_wrap.sv
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8
hw/syn/altera/opae/Makefile
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@ -57,10 +57,10 @@ CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

39
hw/syn/altera/quartus/Makefile
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@ -4,7 +4,7 @@ BUILD_DIR=$(PREFIX)_$(DEVICE_FAMILY)
IP_CACHE_DIR=../ip_cache/$(DEVICE_FAMILY)
.PHONY: dogfood unittest pipeline smem cache fpu_unit tex_unit raster_unit rop_unit core vortex vortex-gfx top top-gfx texunit test
.PHONY: dogfood unittest pipeline smem cache fpu tex raster rop core vortex vortex-gfx top top-gfx test
ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log:
@ -35,25 +35,25 @@ cache:
cp cache/Makefile cache/$(BUILD_DIR)
$(MAKE) -C cache/$(BUILD_DIR) clean && $(MAKE) -C cache/$(BUILD_DIR) > cache/$(BUILD_DIR)/build.log 2>&1 &
fpu-unit: ip-gen
mkdir -p fpu_unit/$(BUILD_DIR)
cp fpu_unit/Makefile fpu_unit/$(BUILD_DIR)
$(MAKE) -C fpu_unit/$(BUILD_DIR) clean && $(MAKE) -C fpu_unit/$(BUILD_DIR) > fpu_unit/$(BUILD_DIR)/build.log 2>&1 &
fpu: ip-gen
mkdir -p fpu/$(BUILD_DIR)
cp fpu/Makefile fpu/$(BUILD_DIR)
$(MAKE) -C fpu/$(BUILD_DIR) clean && $(MAKE) -C fpu/$(BUILD_DIR) > fpu/$(BUILD_DIR)/build.log 2>&1 &
tex-unit:
mkdir -p tex_unit/$(BUILD_DIR)
cp tex_unit/Makefile tex_unit/$(BUILD_DIR)
$(MAKE) -C tex_unit/$(BUILD_DIR) clean && $(MAKE) -C tex_unit/$(BUILD_DIR) > tex_unit/$(BUILD_DIR)/build.log 2>&1 &
tex:
mkdir -p tex/$(BUILD_DIR)
cp tex/Makefile tex/$(BUILD_DIR)
$(MAKE) -C tex/$(BUILD_DIR) clean && $(MAKE) -C tex/$(BUILD_DIR) > tex/$(BUILD_DIR)/build.log 2>&1 &
rop-unit:
mkdir -p rop_unit/$(BUILD_DIR)
cp rop_unit/Makefile rop_unit/$(BUILD_DIR)
$(MAKE) -C rop_unit/$(BUILD_DIR) clean && $(MAKE) -C rop_unit/$(BUILD_DIR) > rop_unit/$(BUILD_DIR)/build.log 2>&1 &
rop:
mkdir -p rop/$(BUILD_DIR)
cp rop/Makefile rop/$(BUILD_DIR)
$(MAKE) -C rop/$(BUILD_DIR) clean && $(MAKE) -C rop/$(BUILD_DIR) > rop/$(BUILD_DIR)/build.log 2>&1 &
raster-unit:
mkdir -p raster_unit/$(BUILD_DIR)
cp raster_unit/Makefile raster_unit/$(BUILD_DIR)
$(MAKE) -C raster_unit/$(BUILD_DIR) clean && $(MAKE) -C raster_unit/$(BUILD_DIR) > raster_unit/$(BUILD_DIR)/build.log 2>&1 &
raster:
mkdir -p raster/$(BUILD_DIR)
cp raster/Makefile raster/$(BUILD_DIR)
$(MAKE) -C raster/$(BUILD_DIR) clean && $(MAKE) -C raster/$(BUILD_DIR) > raster/$(BUILD_DIR)/build.log 2>&1 &
core:
mkdir -p core/$(BUILD_DIR)
@ -80,11 +80,6 @@ top-gfx: ip-gen
cp top-gfx/Makefile top-gfx/$(BUILD_DIR)
$(MAKE) -C top-gfx/$(BUILD_DIR) clean && $(MAKE) -C top-gfx/$(BUILD_DIR) > top-gfx/$(BUILD_DIR)/build.log 2>&1 &
texunit:
mkdir -p texunit/$(BUILD_DIR)
cp texunit/Makefile texunit/$(BUILD_DIR)
$(MAKE) -C texunit/$(BUILD_DIR) clean && $(MAKE) -C texunit/$(BUILD_DIR) > texunit/$(BUILD_DIR)/build.log 2>&1 &
test: ip-gen
mkdir -p test/$(BUILD_DIR)
cp test/Makefile test/$(BUILD_DIR)

4
hw/syn/altera/quartus/core/Makefile
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@ -6,6 +6,6 @@ include ../../common.mk
CONFIGS += -DEXT_GFX_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex_unit -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

2
hw/syn/altera/quartus/fpu_unit/Makefile
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@ -4,5 +4,5 @@ SRC_FILE = $(PROJECT).sv
include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)

2
hw/syn/altera/quartus/raster_unit/Makefile
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@ -4,5 +4,5 @@ SRC_FILE = VX_raster_unit.sv
include ../../common.mk
TEX_INCLUDE = -I$(RTL_DIR)/raster_unit
TEX_INCLUDE = -I$(RTL_DIR)/raster
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/rop_unit/Makefile
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@ -4,5 +4,5 @@ SRC_FILE = VX_rop_unit.sv
include ../../common.mk
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(ROP_INCLUDE)

4
hw/syn/altera/quartus/test/Makefile
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@ -6,6 +6,6 @@ include ../../common.mk
CONFIGS += -DEXT_GFX_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex_unit -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

2
hw/syn/altera/quartus/tex_unit/Makefile
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@ -4,5 +4,5 @@ SRC_FILE = VX_tex_unit.sv
include ../../common.mk
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache $(FPU_INCLUDE) $(TEX_INCLUDE)

4
hw/syn/altera/quartus/top-gfx/Makefile
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@ -16,6 +16,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DSM_DISABLE
#CONFIGS += -DRCACHE_DISABLE -DOCACHE_DISABLE -DTCACHE_DISABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

4
hw/syn/altera/quartus/top/Makefile
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@ -13,6 +13,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DL1_DISABLE
#CONFIGS += -DSM_DISABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

4
hw/syn/altera/quartus/unittest/Makefile
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@ -4,6 +4,6 @@ SRC_FILE = $(PROJECT).sv
include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

4
hw/syn/altera/quartus/vortex-gfx/Makefile
View file

@ -20,6 +20,6 @@ CONFIGS += -DNUM_CORES=2
CONFIGS += -DL2_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex_unit -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

4
hw/syn/altera/quartus/vortex/Makefile
View file

@ -16,6 +16,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

8
hw/syn/xilinx/test/Makefile
View file

@ -5,10 +5,10 @@ AFU_DIR = $(RTL_DIR)/afu/xrt
SCRIPT_DIR = ../../../scripts
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -Iproject_1_files

8
hw/syn/xilinx/xrt/Makefile
View file

@ -76,10 +76,10 @@ CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR)
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

2
hw/unit_tests/imadd/Makefile
View file

@ -2,7 +2,7 @@
default: verilate build
verilate:
verilator -cc --trace ../../rtl/VX_imadd.sv -I../../rtl -I../../../.. -I../../../../dpi -I../../../common -I../../rtl/fpu_unit -v ../../rtl/libs/VX_multiplier.sv ../../rtl/libs/VX_shift_register.sv ../../rtl/libs/VX_pipe_register.sv --exe imadd_tb.cpp
verilator -cc --trace ../../rtl/VX_imadd.sv -I../../rtl -I../../../.. -I../../../../dpi -I../../../common -I../../rtl/fpu -v ../../rtl/libs/VX_multiplier.sv ../../rtl/libs/VX_shift_register.sv ../../rtl/libs/VX_pipe_register.sv --exe imadd_tb.cpp
build:
make -C obj_dir -f VVX_imadd.mk

8
hw/unit_tests/raster_unit/be/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/raster_unit/extents/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/raster_unit/qe/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/raster_unit/raster_slice/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/raster_unit/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster -I$(RTL_DIR)/raster/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/raster_unit/te/arbiter/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/raster_unit/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster -I$(RTL_DIR)/raster/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/raster_unit/te/te/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit -I$(RTL_DIR)/raster_unit/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster -I$(RTL_DIR)/raster/tile_evaluator
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE) -I$(DPI_DIR)/..
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
hw/unit_tests/tex_unit/tex_sampler/Makefile
View file

@ -21,10 +21,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)

8
sim/opaesim/Makefile
View file

@ -45,10 +45,10 @@ SRCS = ../common/util.cpp ../common/mem.cpp ../common/rvfloats.cpp
SRCS += $(DPI_DIR)/util_dpi.cpp $(DPI_DIR)/float_dpi.cpp
SRCS += fpga.cpp opae_sim.cpp
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
RTL_INCLUDE += -I$(AFU_DIR) -I$(AFU_DIR)/ccip

8
sim/rtlsim/Makefile
View file

@ -31,10 +31,10 @@ DBG_TRACE_FLAGS += -DDBG_TRACE_ROP
DBG_FLAGS += -DDEBUG_LEVEL=$(DEBUG) -DVCD_OUTPUT $(DBG_TRACE_FLAGS)
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(RTL_DIR)/simulate $(FPU_INCLUDE)
RTL_INCLUDE += $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)