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felsabbagh3 2019-10-17 11:51:11 -04:00
parent e8a43fa7a9
commit 9bf186fc77
6 changed files with 9 additions and 468 deletions
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102
rtl/VX_context.v
View file

@ -1,102 +0,0 @@
`include "VX_define.v"
module VX_context (
input wire clk,
/* verilator lint_off UNUSED */
input wire in_warp,
/* verilator lint_on UNUSED */
input wire in_wb_warp,
input wire[`NT_M1:0] in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[`NT_M1:0][31:0] in_write_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_is_clone,
input wire in_src1_fwd,
input wire[`NT_M1:0][31:0] in_src1_fwd_data,
input wire in_src2_fwd,
input wire[`NT_M1:0][31:0] in_src2_fwd_data,
output reg[`NT_M1:0][31:0] out_a_reg_data,
output reg[`NT_M1:0][31:0] out_b_reg_data,
output wire out_clone_stall,
output wire[31:0][31:0] w0_t0_registers
);
reg[5:0] state_stall;
initial begin
state_stall = 0;
end
wire[`NT_M1:0][31:0] rd1_register;
wire[`NT_M1:0][31:0] rd2_register;
/* verilator lint_off UNUSED */
wire[31:0][31:0] clone_regsiters;
/* verilator lint_on UNUSED */
assign w0_t0_registers = clone_regsiters;
VX_register_file vx_register_file_master(
.clk (clk),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_warp (in_warp),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_clone (in_is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
always @(posedge clk) begin
if ((in_is_clone) && state_stall == 0) begin
state_stall <= 10;
end else if (state_stall == 1) begin
state_stall <= 0;
end else if (state_stall > 0) begin
state_stall <= state_stall - 1;
end
end
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]);
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
assign out_clone_stall = ((state_stall == 0) && in_is_clone) || ((state_stall != 1) && in_is_clone);
endmodule

145
rtl/VX_context_slave.v
View file

@ -1,145 +0,0 @@
`include "VX_define.v"
module VX_context_slave (
input wire clk,
/* verilator lint_off UNUSED */
input wire in_warp,
/* verilator lint_on UNUSED */
input wire in_wb_warp,
input wire[`NT_M1:0] in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[`NT_M1:0][31:0] in_write_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_is_clone,
input wire in_src1_fwd,
input wire[`NT_M1:0][31:0] in_src1_fwd_data,
input wire in_src2_fwd,
input wire[`NT_M1:0][31:0] in_src2_fwd_data,
input wire[31:0][31:0] in_wspawn_regs,
input wire in_wspawn,
output reg[`NT_M1:0][31:0] out_a_reg_data,
output reg[`NT_M1:0][31:0] out_b_reg_data,
output wire out_clone_stall
);
wire[`NT_M1:0][31:0] rd1_register;
wire[`NT_M1:0][31:0] rd2_register;
/* verilator lint_off UNUSED */
wire[31:0][31:0] clone_regsiters;
/* verilator lint_on UNUSED */
reg[5:0] clone_state_stall = 0;
reg[5:0] wspawn_state_stall = 0;
initial begin
clone_state_stall = 0;
wspawn_state_stall = 0;
end
wire to_wspawn = wspawn_state_stall == 2;
// always @(*) begin
// if (to_wspawn)
// $display("-----> to_wspawn == 1");
// end
VX_register_file_master_slave vx_register_file_master(
.clk (clk),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_wspawn (in_wspawn),
.in_to_wspawn (to_wspawn),
.in_wspawn_regs (in_wspawn_regs),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (clone_state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_warp (in_warp),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_clone (in_is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
// always @(*) begin
// if (in_valid[0] && in_valid[1]) begin
// $display("Reg write: %h %h", in_write_data[0], in_write_data[1]);
// end else if (in_valid[0]) begin
// $display("Reg write: %h", in_write_data[0]);
// end
// end
// for clone
always @(posedge clk) begin
if ((in_is_clone) && clone_state_stall == 0) begin
clone_state_stall <= 10;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
end else if (clone_state_stall == 1) begin
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, in_is_clone);
clone_state_stall <= 0;
end else if (clone_state_stall > 0) begin
clone_state_stall <= clone_state_stall - 1;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
end
end
// for wspawn
always @(posedge clk) begin
if ((in_wspawn) && wspawn_state_stall == 0) begin
wspawn_state_stall <= 10;
// $display("starting wspawn stalling -- in_wspawn: %d -- stall %d", in_wspawn, wspwan_stall);
end else if (wspawn_state_stall == 1) begin
// $display("ENDING wspawn stalling -- in_wspawn %d -- stall: %d", in_wspawn, wspwan_stall);
wspawn_state_stall <= 0;
end else if (wspawn_state_stall > 0) begin
wspawn_state_stall <= wspawn_state_stall - 1;
// $display("wspawn state: %d in_wspawn: %d -- stall: %d", wspawn_state_stall, in_wspawn, wspwan_stall);
end
end
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]);
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
wire clone_stall = ((clone_state_stall == 0) && in_is_clone) || ((clone_state_stall != 1) && in_is_clone);
wire wspwan_stall = ((wspawn_state_stall == 0) && in_wspawn) || (wspawn_state_stall > 1);
assign out_clone_stall = clone_stall || wspwan_stall;
endmodule

16
rtl/VX_gpr_stage.v
View file

@ -47,7 +47,7 @@ module VX_gpr_stage (
assign VX_gpr_jal.curr_PC = VX_bckE_req.curr_PC;
VX_gpr_data_inter VX_gpr_datf;
VX_gpr_data_inter VX_gpr_datf();
VX_gpr_wrapper vx_grp_wrapper(
@ -65,12 +65,14 @@ module VX_gpr_stage (
// assign VX_bckE_req.is_csr = is_csr;
// assign VX_bckE_req_out.csr_mask = (VX_bckE_req.sr_immed == 1'b1) ? {27'h0, VX_bckE_req.rs1} : VX_gpr_data.a_reg_data[0];
wire zero_temp = 0;
VX_generic_register #(.N(256)) reg_data
(
.clk (clk),
.reset(0),
.stall(0),
.flush(0),
.reset(zero_temp),
.stall(zero_temp),
.flush(zero_temp),
.in ({VX_gpr_datf.a_reg_data, VX_gpr_datf.b_reg_data}),
.out ({VX_gpr_data.a_reg_data, VX_gpr_data.b_reg_data})
);
@ -79,10 +81,10 @@ module VX_gpr_stage (
VX_d_e_reg gpr_stage_reg(
.clk (clk),
.reset (0),
.reset (zero_temp),
.in_fwd_stall (stall),
.in_branch_stall (0),
.in_freeze (0),
.in_branch_stall (zero_temp),
.in_freeze (zero_temp),
.in_gpr_stall (out_gpr_stall),
.VX_frE_to_bckE_req(VX_bckE_req),
.VX_bckE_req (VX_bckE_req_out)

68
rtl/VX_register_file.v
View file

@ -1,68 +0,0 @@
module VX_register_file (
input wire clk,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
output wire[31:0][31:0] out_regs,
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data
);
reg[31:0][31:0] registers;
wire[31:0] write_data;
wire[4:0] write_register;
wire write_enable;
reg[5:0] i;
always @(posedge clk) begin
$display("*************");
if (write_enable && in_wb_warp)
$display("writing: %d = %h",in_rd, in_data);
for (i = 0; i < 32; i++) begin
if (registers[i[4:0]] != 0)
$display("%d: %h",i, registers[i[4:0]]);
end
end
// always @(*) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
assign out_regs = registers;
assign write_data = in_data;
assign write_register = in_rd;
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid;
always @(posedge clk) begin
if(write_enable && in_wb_warp) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end
end
// always @(negedge clk) begin
assign out_src1_data = registers[in_src1];
assign out_src2_data = registers[in_src2];
// end
always @(*) begin
$display("Reading Data 1: %d = %h",in_src1, out_src1_data);
$display("Reading Data 2: %d = %h",in_src2, out_src2_data);
end
endmodule

72
rtl/VX_register_file_master_slave.v
View file

@ -1,72 +0,0 @@
module VX_register_file_master_slave (
input wire clk,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_wspawn,
input wire in_to_wspawn,
input wire[31:0][31:0] in_wspawn_regs,
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data,
output wire[31:0][31:0] out_regs
);
reg[31:0][31:0] registers;
wire[31:0] write_data;
wire[4:0] write_register;
wire write_enable;
assign out_regs = registers;
// reg[5:0] i;
// always @(posedge clk) begin
// for (i = 0; i < 32; i++) begin
// $display("%d: %h",i, registers[i[4:0]]);
// end
// end
// integer i;
assign write_data = in_data;
assign write_register = in_rd;
// always @(*) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
always @(posedge clk) begin
if(write_enable && !in_wspawn) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_wspawn && in_to_wspawn) begin
// $display("WSPAWN IN MASTER SLAVE");
registers <= in_wspawn_regs;
end
end
// always @(posedge clk) begin
// for (i = 0; i < 32; i = i + 1)
// $display("(%d): %x", i, registers[i]);
// end
always @(negedge clk) begin
out_src1_data <= registers[in_src1];
out_src2_data <= registers[in_src2];
end
endmodule

74
rtl/VX_register_file_slave.v
View file

@ -1,74 +0,0 @@
module VX_register_file_slave (
input wire clk,
input wire in_warp,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_clone,
input wire in_to_clone,
input wire[31:0][31:0] in_regs,
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data
);
reg[31:0][31:0] registers;
wire[31:0] write_data;
wire[4:0] write_register;
wire write_enable;
// reg[5:0] i;
// always @(posedge clk) begin
// for (i = 0; i < 32; i++) begin
// $display("%d: %h",i, registers[i[4:0]]);
// end
// end
// integer i;
// always @(*) begin
// if (in_warp) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
// end
assign write_data = in_data;
assign write_register = in_rd;
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
always @(posedge clk) begin
if(write_enable && !in_clone) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_clone && in_to_clone && in_warp) begin
registers <= in_regs;
end
end
// always @(posedge clk) begin
// for (i = 0; i < 32; i = i + 1)
// $display("(%d): %x", i, registers[i]);
// end
always @(negedge clk) begin
out_src1_data <= registers[in_src1];
out_src2_data <= registers[in_src2];
end
endmodule