github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

bram reset fix

Browse source
This commit is contained in:
Blaise Tine 2024-08-02 18:13:58 -07:00
parent c1b8ecfd1a
commit 9c5aee5e25
4 changed files with 10 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -91,9 +91,10 @@ module VX_cache_data #(
.SIZE (`CS_LINES_PER_BANK)
) byteen_store (
.clk (clk),
.reset (1'b0),
.read (write || fill || flush),
.write (init || write || fill || flush),
`UNUSED_PIN (wren),
.wren (1'b1),
.addr (line_sel),
.wdata (bs_wdata),
.rdata (bs_rdata)
@ -161,6 +162,7 @@ module VX_cache_data #(
.RW_ASSERT (1)
) data_store (
.clk (clk),
.reset (1'b0),
.read (line_read),
.write (line_write),
.wren (line_wren),

3
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -130,9 +130,10 @@ module VX_cache_tags #(
.RW_ASSERT (1)
) tag_store (
.clk (clk),
.reset (1'b0),
.read (line_read),
.write (line_write),
`UNUSED_PIN (wren),
.wren (1'b1),
.addr (line_sel),
.wdata (line_wdata),
.rdata (line_rdata)

4
hw/rtl/libs/VX_sp_ram.sv
View file

@ -23,12 +23,14 @@ module VX_sp_ram #(
parameter NO_RWCHECK = 0,
parameter RW_ASSERT = 0,
parameter LUTRAM = 0,
parameter RESET_RAM = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
parameter ADDRW = `LOG2UP(SIZE)
) (
input wire clk,
input wire reset,
input wire read,
input wire write,
input wire [WRENW-1:0] wren,
@ -45,12 +47,14 @@ module VX_sp_ram #(
.NO_RWCHECK (NO_RWCHECK),
.RW_ASSERT (RW_ASSERT),
.LUTRAM (LUTRAM),
.RESET_RAM (RESET_RAM),
.INIT_ENABLE (INIT_ENABLE),
.INIT_FILE (INIT_FILE),
.INIT_VALUE (INIT_VALUE),
.ADDRW (ADDRW)
) dp_ram (
.clk (clk),
.reset (reset),
.read (read),
.write (write),
.wren (wren),

1
hw/rtl/mem/VX_local_mem.sv
View file

@ -166,6 +166,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
.WRENW (WORD_SIZE)
) data_store (
.clk (clk),
.reset (1'b0),
.read (1'b1),
.write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]),
.wren (per_bank_req_byteen[i]),