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xilixn simulation doesn't support tasks in header files.

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This commit is contained in:
Blaise Tine 2023-03-29 03:27:25 -04:00
parent 1d1a778dc0
commit 9d3bec9e74
13 changed files with 221 additions and 259 deletions
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2
hw/rtl/VX_dcr_data.sv
View file

@ -39,7 +39,7 @@ module VX_dcr_data (
always @(posedge clk) begin
if (dcr_write_if.valid) begin
`TRACE(1, ("%d: base-dcr: state=", $time));
trace_base_dcr(1, dcr_write_if.addr);
`TRACE_BASE_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
end
end

296
hw/rtl/VX_trace_info.vh
View file

@ -3,162 +3,148 @@
`include "VX_define.vh"
task trace_ex_type (
input int level,
input [`EX_BITS-1:0] ex_type
);
case (ex_type)
`EX_ALU: `TRACE(level, ("ALU"));
`EX_LSU: `TRACE(level, ("LSU"));
`EX_CSR: `TRACE(level, ("CSR"));
`EX_FPU: `TRACE(level, ("FPU"));
`EX_GPU: `TRACE(level, ("GPU"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_EX_TYPE(level, ex_type) \
case (ex_type) \
`EX_ALU: `TRACE(level, ("ALU")); \
`EX_LSU: `TRACE(level, ("LSU")); \
`EX_CSR: `TRACE(level, ("CSR")); \
`EX_FPU: `TRACE(level, ("FPU")); \
`EX_GPU: `TRACE(level, ("GPU")); \
default: `TRACE(level, ("?")); \
endcase
task trace_ex_op (
input int level,
input [`EX_BITS-1:0] ex_type,
input [`INST_OP_BITS-1:0] op_type,
input [`INST_MOD_BITS-1:0] op_mod
);
case (ex_type)
`EX_ALU: begin
if (`INST_ALU_IS_BR(op_mod)) begin
case (`INST_BR_BITS'(op_type))
`INST_BR_EQ: `TRACE(level, ("BEQ"));
`INST_BR_NE: `TRACE(level, ("BNE"));
`INST_BR_LT: `TRACE(level, ("BLT"));
`INST_BR_GE: `TRACE(level, ("BGE"));
`INST_BR_LTU: `TRACE(level, ("BLTU"));
`INST_BR_GEU: `TRACE(level, ("BGEU"));
`INST_BR_JAL: `TRACE(level, ("JAL"));
`INST_BR_JALR: `TRACE(level, ("JALR"));
`INST_BR_ECALL: `TRACE(level, ("ECALL"));
`INST_BR_EBREAK:`TRACE(level, ("EBREAK"));
`INST_BR_URET: `TRACE(level, ("URET"));
`INST_BR_SRET: `TRACE(level, ("SRET"));
`INST_BR_MRET: `TRACE(level, ("MRET"));
default: `TRACE(level, ("?"));
endcase
end else if (`INST_ALU_IS_MUL(op_mod)) begin
case (`INST_MUL_BITS'(op_type))
`INST_MUL_MUL: `TRACE(level, ("MUL"));
`INST_MUL_MULH: `TRACE(level, ("MULH"));
`INST_MUL_MULHSU:`TRACE(level, ("MULHSU"));
`INST_MUL_MULHU: `TRACE(level, ("MULHU"));
`INST_MUL_DIV: `TRACE(level, ("DIV"));
`INST_MUL_DIVU: `TRACE(level, ("DIVU"));
`INST_MUL_REM: `TRACE(level, ("REM"));
`INST_MUL_REMU: `TRACE(level, ("REMU"));
default: `TRACE(level, ("?"));
endcase
end else begin
case (`INST_ALU_BITS'(op_type))
`INST_ALU_ADD: `TRACE(level, ("ADD"));
`INST_ALU_SUB: `TRACE(level, ("SUB"));
`INST_ALU_SLL: `TRACE(level, ("SLL"));
`INST_ALU_SRL: `TRACE(level, ("SRL"));
`INST_ALU_SRA: `TRACE(level, ("SRA"));
`INST_ALU_SLT: `TRACE(level, ("SLT"));
`INST_ALU_SLTU: `TRACE(level, ("SLTU"));
`INST_ALU_XOR: `TRACE(level, ("XOR"));
`INST_ALU_OR: `TRACE(level, ("OR"));
`INST_ALU_AND: `TRACE(level, ("AND"));
`INST_ALU_LUI: `TRACE(level, ("LUI"));
`INST_ALU_AUIPC: `TRACE(level, ("AUIPC"));
default: `TRACE(level, ("?"));
endcase
end
end
`EX_LSU: begin
if (op_mod == 0) begin
case (`INST_LSU_BITS'(op_type))
`INST_LSU_LB: `TRACE(level, ("LB"));
`INST_LSU_LH: `TRACE(level, ("LH"));
`INST_LSU_LW: `TRACE(level, ("LW"));
`INST_LSU_LBU:`TRACE(level, ("LBU"));
`INST_LSU_LHU:`TRACE(level, ("LHU"));
`INST_LSU_SB: `TRACE(level, ("SB"));
`INST_LSU_SH: `TRACE(level, ("SH"));
`INST_LSU_SW: `TRACE(level, ("SW"));
default: `TRACE(level, ("?"));
endcase
end else if (op_mod == 1) begin
case (`INST_FENCE_BITS'(op_type))
`INST_FENCE_D: `TRACE(level, ("DFENCE"));
`INST_FENCE_I: `TRACE(level, ("IFENCE"));
default: `TRACE(level, ("?"));
endcase
end
end
`EX_CSR: begin
case (`INST_CSR_BITS'(op_type))
`INST_CSR_RW: `TRACE(level, ("CSRW"));
`INST_CSR_RS: `TRACE(level, ("CSRS"));
`INST_CSR_RC: `TRACE(level, ("CSRC"));
default: `TRACE(level, ("?"));
endcase
end
`EX_FPU: begin
case (`INST_FPU_BITS'(op_type))
`INST_FPU_ADD: `TRACE(level, ("ADD"));
`INST_FPU_SUB: `TRACE(level, ("SUB"));
`INST_FPU_MUL: `TRACE(level, ("MUL"));
`INST_FPU_DIV: `TRACE(level, ("DIV"));
`INST_FPU_SQRT: `TRACE(level, ("SQRT"));
`INST_FPU_MADD: `TRACE(level, ("MADD"));
`INST_FPU_NMSUB: `TRACE(level, ("NMSUB"));
`INST_FPU_NMADD: `TRACE(level, ("NMADD"));
`INST_FPU_CVTWS: `TRACE(level, ("CVTWS"));
`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS"));
`INST_FPU_CVTSW: `TRACE(level, ("CVTSW"));
`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU"));
`INST_FPU_CLASS: `TRACE(level, ("CLASS"));
`INST_FPU_CMP: `TRACE(level, ("CMP"));
`INST_FPU_MISC: begin
case (op_mod)
0: `TRACE(level, ("SGNJ"));
1: `TRACE(level, ("SGNJN"));
2: `TRACE(level, ("SGNJX"));
3: `TRACE(level, ("MIN"));
4: `TRACE(level, ("MAX"));
5: `TRACE(level, ("MVXW"));
6: `TRACE(level, ("MVWX"));
endcase
end
default: `TRACE(level, ("?"));
endcase
end
`EX_GPU: begin
case (`INST_GPU_BITS'(op_type))
`INST_GPU_TMC: `TRACE(level, ("TMC"));
`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN"));
`INST_GPU_SPLIT: `TRACE(level, ("SPLIT"));
`INST_GPU_JOIN: `TRACE(level, ("JOIN"));
`INST_GPU_BAR: `TRACE(level, ("BAR"));
`INST_GPU_PRED: `TRACE(level, ("PRED"));
`INST_GPU_TEX: `TRACE(level, ("TEX"));
`INST_GPU_RASTER:`TRACE(level, ("RASTER"));
`INST_GPU_ROP: `TRACE(level, ("ROP"));
`INST_GPU_IMADD: `TRACE(level, ("IMADD"));
default: `TRACE(level, ("?"));
endcase
end
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_EX_OP(level, ex_type, op_type, op_mod) \
case (ex_type) \
`EX_ALU: begin \
if (`INST_ALU_IS_BR(op_mod)) begin \
case (`INST_BR_BITS'(op_type)) \
`INST_BR_EQ: `TRACE(level, ("BEQ")); \
`INST_BR_NE: `TRACE(level, ("BNE")); \
`INST_BR_LT: `TRACE(level, ("BLT")); \
`INST_BR_GE: `TRACE(level, ("BGE")); \
`INST_BR_LTU: `TRACE(level, ("BLTU")); \
`INST_BR_GEU: `TRACE(level, ("BGEU")); \
`INST_BR_JAL: `TRACE(level, ("JAL")); \
`INST_BR_JALR: `TRACE(level, ("JALR")); \
`INST_BR_ECALL: `TRACE(level, ("ECALL")); \
`INST_BR_EBREAK:`TRACE(level, ("EBREAK")); \
`INST_BR_URET: `TRACE(level, ("URET")); \
`INST_BR_SRET: `TRACE(level, ("SRET")); \
`INST_BR_MRET: `TRACE(level, ("MRET")); \
default: `TRACE(level, ("?")); \
endcase \
end else if (`INST_ALU_IS_MUL(op_mod)) begin \
case (`INST_MUL_BITS'(op_type)) \
`INST_MUL_MUL: `TRACE(level, ("MUL")); \
`INST_MUL_MULH: `TRACE(level, ("MULH")); \
`INST_MUL_MULHSU:`TRACE(level, ("MULHSU")); \
`INST_MUL_MULHU: `TRACE(level, ("MULHU")); \
`INST_MUL_DIV: `TRACE(level, ("DIV")); \
`INST_MUL_DIVU: `TRACE(level, ("DIVU")); \
`INST_MUL_REM: `TRACE(level, ("REM")); \
`INST_MUL_REMU: `TRACE(level, ("REMU")); \
default: `TRACE(level, ("?")); \
endcase \
end else begin \
case (`INST_ALU_BITS'(op_type)) \
`INST_ALU_ADD: `TRACE(level, ("ADD")); \
`INST_ALU_SUB: `TRACE(level, ("SUB")); \
`INST_ALU_SLL: `TRACE(level, ("SLL")); \
`INST_ALU_SRL: `TRACE(level, ("SRL")); \
`INST_ALU_SRA: `TRACE(level, ("SRA")); \
`INST_ALU_SLT: `TRACE(level, ("SLT")); \
`INST_ALU_SLTU: `TRACE(level, ("SLTU")); \
`INST_ALU_XOR: `TRACE(level, ("XOR")); \
`INST_ALU_OR: `TRACE(level, ("OR")); \
`INST_ALU_AND: `TRACE(level, ("AND")); \
`INST_ALU_LUI: `TRACE(level, ("LUI")); \
`INST_ALU_AUIPC: `TRACE(level, ("AUIPC")); \
default: `TRACE(level, ("?")); \
endcase \
end \
end \
`EX_LSU: begin \
if (op_mod == 0) begin \
case (`INST_LSU_BITS'(op_type)) \
`INST_LSU_LB: `TRACE(level, ("LB")); \
`INST_LSU_LH: `TRACE(level, ("LH")); \
`INST_LSU_LW: `TRACE(level, ("LW")); \
`INST_LSU_LBU:`TRACE(level, ("LBU")); \
`INST_LSU_LHU:`TRACE(level, ("LHU")); \
`INST_LSU_SB: `TRACE(level, ("SB")); \
`INST_LSU_SH: `TRACE(level, ("SH")); \
`INST_LSU_SW: `TRACE(level, ("SW")); \
default: `TRACE(level, ("?")); \
endcase \
end else if (op_mod == 1) begin \
case (`INST_FENCE_BITS'(op_type)) \
`INST_FENCE_D: `TRACE(level, ("DFENCE")); \
`INST_FENCE_I: `TRACE(level, ("IFENCE")); \
default: `TRACE(level, ("?")); \
endcase \
end \
end \
`EX_CSR: begin \
case (`INST_CSR_BITS'(op_type)) \
`INST_CSR_RW: `TRACE(level, ("CSRW")); \
`INST_CSR_RS: `TRACE(level, ("CSRS")); \
`INST_CSR_RC: `TRACE(level, ("CSRC")); \
default: `TRACE(level, ("?")); \
endcase \
end \
`EX_FPU: begin \
case (`INST_FPU_BITS'(op_type)) \
`INST_FPU_ADD: `TRACE(level, ("ADD")); \
`INST_FPU_SUB: `TRACE(level, ("SUB")); \
`INST_FPU_MUL: `TRACE(level, ("MUL")); \
`INST_FPU_DIV: `TRACE(level, ("DIV")); \
`INST_FPU_SQRT: `TRACE(level, ("SQRT")); \
`INST_FPU_MADD: `TRACE(level, ("MADD")); \
`INST_FPU_NMSUB: `TRACE(level, ("NMSUB")); \
`INST_FPU_NMADD: `TRACE(level, ("NMADD")); \
`INST_FPU_CVTWS: `TRACE(level, ("CVTWS")); \
`INST_FPU_CVTWUS:`TRACE(level, ("CVTWUS")); \
`INST_FPU_CVTSW: `TRACE(level, ("CVTSW")); \
`INST_FPU_CVTSWU:`TRACE(level, ("CVTSWU")); \
`INST_FPU_CLASS: `TRACE(level, ("CLASS")); \
`INST_FPU_CMP: `TRACE(level, ("CMP")); \
`INST_FPU_MISC: begin \
case (op_mod) \
0: `TRACE(level, ("SGNJ")); \
1: `TRACE(level, ("SGNJN")); \
2: `TRACE(level, ("SGNJX")); \
3: `TRACE(level, ("MIN")); \
4: `TRACE(level, ("MAX")); \
5: `TRACE(level, ("MVXW")); \
6: `TRACE(level, ("MVWX")); \
endcase \
end \
default: `TRACE(level, ("?")); \
endcase \
end \
`EX_GPU: begin \
case (`INST_GPU_BITS'(op_type)) \
`INST_GPU_TMC: `TRACE(level, ("TMC")); \
`INST_GPU_WSPAWN:`TRACE(level, ("WSPAWN")); \
`INST_GPU_SPLIT: `TRACE(level, ("SPLIT")); \
`INST_GPU_JOIN: `TRACE(level, ("JOIN")); \
`INST_GPU_BAR: `TRACE(level, ("BAR")); \
`INST_GPU_PRED: `TRACE(level, ("PRED")); \
`INST_GPU_TEX: `TRACE(level, ("TEX")); \
`INST_GPU_RASTER:`TRACE(level, ("RASTER")); \
`INST_GPU_ROP: `TRACE(level, ("ROP")); \
`INST_GPU_IMADD: `TRACE(level, ("IMADD")); \
default: `TRACE(level, ("?")); \
endcase \
end \
default: `TRACE(level, ("?")); \
endcase
task trace_base_dcr (
input int level,
input [`DCR_ADDR_BITS-1:0] addr
);
case (addr)
`DCR_BASE_STARTUP_ADDR: `TRACE(level, ("STARTUP_ADDR"));
`DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_BASE_DCR(level, addr) \
case (addr) \
`DCR_BASE_STARTUP_ADDR: `TRACE(level, ("STARTUP_ADDR")); \
`DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS")); \
default: `TRACE(level, ("?")); \
endcase
`endif

4
hw/rtl/core/VX_decode.sv
View file

@ -488,9 +488,9 @@ module VX_decode #(
always @(posedge clk) begin
if (decode_if.valid && decode_if.ready) begin
`TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, decode_if.wid, decode_if.PC));
trace_ex_type(1, decode_if.ex_type);
`TRACE_EX_TYPE(1, decode_if.ex_type);
`TRACE(1, (", op="));
trace_ex_op(1, decode_if.ex_type, decode_if.op_type, decode_if.op_mod);
`TRACE_EX_OP(1, decode_if.ex_type, decode_if.op_type, decode_if.op_mod);
`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, use_pc=%b, use_imm=%b (#%0d)\n",
decode_if.op_mod, decode_if.tmask, decode_if.wb, decode_if.rd, decode_if.rs1, decode_if.rs2, decode_if.rs3, decode_if.imm, decode_if.use_PC, decode_if.use_imm, decode_if.uuid));
end

4
hw/rtl/core/VX_issue.sv
View file

@ -251,9 +251,9 @@ module VX_issue #(
always @(posedge clk) begin
if (dispatch_if.valid && dispatch_if.ready) begin
`TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, dispatch_if.wid, dispatch_if.PC));
trace_ex_type(1, dispatch_if.ex_type);
`TRACE_EX_TYPE(1, dispatch_if.ex_type);
`TRACE(1, (", op="));
trace_ex_op(1, dispatch_if.ex_type, dispatch_if.op_type, dispatch_if.op_mod);
`TRACE_EX_OP(1, dispatch_if.ex_type, dispatch_if.op_type, dispatch_if.op_mod);
`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", dispatch_if.op_mod, dispatch_if.tmask, dispatch_if.wb, dispatch_if.rd));
`TRACE_ARRAY1D(1, gpr_rsp_if.rs1_data, `NUM_THREADS);
`TRACE(1, (", rs2_data="));

2
hw/rtl/raster_unit/VX_raster_csr.sv
View file

@ -95,7 +95,7 @@ module VX_raster_csr #(
always @(posedge clk) begin
if (raster_csr_if.read_enable) begin
`TRACE(1, ("%d: core%0d-raster-csr-read: wid=%0d, tmask=%b, state=", $time, CORE_ID, raster_csr_if.read_wid, raster_csr_if.read_tmask));
trace_raster_csr(1, raster_csr_if.read_addr);
`TRACE_RASTER_CSR(1, raster_csr_if.read_addr);
`TRACE(1, (", data="));
`TRACE_ARRAY1D(1, raster_csr_if.read_data, `NUM_THREADS);
`TRACE(1, (" (#%0d)\n", raster_csr_if.read_uuid));

2
hw/rtl/raster_unit/VX_raster_dcr.sv
View file

@ -54,7 +54,7 @@ module VX_raster_dcr #(
always @(posedge clk) begin
if (dcr_write_if.valid) begin
`TRACE(1, ("%d: %s-raster-dcr: state=", $time, INSTANCE_ID));
trace_raster_state(1, dcr_write_if.addr);
`TRACE_RASTER_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
end
end

62
hw/rtl/raster_unit/VX_raster_define.vh
View file

@ -21,42 +21,34 @@ import VX_raster_types::*;
assign dst[1][2] = eval[1]; \
assign dst[2][2] = eval[2]
task trace_raster_state (
input int level,
input [`DCR_ADDR_BITS-1:0] state
);
case (state)
`DCR_RASTER_TBUF_ADDR: `TRACE(level, ("TBUF_ADDR"));
`DCR_RASTER_TILE_COUNT: `TRACE(level, ("TILE_COUNT"));
`DCR_RASTER_PBUF_ADDR: `TRACE(level, ("PBUF_ADDR"));
`DCR_RASTER_PBUF_STRIDE: `TRACE(level, ("PBUF_STRIDE"));
`DCR_RASTER_SCISSOR_X: `TRACE(level, ("SCISSOR_X"));
`DCR_RASTER_SCISSOR_Y: `TRACE(level, ("SCISSOR_Y"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_RASTER_DCR(level, state) \
case (state) \
`DCR_RASTER_TBUF_ADDR: `TRACE(level, ("TBUF_ADDR")); \
`DCR_RASTER_TILE_COUNT: `TRACE(level, ("TILE_COUNT")); \
`DCR_RASTER_PBUF_ADDR: `TRACE(level, ("PBUF_ADDR")); \
`DCR_RASTER_PBUF_STRIDE: `TRACE(level, ("PBUF_STRIDE")); \
`DCR_RASTER_SCISSOR_X: `TRACE(level, ("SCISSOR_X")); \
`DCR_RASTER_SCISSOR_Y: `TRACE(level, ("SCISSOR_Y")); \
default: `TRACE(level, ("?")); \
endcase
task trace_raster_csr (
input int level,
input [`CSR_ADDR_BITS-1:0] addr
);
case (addr)
`CSR_RASTER_POS_MASK: `TRACE(level, ("POS_MASK"));
`CSR_RASTER_BCOORD_X0: `TRACE(level, ("BCOORD_X0"));
`CSR_RASTER_BCOORD_X1: `TRACE(level, ("BCOORD_X1"));
`CSR_RASTER_BCOORD_X2: `TRACE(level, ("BCOORD_X2"));
`CSR_RASTER_BCOORD_X3: `TRACE(level, ("BCOORD_X3"));
`CSR_RASTER_BCOORD_Y0: `TRACE(level, ("BCOORD_Y0"));
`CSR_RASTER_BCOORD_Y1: `TRACE(level, ("BCOORD_Y1"));
`CSR_RASTER_BCOORD_Y2: `TRACE(level, ("BCOORD_Y2"));
`CSR_RASTER_BCOORD_Y3: `TRACE(level, ("BCOORD_Y3"));
`CSR_RASTER_BCOORD_Z0: `TRACE(level, ("BCOORD_Z0"));
`CSR_RASTER_BCOORD_Z1: `TRACE(level, ("BCOORD_Z1"));
`CSR_RASTER_BCOORD_Z2: `TRACE(level, ("BCOORD_Z2"));
`CSR_RASTER_BCOORD_Z3: `TRACE(level, ("BCOORD_Z3"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_RASTER_CSR(level, addr) \
case (addr) \
`CSR_RASTER_POS_MASK: `TRACE(level, ("POS_MASK")); \
`CSR_RASTER_BCOORD_X0: `TRACE(level, ("BCOORD_X0")); \
`CSR_RASTER_BCOORD_X1: `TRACE(level, ("BCOORD_X1")); \
`CSR_RASTER_BCOORD_X2: `TRACE(level, ("BCOORD_X2")); \
`CSR_RASTER_BCOORD_X3: `TRACE(level, ("BCOORD_X3")); \
`CSR_RASTER_BCOORD_Y0: `TRACE(level, ("BCOORD_Y0")); \
`CSR_RASTER_BCOORD_Y1: `TRACE(level, ("BCOORD_Y1")); \
`CSR_RASTER_BCOORD_Y2: `TRACE(level, ("BCOORD_Y2")); \
`CSR_RASTER_BCOORD_Y3: `TRACE(level, ("BCOORD_Y3")); \
`CSR_RASTER_BCOORD_Z0: `TRACE(level, ("BCOORD_Z0")); \
`CSR_RASTER_BCOORD_Z1: `TRACE(level, ("BCOORD_Z1")); \
`CSR_RASTER_BCOORD_Z2: `TRACE(level, ("BCOORD_Z2")); \
`CSR_RASTER_BCOORD_Z3: `TRACE(level, ("BCOORD_Z3")); \
default: `TRACE(level, ("?")); \
endcase
`define PERF_RASTER_ADD(dst, src, count) \
`REDUCE_ADD (dst, src, mem_reads, `PERF_CTR_BITS, count); \

2
hw/rtl/rop_unit/VX_rop_csr.sv
View file

@ -51,7 +51,7 @@ module VX_rop_csr #(
always @(posedge clk) begin
if (rop_csr_if.write_enable) begin
`TRACE(1, ("%d: core%0d-rop-csr-write: wid=%0d, tmask=%b, state=", $time, CORE_ID, rop_csr_if.write_wid, rop_csr_if.write_tmask));
trace_rop_csr(1, rop_csr_if.write_addr);
`TRACE_ROP_CSR(1, rop_csr_if.write_addr);
`TRACE(1, (", data="));
`TRACE_ARRAY1D(1, rop_csr_if.write_data, `NUM_THREADS);
`TRACE(1, (" (#%0d)\n", rop_csr_if.write_uuid));

2
hw/rtl/rop_unit/VX_rop_dcr.sv
View file

@ -125,7 +125,7 @@ module VX_rop_dcr #(
always @(posedge clk) begin
if (dcr_write_if.valid) begin
`TRACE(1, ("%d: %s-rop-dcr: state=", $time, INSTANCE_ID));
trace_rop_state(1, dcr_write_if.addr);
`TRACE_ROP_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
end
end

64
hw/rtl/rop_unit/VX_rop_define.vh
View file

@ -10,43 +10,35 @@ import VX_gpu_types::*;
import VX_rop_types::*;
`IGNORE_WARNINGS_END
task trace_rop_state (
input int level,
input [`DCR_ADDR_BITS-1:0] state
);
case (state)
`DCR_ROP_CBUF_ADDR: `TRACE(level, ("CBUF_ADDR"));
`DCR_ROP_CBUF_PITCH: `TRACE(level, ("CBUF_PITCH"));
`DCR_ROP_CBUF_WRITEMASK: `TRACE(level, ("CBUF_WRITEMASK"));
`DCR_ROP_ZBUF_ADDR: `TRACE(level, ("ZBUF_ADDR"));
`DCR_ROP_ZBUF_PITCH: `TRACE(level, ("ZBUF_PITCH"));
`DCR_ROP_DEPTH_FUNC: `TRACE(level, ("DEPTH_FUNC"));
`DCR_ROP_DEPTH_WRITEMASK: `TRACE(level, ("DEPTH_WRITEMASK"));
`DCR_ROP_STENCIL_FUNC: `TRACE(level, ("STENCIL_FUNC"));
`DCR_ROP_STENCIL_ZPASS: `TRACE(level, ("STENCIL_ZPASS"));
`DCR_ROP_STENCIL_ZFAIL: `TRACE(level, ("STENCIL_ZFAIL"));
`DCR_ROP_STENCIL_FAIL: `TRACE(level, ("STENCIL_FAIL"));
`DCR_ROP_STENCIL_REF: `TRACE(level, ("STENCIL_REF"));
`DCR_ROP_STENCIL_MASK: `TRACE(level, ("STENCIL_MASK"));
`DCR_ROP_STENCIL_WRITEMASK: `TRACE(level, ("STENCIL_WRITEMASK"));
`DCR_ROP_BLEND_MODE: `TRACE(level, ("BLEND_MODE"));
`DCR_ROP_BLEND_FUNC: `TRACE(level, ("BLEND_FUNC"));
`DCR_ROP_BLEND_CONST: `TRACE(level, ("BLEND_CONST"));
`DCR_ROP_LOGIC_OP: `TRACE(level, ("LOGIC_OP"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_ROP_DCR(level, state) \
case (state) \
`DCR_ROP_CBUF_ADDR: `TRACE(level, ("CBUF_ADDR")); \
`DCR_ROP_CBUF_PITCH: `TRACE(level, ("CBUF_PITCH")); \
`DCR_ROP_CBUF_WRITEMASK: `TRACE(level, ("CBUF_WRITEMASK")); \
`DCR_ROP_ZBUF_ADDR: `TRACE(level, ("ZBUF_ADDR")); \
`DCR_ROP_ZBUF_PITCH: `TRACE(level, ("ZBUF_PITCH")); \
`DCR_ROP_DEPTH_FUNC: `TRACE(level, ("DEPTH_FUNC")); \
`DCR_ROP_DEPTH_WRITEMASK: `TRACE(level, ("DEPTH_WRITEMASK")); \
`DCR_ROP_STENCIL_FUNC: `TRACE(level, ("STENCIL_FUNC")); \
`DCR_ROP_STENCIL_ZPASS: `TRACE(level, ("STENCIL_ZPASS")); \
`DCR_ROP_STENCIL_ZFAIL: `TRACE(level, ("STENCIL_ZFAIL")); \
`DCR_ROP_STENCIL_FAIL: `TRACE(level, ("STENCIL_FAIL")); \
`DCR_ROP_STENCIL_REF: `TRACE(level, ("STENCIL_REF")); \
`DCR_ROP_STENCIL_MASK: `TRACE(level, ("STENCIL_MASK")); \
`DCR_ROP_STENCIL_WRITEMASK: `TRACE(level, ("STENCIL_WRITEMASK")); \
`DCR_ROP_BLEND_MODE: `TRACE(level, ("BLEND_MODE")); \
`DCR_ROP_BLEND_FUNC: `TRACE(level, ("BLEND_FUNC")); \
`DCR_ROP_BLEND_CONST: `TRACE(level, ("BLEND_CONST")); \
`DCR_ROP_LOGIC_OP: `TRACE(level, ("LOGIC_OP")); \
default: `TRACE(level, ("?")); \
endcase
task trace_rop_csr (
input int level,
input [`CSR_ADDR_BITS-1:0] addr
);
case (addr)
`CSR_ROP_RT_IDX: `TRACE(level, ("RT_IDX"));
`CSR_ROP_SAMPLE_IDX: `TRACE(level, ("SAMPLE_IDX"));
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_ROP_CSR(level, addr) \
case (addr) \
`CSR_ROP_RT_IDX: `TRACE(level, ("RT_IDX")); \
`CSR_ROP_SAMPLE_IDX: `TRACE(level, ("SAMPLE_IDX")); \
default: `TRACE(level, ("?")); \
endcase
`define PERF_ROP_ADD(dst, src, count) \
`REDUCE_ADD (dst, src, mem_reads, `PERF_CTR_BITS, count); \

2
hw/rtl/tex_unit/VX_tex_csr.sv
View file

@ -50,7 +50,7 @@ module VX_tex_csr #(
always @(posedge clk) begin
if (tex_csr_if.write_enable) begin
`TRACE(1, ("%d: core%0d-tex-csr-write: wid=%0d, tmask=%b, state=", $time, CORE_ID, tex_csr_if.write_wid, tex_csr_if.write_tmask));
trace_tex_csr(1, tex_csr_if.write_addr);
`TRACE_TEX_CSR(1, tex_csr_if.write_addr);
`TRACE(1, (", data="));
`TRACE_ARRAY1D(1, tex_csr_if.write_data, `NUM_THREADS);
`TRACE(1, (" (#%0d)\n", tex_csr_if.write_uuid));

2
hw/rtl/tex_unit/VX_tex_dcr.sv
View file

@ -68,7 +68,7 @@ module VX_tex_dcr #(
always @(posedge clk) begin
if (dcr_write_if.valid) begin
`TRACE(1, ("%d: %s-tex-dcr: stage=%0d, state=", $time, INSTANCE_ID, dcr_stage));
trace_tex_dcr(1, dcr_write_if.addr);
`TRACE_TEX_DCR(1, dcr_write_if.addr);
`TRACE(1, (", data=0x%0h\n", dcr_write_if.data));
end
end

36
hw/rtl/tex_unit/VX_tex_define.vh
View file

@ -10,29 +10,21 @@ import VX_gpu_types::*;
import VX_tex_types::*;
`IGNORE_WARNINGS_END
task trace_tex_dcr (
input int level,
input [`DCR_ADDR_BITS-1:0] addr
);
case (addr)
`DCR_TEX_ADDR: `TRACE(level, ("ADDR"));
`DCR_TEX_LOGDIM: `TRACE(level, ("LOGDIM"));
`DCR_TEX_FORMAT: `TRACE(level, ("FORMAT"));
`DCR_TEX_FILTER: `TRACE(level, ("FILTER"));
`DCR_TEX_WRAP: `TRACE(level, ("WRAP"));
//`DCR_TEX_MIPOFF
default: `TRACE(level, ("MIPOFF"));
endcase
endtask
`define TRACE_TEX_DCR(level, addr) \
case (addr) \
`DCR_TEX_ADDR: `TRACE(level, ("ADDR")); \
`DCR_TEX_LOGDIM: `TRACE(level, ("LOGDIM")); \
`DCR_TEX_FORMAT: `TRACE(level, ("FORMAT")); \
`DCR_TEX_FILTER: `TRACE(level, ("FILTER")); \
`DCR_TEX_WRAP: `TRACE(level, ("WRAP")); \
//`DCR_TEX_MIPOFF \
default: `TRACE(level, ("MIPOFF")); \
endcase
task trace_tex_csr (
input int level,
input [`CSR_ADDR_BITS-1:0] addr
);
case (addr)
default: `TRACE(level, ("?"));
endcase
endtask
`define TRACE_TEX_CSR(level, addr) \
case (addr) \
default: `TRACE(level, ("?")); \
endcase
`define PERF_TEX_ADD(dst, src, count) \
`REDUCE_ADD (dst, src, mem_reads, `PERF_CTR_BITS, count); \