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Moving from one-hot to binary muxing optimization

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FPGA synthesis is suboptimal with one-hot muxing, particularly Xilinx Vivado.
This change fixed Xilinx synthesis for 256-thread cores.
This commit is contained in:
Blaise Tine 2024-08-06 12:32:02 -07:00
parent b81ae8e431
commit 9dcb377b67
2 changed files with 6 additions and 22 deletions
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10
hw/rtl/libs/VX_stream_arb.sv
View file

@ -174,17 +174,9 @@ module VX_stream_arb #(
);
assign valid_in_r = arb_valid;
assign data_in_r = data_in[arb_index];
assign arb_ready = ready_in_r;
VX_onehot_mux #(
.DATAW (DATAW),
.N (NUM_REQS)
) onehot_mux (
.data_in (data_in),
.sel_in (arb_onehot),
.data_out (data_in_r)
);
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign ready_in[i] = ready_in_r && arb_onehot[i];
end

18
hw/rtl/libs/VX_stream_pack.sv
View file

@ -39,8 +39,9 @@ module VX_stream_pack #(
input wire ready_out
);
if (NUM_REQS > 1) begin
localparam LOG_NUM_REQS = `CLOG2(NUM_REQS);
wire [NUM_REQS-1:0] grant_onehot;
wire [LOG_NUM_REQS-1:0] grant_index;
wire grant_valid;
wire grant_ready;
@ -52,21 +53,12 @@ module VX_stream_pack #(
.reset (reset),
.requests (valid_in),
.grant_valid (grant_valid),
`UNUSED_PIN (grant_index),
.grant_onehot(grant_onehot),
.grant_index (grant_index),
`UNUSED_PIN (grant_onehot),
.grant_ready (grant_ready)
);
wire [TAG_WIDTH-1:0] tag_sel;
VX_onehot_mux #(
.DATAW (TAG_WIDTH),
.N (NUM_REQS)
) onehot_mux (
.data_in (tag_in),
.sel_in (grant_onehot),
.data_out (tag_sel)
);
wire [TAG_WIDTH-1:0] tag_sel = tag_in[grant_index];
wire [NUM_REQS-1:0] tag_matches;