mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
This commit is contained in:
codetector
commit
9ee12d4a01
8 changed files with 203 additions and 44 deletions
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@ -281,7 +281,6 @@ begin
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avs_writedata <= 0;
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avs_read <= 0;
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avs_write <= 0;
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avs_read_ctr <= 0;
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avs_write_ctr <= 0;
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end
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@ -323,9 +322,7 @@ begin
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STATE_RUN: begin
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if (vx_dram_req_read
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&& !avs_waitrequest
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&& !avs_raq_full
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&& !avs_rdq_full)
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&& !vx_dram_req_delay)
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begin
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avs_address <= (vx_dram_req_addr >> 6);
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avs_read <= 1;
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@ -333,7 +330,7 @@ begin
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end
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if (vx_dram_req_write
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&& !avs_waitrequest)
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&& !vx_dram_req_delay)
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begin
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avs_writedata <= {>>{vx_dram_req_data}};
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avs_address <= (vx_dram_req_addr >> 6);
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@ -345,19 +342,22 @@ begin
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if (avs_readdatavalid)
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begin
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$display("%t: AVS Rd Rsp: value=%h", $time, avs_readdata[63:0]);
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$display("%t: AVS Rd Rsp", $time);
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end
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end
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end
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// Vortex DRAM requests stalling
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assign vx_dram_req_delay = !(avs_read || avs_write);
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assign vx_dram_req_delay = !((STATE_RUN == state)
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&& !avs_waitrequest
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&& !avs_raq_full
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&& !avs_rdq_full);
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// Vortex DRAM fill response
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always_comb
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begin
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vx_dram_fill_rsp = (STATE_RUN == state) && !avs_rdq_empty && vx_dram_fill_accept;
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vx_dram_fill_rsp_addr = avs_raq_dout;
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vx_dram_fill_rsp_addr = (avs_raq_dout << 6);
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{>>{vx_dram_fill_rsp_data}} = avs_rdq_dout;
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end
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@ -369,7 +369,7 @@ always_comb
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begin
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avs_raq_pop = vx_dram_fill_rsp || cci_write_req;
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avs_raq_din = avs_address;
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avs_raq_push = avs_write;
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avs_raq_push = avs_read;
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end
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VX_generic_queue_ll #(
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@ -463,10 +463,10 @@ logic cci_write_pending;
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always_comb
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begin
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cci_write_req = (STATE_READ == state)
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_pending
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&& cci_write_ctr < csr_data_size;
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_pending
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&& cci_write_ctr < csr_data_size;
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wr_hdr = t_ccip_c1_ReqMemHdr'(0);
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wr_hdr.address = csr_io_addr + cci_write_ctr;
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64
driver/hw/wave.do
Normal file
64
driver/hw/wave.do
Normal file
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@ -0,0 +1,64 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -label clk /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/clk
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add wave -noupdate -label reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/SoftReset
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add wave -noupdate -label state /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/state
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add wave -noupdate -label cci_write_pending /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_pending
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add wave -noupdate -label cci_write_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_ctr
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add wave -noupdate -label csr_data_size -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/csr_data_size
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add wave -noupdate -label avs_read_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read_ctr
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add wave -noupdate -label avs_waitrequest /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_waitrequest
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add wave -noupdate -label avs_address -radix hexadecimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_address
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add wave -noupdate -label avs_readdata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdata
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add wave -noupdate -label avs_writedata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_writedata
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add wave -noupdate -label avs_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_write
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add wave -noupdate -label avs_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read
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add wave -noupdate -label avs_readdatavalid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdatavalid
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add wave -noupdate -label sRx.c0.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c0.rspValid
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add wave -noupdate -label sRx.c1.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c1.rspValid
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add wave -noupdate -label sTx.c0.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c0.valid
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add wave -noupdate -label sTx.c1.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c1.valid
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add wave -noupdate -label cci_write_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_req
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add wave -noupdate -label avs_raq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_push
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add wave -noupdate -label avs_rdq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_push
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add wave -noupdate -label avs_raq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_pop
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add wave -noupdate -label avs_rdq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_pop
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add wave -noupdate -label avs_raq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_full
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add wave -noupdate -label avs_rdq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_full
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add wave -noupdate -label avs_raq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_empty
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add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_empty
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add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write
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add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay
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add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read
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add wave -noupdate -label vx_reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/reset
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add wave -noupdate -label out_dram_fill_rsp /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_rsp
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add wave -noupdate -label out_dram_fill_accept /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_dram_fill_accept
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add wave -noupdate -label llc_snp_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req
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add wave -noupdate -label llc_snp_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/llc_snp_req_delay
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add wave -noupdate -label out_break /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/out_ebreak
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add wave -noupdate -label warp_pc -radix hexadecimal -radixshowbase 0 {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_pc}
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add wave -noupdate -label scheduled_warp {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/scheduled_warp}
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add wave -noupdate -label thread_mask {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/thread_mask}
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add wave -noupdate -label warp_num {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_num}
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add wave -noupdate -label warp_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_active}
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add wave -noupdate -label warp_stalled {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_stalled}
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add wave -noupdate -label warp_lock {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/warp_lock}
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add wave -noupdate -label use_active {/ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_soc/genblk1/Vortex_Cluster/genblk1[0]/vortex_core/vx_front_end/vx_fetch/warp_scheduler/use_active}
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {66234495 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 195
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ps
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update
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WaveRestoreZoom {66041656 ps} {66406344 ps}
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@ -18,7 +18,7 @@ run-fpga: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
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run-ase: $(PROJECT)
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ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
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ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -t 1
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run-rtlsim: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT)
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@ -114,8 +114,6 @@ module VX_bank
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wire snrq_valid_st0;
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wire[31:0] snrq_addr_st0;
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reg snrq_hazard_st0;
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assign snrq_valid_st0 = !snrq_empty;
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VX_generic_queue_ll #(.DATAW(32), .SIZE(SNRQ_SIZE)) snr_queue(
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.clk (clk),
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@ -133,7 +131,6 @@ module VX_bank
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wire dfpq_full;
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wire[31:0] dfpq_addr_st0;
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wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dfpq_filldata_st0;
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reg dfpq_hazard_st0;
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assign dram_fill_accept = !dfpq_full;
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@ -161,7 +158,6 @@ module VX_bank
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wire [`NW_M1:0] reqq_req_warp_num_st0;
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wire [2:0] reqq_req_mem_read_st0;
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wire [2:0] reqq_req_mem_write_st0;
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reg reqq_hazard_st0;
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wire [31:0] reqq_req_pc_st0;
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assign reqq_push = !delay_req && (|bank_valids);
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@ -229,7 +225,6 @@ module VX_bank
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wire [`NW_M1:0] mrvq_warp_num_st0;
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wire [2:0] mrvq_mem_read_st0;
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wire [2:0] mrvq_mem_write_st0;
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reg mrvq_hazard_st0;
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wire miss_add;
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wire[31:0] miss_add_addr;
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@ -321,28 +316,13 @@ module VX_bank
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// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
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assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
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assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
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assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
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assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe;
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assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe;
|
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assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe;
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assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe;
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|
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integer st1_cycle;
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||||
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always @(*) begin
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dfpq_hazard_st0 = 0;
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mrvq_hazard_st0 = 0;
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reqq_hazard_st0 = 0;
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snrq_hazard_st0 = 0;
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// for (st1_cycle = 0; st1_cycle < STAGE_1_CYCLES; st1_cycle = st1_cycle + 1) begin
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// if (valid_st1[st1_cycle] && going_to_write_st1[st1_cycle]) begin
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// if (dfpq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) dfpq_hazard_st0 = 1;
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// if (mrvq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) mrvq_hazard_st0 = 1;
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// if (reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) reqq_hazard_st0 = 1;
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// if (snrq_addr_st0 [31:`LINE_SELECT_ADDR_START] == addr_st1[st1_cycle][31:`LINE_SELECT_ADDR_START]) snrq_hazard_st0 = 1;
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// end
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// end
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end
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wire qual_is_fill_st0;
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wire qual_valid_st0;
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wire [31:0] qual_addr_st0;
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|
|
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|||
|
|
@ -43,6 +43,10 @@ module VX_cache
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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|
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// Prefetcher
|
||||
parameter PRFQ_SIZE = 64,
|
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parameter PRFQ_STRIDE = 0,
|
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|
||||
// Dram knobs
|
||||
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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|
|
@ -147,7 +151,8 @@ module VX_cache
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|||
assign snp_req_delay = (|per_bank_snrq_full);
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||||
|
||||
assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
|
||||
// assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
|
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assign dram_fill_accept = (|per_bank_dram_fill_accept);
|
||||
|
||||
VX_cache_dram_req_arb #(
|
||||
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
|
||||
|
|
@ -165,6 +170,8 @@ module VX_cache
|
|||
.DFQQ_SIZE (DFQQ_SIZE),
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||||
.LLVQ_SIZE (LLVQ_SIZE),
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||||
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
||||
.PRFQ_SIZE (PRFQ_SIZE),
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||||
.PRFQ_STRIDE (PRFQ_STRIDE),
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||||
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
|
||||
)
|
||||
VX_cache_dram_req_arb
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ module VX_cache_dram_req_arb
|
|||
// Fill Invalidator Size {Fill invalidator must be active}
|
||||
parameter FILL_INVALIDAOR_SIZE = 16,
|
||||
|
||||
// Prefetcher
|
||||
parameter PRFQ_SIZE = 64,
|
||||
parameter PRFQ_STRIDE = 2,
|
||||
|
||||
// Dram knobs
|
||||
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
|
||||
|
||||
|
|
@ -74,6 +78,33 @@ module VX_cache_dram_req_arb
|
|||
|
||||
);
|
||||
|
||||
|
||||
wire pref_pop;
|
||||
wire pref_valid;
|
||||
wire[31:0] pref_addr;
|
||||
|
||||
assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_delay && pref_valid;
|
||||
VX_prefetcher #(
|
||||
.PRFQ_SIZE (PRFQ_SIZE),
|
||||
.PRFQ_STRIDE (PRFQ_STRIDE),
|
||||
.BANK_LINE_SIZE_BYTES(BANK_LINE_SIZE_BYTES),
|
||||
.WORD_SIZE_BYTES (WORD_SIZE_BYTES)
|
||||
)
|
||||
prfqq
|
||||
(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
.dram_req (dram_req && dram_req_read),
|
||||
.dram_req_addr(dram_req_addr),
|
||||
|
||||
.pref_pop (pref_pop),
|
||||
.pref_valid (pref_valid),
|
||||
.pref_addr (pref_addr)
|
||||
|
||||
|
||||
);
|
||||
|
||||
wire dfqq_req;
|
||||
wire[31:0] dfqq_req_addr;
|
||||
wire dfqq_empty;
|
||||
|
|
@ -107,10 +138,10 @@ module VX_cache_dram_req_arb
|
|||
assign per_bank_dram_wb_queue_pop = dram_req_delay ? 0 : use_wb_valid & ((1 << dwb_bank));
|
||||
|
||||
|
||||
assign dram_req = dwb_valid || dfqq_req;
|
||||
assign dram_req = dwb_valid || dfqq_req || pref_pop;
|
||||
assign dram_req_write = dwb_valid;
|
||||
assign dram_req_read = dfqq_req && !dwb_valid;
|
||||
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
|
||||
assign dram_req_read = (dfqq_req && !dwb_valid) || pref_pop;
|
||||
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK;
|
||||
assign dram_req_size = BANK_LINE_SIZE_BYTES;
|
||||
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
|
||||
// assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;
|
||||
|
|
|
|||
77
rtl/VX_cache/VX_prefetcher.v
Normal file
77
rtl/VX_cache/VX_prefetcher.v
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
`include "VX_cache_config.v"
|
||||
|
||||
module VX_prefetcher
|
||||
#(
|
||||
parameter PRFQ_SIZE = 64,
|
||||
parameter PRFQ_STRIDE = 2,
|
||||
// Size of line inside a bank in bytes
|
||||
parameter BANK_LINE_SIZE_BYTES = 16,
|
||||
// Size of a word in bytes
|
||||
parameter WORD_SIZE_BYTES = 4
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
input wire dram_req,
|
||||
input wire[31:0] dram_req_addr,
|
||||
|
||||
input wire pref_pop,
|
||||
output wire pref_valid,
|
||||
output wire[31:0] pref_addr
|
||||
|
||||
);
|
||||
|
||||
|
||||
reg[`vx_clog2(PRFQ_STRIDE):0] use_valid;
|
||||
reg[31:0] use_addr;
|
||||
|
||||
|
||||
wire current_valid;
|
||||
wire[31:0] current_addr;
|
||||
|
||||
wire current_full;
|
||||
wire current_empty;
|
||||
|
||||
|
||||
assign current_valid = ~current_empty;
|
||||
|
||||
wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;
|
||||
|
||||
VX_generic_queue_ll #(.DATAW(32), .SIZE(PRFQ_SIZE)) pfq_queue(
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
||||
.push (dram_req && !current_full && !pref_pop),
|
||||
.in_data (dram_req_addr & `BASE_ADDR_MASK),
|
||||
|
||||
.pop (update_use),
|
||||
.out_data(current_addr),
|
||||
|
||||
.empty (current_empty),
|
||||
.full (current_full)
|
||||
);
|
||||
|
||||
|
||||
|
||||
assign pref_valid = use_valid != 0;
|
||||
assign pref_addr = use_addr;
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
use_valid <= 0;
|
||||
use_addr <= 0;
|
||||
end else begin
|
||||
if (update_use) begin
|
||||
use_valid <= PRFQ_STRIDE;
|
||||
use_addr <= current_addr + BANK_LINE_SIZE_BYTES;
|
||||
end else if (pref_valid && pref_pop) begin
|
||||
use_valid <= use_valid - 1;
|
||||
use_addr <= use_addr + BANK_LINE_SIZE_BYTES;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -234,8 +234,8 @@ int _write (int file, char *buf, int nbytes)
|
|||
|
||||
|
||||
|
||||
static int heap_start = (int) 0x30000000;
|
||||
static int head_end = (int) 0x40000000;
|
||||
static int heap_start = (int) 0x90000000;
|
||||
static int head_end = (int) 0xa0000000;
|
||||
|
||||
void * _sbrk (int nbytes)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue