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fpu timing optimization

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This commit is contained in:
Blaise Tine 2024-09-02 03:11:26 -07:00
parent 40e04a409e
commit a17580375b
6 changed files with 9 additions and 11 deletions
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2
hw/rtl/fpu/VX_fpu_cvt.sv
View file

@ -64,7 +64,7 @@ module VX_fpu_cvt import VX_fpu_pkg::*; #(
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF ((NUM_LANES != NUM_PES) ? 2 : 0)
.OUT_BUF (2)
) pe_serializer (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu/VX_fpu_div.sv
View file

@ -67,8 +67,8 @@ module VX_fpu_div import VX_fpu_pkg::*; #(
.DATA_IN_WIDTH(2*32),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG ((NUM_LANES != NUM_PES) ? 1 : 0), // must be registered for DSPs
.OUT_BUF ((NUM_LANES != NUM_PES) ? 2 : 0)
.PE_REG (0),
.OUT_BUF (2)
) pe_serializer (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -111,9 +111,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
VX_stream_switch #(
.DATAW (REQ_DATAW),
.NUM_INPUTS (1),
.NUM_OUTPUTS (NUM_FPCORES),
.OUT_BUF (0)
.NUM_OUTPUTS (NUM_FPCORES)
) req_switch (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu/VX_fpu_fma.sv
View file

@ -98,8 +98,8 @@ module VX_fpu_fma import VX_fpu_pkg::*; #(
.DATA_IN_WIDTH(3*32),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG ((NUM_LANES != NUM_PES) ? 1 : 0), // must be registered for DSPs
.OUT_BUF ((NUM_LANES != NUM_PES) ? 2 : 0)
.PE_REG (1), // must be registered for DSPs
.OUT_BUF (2)
) pe_serializer (
.clk (clk),
.reset (reset),

2
hw/rtl/fpu/VX_fpu_ncp.sv
View file

@ -69,7 +69,7 @@ module VX_fpu_ncp import VX_fpu_pkg::*; #(
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG (0),
.OUT_BUF ((NUM_LANES != NUM_PES) ? 2 : 0)
.OUT_BUF (2)
) pe_serializer (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu/VX_fpu_sqrt.sv
View file

@ -61,8 +61,8 @@ module VX_fpu_sqrt import VX_fpu_pkg::*; #(
.DATA_IN_WIDTH(32),
.DATA_OUT_WIDTH(`FP_FLAGS_BITS + 32),
.TAG_WIDTH (NUM_LANES + TAG_WIDTH),
.PE_REG ((NUM_LANES != NUM_PES) ? 1 : 0), // must be registered for DSPs
.OUT_BUF ((NUM_LANES != NUM_PES) ? 2 : 0)
.PE_REG (0),
.OUT_BUF (2)
) pe_serializer (
.clk (clk),
.reset (reset),