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rtl cache refactory

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This commit is contained in:
Blaise Tine 2020-04-30 17:12:18 -04:00
parent 814ac50d12
commit a1dc90b951
67 changed files with 51076 additions and 51059 deletions
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2
driver/common/vx_utils.cpp
View file

@ -15,7 +15,7 @@ extern int vx_dev_caps(int caps_id) {
case VX_CAPS_MAX_THREADS:
return NUM_THREADS;
case VX_CAPS_CACHE_LINESIZE:
return GLOBAL_BLOCK_SIZE_BYTES;
return GLOBAL_BLOCK_SIZE;
case VX_CAPS_LOCAL_MEM_SIZE:
return 0xffffffff;
case VX_CAPS_ALLOC_BASE_ADDR:

30
driver/rtlsim/Makefile
View file

@ -1,45 +1,43 @@
CFLAGS += -std=c++11 -O2 -DNDEBUG -Wall -Wextra -Wfatal-errors
# CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -Wfatal-errors
USE_MULTICORE=1
CFLAGS += -I../../include -I../../../hw/simulate -I../../../runtime
MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=2
#DEBUG = 1
CFLAGS += -fPIC
CFLAGS += -DUSE_RTLSIM
CFLAGS += -DUSE_RTLSIM $(MULTICORE)
LDFLAGS += -shared -pthread
ifdef USE_MULTICORE
CFLAGS += -DUSE_MULTICORE
RTL_TOP = Vortex_Socket
else
VL_FLAGS += -DSINGLE_CORE_BENCH
RTL_TOP = Vortex
endif
SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp
RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache
VL_FLAGS += -DNDEBUG --assert -Wall -Wpedantic
VL_FLAGS += --assert -Wall -Wpedantic $(MULTICORE)
# Enable Verilator multithreaded simulation
#THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
#VL_FLAGS += --threads $(THREADS)
# Debugigng
#VL_FLAGS += --trace -DVL_DEBUG=1
#CFLAGS += -DVCD_OUTPUT
ifdef DEBUG
VL_FLAGS += --trace -DVL_DEBUG=1
CFLAGS += -DVCD_OUTPUT
else
CFLAGS += -DNDEBUG
VL_FLAGS += -DNDEBUG
endif
PROJECT = libvortex.so
all: $(PROJECT)
$(PROJECT): $(SRCS)
verilator --exe --cc $(RTL_TOP).v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
make -j -C obj_dir -f V$(RTL_TOP).mk
verilator --exe --cc Vortex_Socket.v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
make -j -C obj_dir -f VVortex_Socket.mk
clean:
rm -rf $(PROJECT) obj_dir

38
hw/Makefile
View file

@ -4,22 +4,16 @@ CF += -std=c++11 -fms-extensions
VF += -compiler gcc --language 1800-2009 --assert -Wall -Wpedantic
VF += -exe $(SRCS) $(INCLUDE)
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate
SINGLE_CORE = Vortex.v
MULTI_CORE = Vortex_Socket.v
SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp
VF += -exe $(SRCS) $(INCLUDE)
DBG += --trace -DVL_DEBUG=1
MAKECPP_S += (cd obj_dir && make -j -f VVortex.mk)
MAKECPP_M += (cd obj_dir && make -j -f VVortex_Socket.mk)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
.PHONY: build_config
@ -28,31 +22,31 @@ build_config:
./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h
gen-singlecore: build_config
verilator $(VF) -DNDEBUG -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG'
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG'
gen-singlecore-t: build_config
verilator $(VF) -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS)
gen-singlecore-d: build_config
verilator $(VF) -cc $(SINGLE_CORE) -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT' $(DBG)
verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT' $(DBG)
gen-multicore: build_config
verilator $(VF) -DNDEBUG -cc $(MULTI_CORE) -CFLAGS '$(CF) -DNDEBUG -DUSE_MULTICORE'
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)'
gen-multicore-t: build_config
verilator $(VF) -DNDEBUG -cc $(MULTI_CORE) -CFLAGS '$(CF) -DNDEBUG -O2 -DUSE_MULTICORE' --threads $(THREADS)
verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS)
gen-multicore-d: build_config
verilator $(VF) -cc $(MULTI_CORE) -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT -DUSE_MULTICORE' $(DBG)
verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 -DVCD_OUTPUT $(MULTICORE)' $(DBG)
singlecore: gen-singlecore
(cd obj_dir && make -j -f VVortex.mk)
(cd obj_dir && make -j -f VVortex_Socket.mk)
singlecore-t: gen-singlecore-t
(cd obj_dir && make -j -f VVortex.mk)
(cd obj_dir && make -j -f VVortex_Socket.mk)
singlecore-d: gen-singlecore-d
(cd obj_dir && make -j -f VVortex.mk)
(cd obj_dir && make -j -f VVortex_Socket.mk)
multicore: gen-multicore
(cd obj_dir && make -j -f VVortex_Socket.mk)
@ -64,13 +58,13 @@ multicore-d: gen-multicore-d
(cd obj_dir && make -j -f VVortex_Socket.mk)
run: singlecore
(cd obj_dir && ./VVortex)
(cd obj_dir && ./VVortex_Socket)
run-d: singlecore-d
(cd obj_dir && ./VVortex)
(cd obj_dir && ./VVortex_Socket)
run-t: singlecore-t
(cd obj_dir && ./VVortex)
(cd obj_dir && ./VVortex_Socket)
run-m: multicore
(cd obj_dir && ./VVortex_Socket)

1
hw/opae/sources.txt
View file

@ -38,7 +38,6 @@ vortex_afu.json
../rtl/interfaces/VX_warp_ctl_if.v
../rtl/interfaces/VX_inst_mem_wb_if.v
../rtl/libs/VX_priority_encoder_w_mask.v
../rtl/libs/VX_generic_register.v
../rtl/libs/VX_mult.v
../rtl/libs/VX_divide.v

4
hw/opae/vortex_afu.sv
View file

@ -70,13 +70,13 @@ state_t state;
logic vx_dram_req_read;
logic vx_dram_req_write;
logic [31:0] vx_dram_req_addr;
logic [`GLOBAL_BLOCK_SIZE_BYTES-1:0] vx_dram_req_data;
logic [`GLOBAL_BLOCK_SIZE-1:0] vx_dram_req_data;
logic vx_dram_req_ready;
logic vx_dram_rsp_ready;
logic vx_dram_rsp_valid;
logic [31:0] vx_dram_rsp_addr;
logic [`GLOBAL_BLOCK_SIZE_BYTES-1:0] vx_dram_rsp_data;
logic [`GLOBAL_BLOCK_SIZE-1:0] vx_dram_rsp_data;
logic vx_snp_req;
logic [31:0] vx_snp_req_addr;

26
hw/rtl/VX_back_end.v
View file

@ -23,12 +23,12 @@ module VX_back_end #(
);
VX_wb_if writeback_temp_if();
assign writeback_if.wb = writeback_temp_if.wb;
assign writeback_if.rd = writeback_temp_if.rd;
assign writeback_if.write_data = writeback_temp_if.write_data;
assign writeback_if.wb_valid = writeback_temp_if.wb_valid;
assign writeback_if.wb_warp_num = writeback_temp_if.wb_warp_num;
assign writeback_if.wb_pc = writeback_temp_if.wb_pc;
assign writeback_if.wb = writeback_temp_if.wb;
assign writeback_if.rd = writeback_temp_if.rd;
assign writeback_if.data = writeback_temp_if.data;
assign writeback_if.valid = writeback_temp_if.valid;
assign writeback_if.warp_num = writeback_temp_if.warp_num;
assign writeback_if.pc = writeback_temp_if.pc;
// assign VX_writeback_if(writeback_temp_if);
@ -37,18 +37,18 @@ wire no_slot_exec;
// LSU input + output
VX_lsu_req_if lsu_req_if();
VX_inst_mem_wb_if mem_wb_if();
VX_wb_if mem_wb_if();
// Exec unit input + output
VX_exec_unit_req_if exec_unit_req_if();
VX_inst_exec_wb_if inst_exec_wb_if();
VX_wb_if inst_exec_wb_if();
// GPU unit input
VX_gpgpu_inst_req_if gpgpu_inst_req_if();
VX_gpu_inst_req_if gpu_inst_req_if();
// CSR unit inputs
VX_csr_req_if csr_req_if();
VX_csr_wb_if csr_wb_if();
VX_wb_if csr_wb_if();
wire no_slot_csr;
wire stall_gpr_csr;
@ -61,7 +61,7 @@ VX_gpr_stage gpr_stage (
// New
.exec_unit_req_if (exec_unit_req_if),
.lsu_req_if (lsu_req_if),
.gpgpu_inst_req_if (gpgpu_inst_req_if),
.gpu_inst_req_if (gpu_inst_req_if),
.csr_req_if (csr_req_if),
.stall_gpr_csr (stall_gpr_csr),
// End new
@ -92,8 +92,8 @@ VX_exec_unit exec_unit (
.no_slot_exec (no_slot_exec)
);
VX_gpgpu_inst gpgpu_inst (
.gpgpu_inst_req_if(gpgpu_inst_req_if),
VX_gpu_inst gpu_inst (
.gpu_inst_req_if(gpu_inst_req_if),
.warp_ctl_if (warp_ctl_if)
);

98
hw/rtl/VX_config.vh
View file

@ -23,8 +23,8 @@
`define NUM_BARRIERS 4
`endif
`ifndef GLOBAL_BLOCK_SIZE_BYTES
`define GLOBAL_BLOCK_SIZE_BYTES 16
`ifndef GLOBAL_BLOCK_SIZE
`define GLOBAL_BLOCK_SIZE 16
`endif
`ifndef NUM_CSRS
@ -39,29 +39,30 @@
`define STARTUP_ADDR 32'h80000000
`endif
`ifndef SHARED_MEM_ADDR_MATCH
`define SHARED_MEM_ADDR_MATCH(x) (x[31:24] == 8'hFF)
`endif
// ========================= Dcache Configurable Knobs ========================
// Size of cache in bytes
`ifndef DCACHE_SIZE_BYTES
`define DCACHE_SIZE_BYTES 2048
`ifndef DCACHE_SIZE
`define DCACHE_SIZE 2048
`endif
// Size of line inside a bank in bytes
`ifndef DBANK_LINE_SIZE_BYTES
`define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`ifndef DBANK_LINE_SIZE
`define DBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
`endif
// Size of line inside a bank in bits
`define DBANK_LINE_SIZE (`DBANK_LINE_SIZE_BYTES * 8)
// Number of banks {1, 2, 4, 8,...}
`ifndef DNUM_BANKS
`define DNUM_BANKS 8
`endif
// Size of a word in bytes
`ifndef DWORD_SIZE_BYTES
`define DWORD_SIZE_BYTES 4
`ifndef DWORD_SIZE
`define DWORD_SIZE 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
@ -133,21 +134,16 @@
`define DFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef DSIMULATED_DRAM_LATENCY_CYCLES
`define DSIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ========================== Icache Configurable Knobs =======================
// Size of cache in bytes
`ifndef ICACHE_SIZE_BYTES
`define ICACHE_SIZE_BYTES 4096
`ifndef ICACHE_SIZE
`define ICACHE_SIZE 2048
`endif
// Size of line inside a bank in bytes
`ifndef IBANK_LINE_SIZE_BYTES
`define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`ifndef IBANK_LINE_SIZE
`define IBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
`endif
// Number of banks {1, 2, 4, 8,...}
@ -156,8 +152,8 @@
`endif
// Size of a word in bytes
`ifndef IWORD_SIZE_BYTES
`define IWORD_SIZE_BYTES 4
`ifndef IWORD_SIZE
`define IWORD_SIZE 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
@ -229,21 +225,16 @@
`define IFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef ISIMULATED_DRAM_LATENCY_CYCLES
`define ISIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// =========================== SM Configurable Knobs ==========================
// Size of cache in bytes
`ifndef SCACHE_SIZE_BYTES
`define SCACHE_SIZE_BYTES 1024
`ifndef SCACHE_SIZE
`define SCACHE_SIZE 1024
`endif
// Size of line inside a bank in bytes
`ifndef SBANK_LINE_SIZE_BYTES
`define SBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`ifndef SBANK_LINE_SIZE
`define SBANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
`endif
// Number of banks {1, 2, 4, 8,...}
@ -252,8 +243,8 @@
`endif
// Size of a word in bytes
`ifndef SWORD_SIZE_BYTES
`define SWORD_SIZE_BYTES 4
`ifndef SWORD_SIZE
`define SWORD_SIZE 4
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
@ -325,21 +316,16 @@
`define SFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef SSIMULATED_DRAM_LATENCY_CYCLES
`define SSIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ======================== L2cache Configurable Knobs ========================
// Size of cache in bytes
`ifndef L2CACHE_SIZE_BYTES
`define L2CACHE_SIZE_BYTES 4096
`ifndef L2CACHE_SIZE
`define L2CACHE_SIZE 4096
`endif
// Size of line inside a bank in bytes
`ifndef L2BANK_LINE_SIZE_BYTES
`define L2BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`ifndef L2BANK_LINE_SIZE
`define L2BANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
`endif
// Number of banks {1, 2, 4, 8,...}
@ -348,8 +334,8 @@
`endif
// Size of a word in bytes
`ifndef L2WORD_SIZE_BYTES
`define L2WORD_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES)
`ifndef L2WORD_SIZE
`define L2WORD_SIZE `L2BANK_LINE_SIZE
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
@ -421,21 +407,16 @@
`define L2FILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef L2SIMULATED_DRAM_LATENCY_CYCLES
`define L2SIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// ======================== L3cache Configurable Knobs ========================
// Size of cache in bytes
`ifndef L3CACHE_SIZE_BYTES
`define L3CACHE_SIZE_BYTES 8192
`ifndef L3CACHE_SIZE
`define L3CACHE_SIZE 8192
`endif
// Size of line inside a bank in bytes
`ifndef L3BANK_LINE_SIZE_BYTES
`define L3BANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
`ifndef L3BANK_LINE_SIZE
`define L3BANK_LINE_SIZE `GLOBAL_BLOCK_SIZE
`endif
// Number of banks {1, 2, 4, 8,...}
@ -444,13 +425,13 @@
`endif
// Size of a word in bytes
`ifndef L3WORD_SIZE_BYTES
`define L3WORD_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES)
`ifndef L3WORD_SIZE
`define L3WORD_SIZE `L3BANK_LINE_SIZE
`endif
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`ifndef L3NUM_REQUESTS
`define L3NUM_REQUESTS (`NUM_CLUSTERS)
`define L3NUM_REQUESTS `NUM_CLUSTERS
`endif
// Number of cycles to complete stage 1 (read from memory)
@ -515,11 +496,6 @@
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef L3FILL_INVALIDAOR_SIZE
`define L3FILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
`ifndef L3SIMULATED_DRAM_LATENCY_CYCLES
`define L3SIMULATED_DRAM_LATENCY_CYCLES 2
`endif
// VX_CONFIG

22
hw/rtl/VX_csr_pipe.v
View file

@ -8,18 +8,18 @@ module VX_csr_pipe #(
input wire no_slot_csr,
VX_csr_req_if csr_req_if,
VX_wb_if writeback_if,
VX_csr_wb_if csr_wb_if,
VX_wb_if csr_wb_if,
output wire stall_gpr_csr
);
wire[`NUM_THREADS-1:0] valid_s2;
wire[`NW_BITS-1:0] warp_num_s2;
wire[4:0] rd_s2;
wire[1:0] wb_s2;
wire is_csr_s2;
wire[4:0] rd_s2;
wire[1:0] wb_s2;
wire is_csr_s2;
wire[`CSR_ADDR_SIZE-1:0] csr_address_s2;
wire[31:0] csr_read_data_s2;
wire[31:0] csr_updated_data_s2;
wire[31:0] csr_read_data_s2;
wire[31:0] csr_updated_data_s2;
wire[31:0] csr_read_data_unqual;
wire[31:0] csr_read_data;
@ -28,7 +28,7 @@ module VX_csr_pipe #(
assign csr_read_data = (csr_address_s2 == csr_req_if.csr_address) ? csr_updated_data_s2 : csr_read_data_unqual;
wire writeback = |writeback_if.wb_valid;
wire writeback = |writeback_if.valid;
VX_csr_data csr_data(
.clk (clk),
@ -88,9 +88,9 @@ module VX_csr_pipe #(
assign csr_vec_read_data_s2[cur_v] = csr_read_data_s2;
end
wire thread_select = csr_address_s2 == 12'h20;
wire warp_select = csr_address_s2 == 12'h21;
wire warp_id_select = csr_address_s2 == 12'h22;
wire thread_select = (csr_address_s2 == `CSR_THREAD);
wire warp_select = (csr_address_s2 == `CSR_WARP);
wire warp_id_select = (csr_address_s2 == `CSR_WARP_ID);
assign final_csr_data = thread_select ? thread_ids :
warp_select ? warp_ids :
@ -101,6 +101,6 @@ module VX_csr_pipe #(
assign csr_wb_if.warp_num = warp_num_s2;
assign csr_wb_if.rd = rd_s2;
assign csr_wb_if.wb = wb_s2;
assign csr_wb_if.csr_result = final_csr_data;
assign csr_wb_if.data = final_csr_data;
endmodule

2
hw/rtl/VX_csr_wrapper.v
View file

@ -3,7 +3,7 @@
module VX_csr_wrapper (
VX_csr_req_if csr_req_if,
VX_csr_wb_if csr_wb_if
VX_wb_if csr_wb_if
);
wire[`NUM_THREADS-1:0][31:0] thread_ids;

14
hw/rtl/VX_decode.v
View file

@ -140,8 +140,8 @@ module VX_decode(
assign frE_to_bckE_req_if.rs2_src = (is_itype || is_stype) ? `RS2_IMMED : `RS2_REG;
// MEM signals
assign frE_to_bckE_req_if.mem_read = (is_linst) ? func3 : `NO_MEM_READ;
assign frE_to_bckE_req_if.mem_write = (is_stype) ? func3 : `NO_MEM_WRITE;
assign frE_to_bckE_req_if.mem_read = (is_linst) ? func3 : `WORD_SEL_NO;
assign frE_to_bckE_req_if.mem_write = (is_stype) ? func3 : `WORD_SEL_NO;
// UPPER IMMEDIATE
always @(*) begin
@ -211,8 +211,8 @@ module VX_decode(
// CSR
assign csr_cond1 = func3 != 3'h0;
assign csr_cond2 = u_12 >= 12'h2;
assign csr_cond1 = func3 != 3'h0;
assign csr_cond2 = u_12 >= 12'h2;
assign frE_to_bckE_req_if.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55;
@ -325,6 +325,12 @@ module VX_decode(
assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
/*always_comb begin
if (1'($time & 1) && |fd_inst_meta_de.valid) begin
$display("*** %t: decode: opcode=%h", $time, curr_opcode);
end
end*/
endmodule

88
hw/rtl/VX_define.vh
View file

@ -29,7 +29,7 @@
if (!(cond)) $error(msg); \
endgenerate
`define CLOG2(x) $clog2(x);
`define CLOG2(x) $clog2(x)
`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > x) ? 1 : 0))
`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
@ -50,10 +50,18 @@
`define CSR_WIDTH 12
`define CSR_CYCL_L 12'hC00;
`define CSR_CYCL_H 12'hC80;
`define CSR_INST_L 12'hC02;
`define CSR_INST_H 12'hC82;
///////////////////////////////////////////////////////////////////////////////
`define CSR_THREAD 12'h020
`define CSR_WARP 12'h021
`define CSR_WARP_ID 12'h022
`define CSR_CYCL_L 12'hC00;
`define CSR_CYCL_H 12'hC80;
`define CSR_INST_L 12'hC02;
`define CSR_INST_H 12'hC82;
///////////////////////////////////////////////////////////////////////////////
`define R_INST 7'd51
`define L_INST 7'd3
@ -67,6 +75,8 @@
`define SYS_INST 7'd115
`define GPGPU_INST 7'h6b
///////////////////////////////////////////////////////////////////////////////
`define WB_ALU 2'h1
`define WB_MEM 2'h2
`define WB_JAL 2'h3
@ -75,18 +85,6 @@
`define RS2_IMMED 1
`define RS2_REG 0
`define NO_MEM_READ 3'h7
`define LB_MEM_READ 3'h0
`define LH_MEM_READ 3'h1
`define LW_MEM_READ 3'h2
`define LBU_MEM_READ 3'h4
`define LHU_MEM_READ 3'h5
`define NO_MEM_WRITE 3'h7
`define SB_MEM_WRITE 3'h0
`define SH_MEM_WRITE 3'h1
`define SW_MEM_WRITE 3'h2
`define NO_BRANCH 3'h0
`define BEQ 3'h1
`define BNE 3'h2
@ -145,58 +143,70 @@
// Function ID
`define DFUNC_ID 0
// Size of line inside a bank in bits
`define DBANK_LINE_SIZE (`DBANK_LINE_SIZE_BYTES * 8)
// DRAM request data bits
`define DDRAM_LINE_WIDTH (`DBANK_LINE_SIZE * 8)
// Bank Number of words in a line
`define DBANK_LINE_WORDS (`DBANK_LINE_SIZE_BYTES / `DWORD_SIZE_BYTES)
// DRAM request address bits
`define DDRAM_ADDR_WIDTH (32 - `CLOG2(`DBANK_LINE_SIZE))
// Word size in bits
`define DWORD_SIZE_BITS (`DWORD_SIZE_BYTES * 8)
// DRAM request tag bits
`define DDRAM_TAG_WIDTH `DDRAM_ADDR_WIDTH
////////////////////////// Icache Configurable Knobs //////////////////////////
// Function ID
`define IFUNC_ID 1
// Size of line inside a bank in bits
`define IBANK_LINE_SIZE (`IBANK_LINE_SIZE_BYTES * 8)
// DRAM request data bits
`define IDRAM_LINE_WIDTH (`IBANK_LINE_SIZE * 8)
// Bank Number of words in a line
`define IBANK_LINE_WORDS (`IBANK_LINE_SIZE_BYTES / `IWORD_SIZE_BYTES)
// DRAM request address bits
`define IDRAM_ADDR_WIDTH (32 - `CLOG2(`IBANK_LINE_SIZE))
// DRAM request tag bits
`define IDRAM_TAG_WIDTH `IDRAM_ADDR_WIDTH
////////////////////////// SM Configurable Knobs //////////////////////////////
// Function ID
`define SFUNC_ID 2
// Size of line inside a bank in bits
`define SBANK_LINE_SIZE (`SBANK_LINE_SIZE_BYTES * 8)
// DRAM request data bits
`define SDRAM_LINE_WIDTH (`SBANK_LINE_SIZE * 8)
// Bank Number of words in a line
`define SBANK_LINE_WORDS (`SBANK_LINE_SIZE_BYTES / `SWORD_SIZE_BYTES)
// DRAM request address bits
`define SDRAM_ADDR_WIDTH (32 - `CLOG2(`SBANK_LINE_SIZE))
// DRAM request tag bits
`define SDRAM_TAG_WIDTH `SDRAM_ADDR_WIDTH
////////////////////////// L2cache Configurable Knobs /////////////////////////
// Function ID
`define L2FUNC_ID 3
// Size of line inside a bank in bits
`define L2BANK_LINE_SIZE (`L2BANK_LINE_SIZE_BYTES * 8)
// DRAM request data bits
`define L2DRAM_LINE_WIDTH (`L2BANK_LINE_SIZE * 8)
// Bank Number of words in a line
`define L2BANK_LINE_WORDS (`L2BANK_LINE_SIZE_BYTES / `L2WORD_SIZE_BYTES)
// DRAM request address bits
`define L2DRAM_ADDR_WIDTH (32 - `CLOG2(`L2BANK_LINE_SIZE))
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH ((`NUM_CORES > 1) ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+1))
////////////////////////// L3cache Configurable Knobs /////////////////////////
// Function ID
`define L3FUNC_ID 3
// Size of line inside a bank in bits
`define L3BANK_LINE_SIZE (`L3BANK_LINE_SIZE_BYTES * 8)
// DRAM request data bits
`define L3DRAM_LINE_WIDTH (`L3BANK_LINE_SIZE * 8)
// Bank Number of words in a line
`define L3BANK_LINE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
// DRAM request address bits
`define L3DRAM_ADDR_WIDTH (32 - `CLOG2(`L3BANK_LINE_SIZE))
// DRAM request tag bits
`define L3DRAM_TAG_WIDTH ((`NUM_CLUSTERS > 1) ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
// VX_DEFINE
`endif

331
hw/rtl/VX_dmem_ctrl.v
View file

@ -22,122 +22,123 @@ module VX_dmem_ctrl (
VX_cache_core_rsp_if icache_core_rsp_if,
VX_cache_core_req_if icache_core_req_if
);
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_req_smem_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_smem_if();
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_smem_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_rsp_smem_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_req_dcache_if();
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_dcache_if();
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_req_dcache_if();
wire to_shm = dcache_core_req_if.core_req_addr[0][31:24] == 8'hFF;
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_rsp_dcache_if();
wire to_shm = `SHARED_MEM_ADDR_MATCH(dcache_core_req_if.core_req_addr[0]);
wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_rsp_valid);
// Dcache Request
assign dcache_req_dcache_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
assign dcache_req_dcache_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_dcache_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_dcache_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_dcache_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_dcache_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_req_dcache_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_req_dcache_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_req_dcache_if.core_req_pc = dcache_core_req_if.core_req_pc;
assign dcache_req_dcache_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
assign dcache_req_dcache_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_dcache_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_dcache_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_dcache_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_dcache_if.core_req_tag = dcache_core_req_if.core_req_tag;
assign dcache_rsp_dcache_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready;
assign dcache_rsp_dcache_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready;
// Shared Memory Request
assign dcache_req_smem_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
assign dcache_req_smem_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_smem_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_smem_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_smem_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_smem_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_req_smem_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_req_smem_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_req_smem_if.core_req_pc = dcache_core_req_if.core_req_pc;
assign dcache_rsp_smem_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready && ~dcache_wants_wb;
assign dcache_req_smem_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
assign dcache_req_smem_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_req_smem_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_req_smem_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_req_smem_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_req_smem_if.core_req_tag = dcache_core_req_if.core_req_tag;
assign dcache_core_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
// Dcache Response
assign dcache_core_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
assign dcache_core_rsp_if.core_rsp_read = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_read : dcache_rsp_smem_if.core_rsp_read;
assign dcache_core_rsp_if.core_rsp_write = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_write : dcache_rsp_smem_if.core_rsp_write;
assign dcache_core_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc;
assign dcache_core_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
assign dcache_core_rsp_if.core_rsp_data = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_data : dcache_rsp_smem_if.core_rsp_data;
assign dcache_core_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num;
assign dcache_core_rsp_if.core_rsp_tag = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_tag : dcache_rsp_smem_if.core_rsp_tag;
assign dcache_rsp_smem_if.core_rsp_ready = dcache_core_rsp_if.core_rsp_ready && ~dcache_wants_wb;
assign dcache_core_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) smem_dram_req_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) smem_dram_rsp_if();
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) smem_dram_rsp_if();
VX_cache #(
.CACHE_SIZE_BYTES (`SCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`SBANK_LINE_SIZE_BYTES),
.NUM_BANKS (`SNUM_BANKS),
.WORD_SIZE_BYTES (`SWORD_SIZE_BYTES),
.NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.FUNC_ID (`SFUNC_ID),
.REQQ_SIZE (`SREQQ_SIZE),
.MRVQ_SIZE (`SMRVQ_SIZE),
.DFPQ_SIZE (`SDFPQ_SIZE),
.SNRQ_SIZE (`SSNRQ_SIZE),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.LLVQ_SIZE (`SLLVQ_SIZE),
.FFSQ_SIZE (`SFFSQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES)
.CACHE_SIZE (`SCACHE_SIZE),
.BANK_LINE_SIZE (`SBANK_LINE_SIZE),
.NUM_BANKS (`SNUM_BANKS),
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQUESTS (`SNUM_REQUESTS),
.STAGE_1_CYCLES (`SSTAGE_1_CYCLES),
.FUNC_ID (`SFUNC_ID),
.REQQ_SIZE (`SREQQ_SIZE),
.MRVQ_SIZE (`SMRVQ_SIZE),
.DFPQ_SIZE (`SDFPQ_SIZE),
.SNRQ_SIZE (`SSNRQ_SIZE),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DWBQ_SIZE (`SDWBQ_SIZE),
.DFQQ_SIZE (`SDFQQ_SIZE),
.LLVQ_SIZE (`SLLVQ_SIZE),
.FFSQ_SIZE (`SFFSQ_SIZE),
.PRFQ_SIZE (`SPRFQ_SIZE),
.PRFQ_STRIDE (`SPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) gpu_smem (
.clk (clk),
.reset (reset),
// Core req
// Core request
.core_req_valid (dcache_req_smem_if.core_req_valid),
.core_req_read (dcache_req_smem_if.core_req_read),
.core_req_write (dcache_req_smem_if.core_req_write),
.core_req_addr (dcache_req_smem_if.core_req_addr),
.core_req_data (dcache_req_smem_if.core_req_data),
.core_req_rd (dcache_req_smem_if.core_req_rd),
.core_req_wb (dcache_req_smem_if.core_req_wb),
.core_req_warp_num (dcache_req_smem_if.core_req_warp_num),
.core_req_pc (dcache_req_smem_if.core_req_pc),
// Can submit core Req
.core_req_tag (dcache_req_smem_if.core_req_tag),
.core_req_ready (dcache_req_smem_if.core_req_ready),
// Core Cache Can't WB
// Core response
.core_rsp_valid (dcache_rsp_smem_if.core_rsp_valid),
.core_rsp_data (dcache_rsp_smem_if.core_rsp_data),
.core_rsp_tag (dcache_rsp_smem_if.core_rsp_tag),
.core_rsp_ready (dcache_rsp_smem_if.core_rsp_ready),
// Cache CWB
.core_rsp_valid (dcache_rsp_smem_if.core_rsp_valid),
.core_rsp_read (dcache_rsp_smem_if.core_rsp_read),
.core_rsp_write (dcache_rsp_smem_if.core_rsp_write),
.core_rsp_warp_num (dcache_rsp_smem_if.core_rsp_warp_num),
.core_rsp_data (dcache_rsp_smem_if.core_rsp_data),
.core_rsp_pc (dcache_rsp_smem_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_rsp_addr (),
`IGNORE_WARNINGS_END
// DRAM response
.dram_rsp_valid (smem_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (smem_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (smem_dram_rsp_if.dram_rsp_data),
// DRAM accept response
.dram_rsp_ready (smem_dram_req_if.dram_rsp_ready),
// DRAM Req
// DRAM request
.dram_req_read (smem_dram_req_if.dram_req_read),
.dram_req_write (smem_dram_req_if.dram_req_write),
.dram_req_addr (smem_dram_req_if.dram_req_addr),
.dram_req_data (smem_dram_req_if.dram_req_data),
.dram_req_ready (0),
.dram_req_tag (smem_dram_req_if.dram_req_tag),
.dram_req_ready (smem_dram_req_if.dram_req_ready),
// DRAM response
.dram_rsp_valid (smem_dram_rsp_if.dram_rsp_valid),
.dram_rsp_data (smem_dram_rsp_if.dram_rsp_data),
.dram_rsp_tag (smem_dram_rsp_if.dram_rsp_tag),
.dram_rsp_ready (smem_dram_rsp_if.dram_rsp_ready),
// Snoop Request
.snp_req_valid (0),
@ -155,26 +156,27 @@ module VX_dmem_ctrl (
);
VX_cache #(
.CACHE_SIZE_BYTES (`DCACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`DBANK_LINE_SIZE_BYTES),
.NUM_BANKS (`DNUM_BANKS),
.WORD_SIZE_BYTES (`DWORD_SIZE_BYTES),
.NUM_REQUESTS (`DNUM_REQUESTS),
.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
.FUNC_ID (`DFUNC_ID),
.REQQ_SIZE (`DREQQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DFPQ_SIZE (`DDFPQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
.CWBQ_SIZE (`DCWBQ_SIZE),
.DWBQ_SIZE (`DDWBQ_SIZE),
.DFQQ_SIZE (`DDFQQ_SIZE),
.LLVQ_SIZE (`DLLVQ_SIZE),
.FFSQ_SIZE (`DFFSQ_SIZE),
.PRFQ_SIZE (`DPRFQ_SIZE),
.PRFQ_STRIDE (`DPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES)
.CACHE_SIZE (`DCACHE_SIZE),
.BANK_LINE_SIZE (`DBANK_LINE_SIZE),
.NUM_BANKS (`DNUM_BANKS),
.WORD_SIZE (`DWORD_SIZE),
.NUM_REQUESTS (`DNUM_REQUESTS),
.STAGE_1_CYCLES (`DSTAGE_1_CYCLES),
.FUNC_ID (`DFUNC_ID),
.REQQ_SIZE (`DREQQ_SIZE),
.MRVQ_SIZE (`DMRVQ_SIZE),
.DFPQ_SIZE (`DDFPQ_SIZE),
.SNRQ_SIZE (`DSNRQ_SIZE),
.CWBQ_SIZE (`DCWBQ_SIZE),
.DWBQ_SIZE (`DDWBQ_SIZE),
.DFQQ_SIZE (`DDFQQ_SIZE),
.LLVQ_SIZE (`DLLVQ_SIZE),
.FFSQ_SIZE (`DFFSQ_SIZE),
.PRFQ_SIZE (`DPRFQ_SIZE),
.PRFQ_STRIDE (`DPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH)
) gpu_dcache (
.clk (clk),
.reset (reset),
@ -185,43 +187,29 @@ module VX_dmem_ctrl (
.core_req_write (dcache_req_dcache_if.core_req_write),
.core_req_addr (dcache_req_dcache_if.core_req_addr),
.core_req_data (dcache_req_dcache_if.core_req_data),
.core_req_rd (dcache_req_dcache_if.core_req_rd),
.core_req_wb (dcache_req_dcache_if.core_req_wb),
.core_req_warp_num (dcache_req_dcache_if.core_req_warp_num),
.core_req_pc (dcache_req_dcache_if.core_req_pc),
// Can submit core Req
.core_req_tag (dcache_req_dcache_if.core_req_tag),
.core_req_ready (dcache_req_dcache_if.core_req_ready),
// Core Cache Can't WB
// Core response
.core_rsp_valid (dcache_rsp_dcache_if.core_rsp_valid),
.core_rsp_data (dcache_rsp_dcache_if.core_rsp_data),
.core_rsp_tag (dcache_rsp_dcache_if.core_rsp_tag),
.core_rsp_ready (dcache_rsp_dcache_if.core_rsp_ready),
// Cache CWB
.core_rsp_valid (dcache_rsp_dcache_if.core_rsp_valid),
.core_rsp_read (dcache_rsp_dcache_if.core_rsp_read),
.core_rsp_write (dcache_rsp_dcache_if.core_rsp_write),
.core_rsp_warp_num (dcache_rsp_dcache_if.core_rsp_warp_num),
.core_rsp_data (dcache_rsp_dcache_if.core_rsp_data),
.core_rsp_pc (dcache_rsp_dcache_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_rsp_addr (),
`IGNORE_WARNINGS_END
// DRAM response
.dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (dcache_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data),
// DRAM accept response
.dram_rsp_ready (dcache_dram_req_if.dram_rsp_ready),
// DRAM Req
// DRAM request
.dram_req_read (dcache_dram_req_if.dram_req_read),
.dram_req_write (dcache_dram_req_if.dram_req_write),
.dram_req_addr (dcache_dram_req_if.dram_req_addr),
.dram_req_data (dcache_dram_req_if.dram_req_data),
.dram_req_tag (dcache_dram_req_if.dram_req_tag),
.dram_req_ready (dcache_dram_req_if.dram_req_ready),
// DRAM response
.dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data),
.dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag),
.dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready),
// Snoop Request
.snp_req_valid (dcache_snp_req_if.snp_req_valid),
.snp_req_addr (dcache_snp_req_if.snp_req_addr),
@ -236,72 +224,59 @@ module VX_dmem_ctrl (
);
VX_cache #(
.CACHE_SIZE_BYTES (`ICACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`IBANK_LINE_SIZE_BYTES),
.NUM_BANKS (`INUM_BANKS),
.WORD_SIZE_BYTES (`IWORD_SIZE_BYTES),
.NUM_REQUESTS (`INUM_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.FUNC_ID (`IFUNC_ID),
.REQQ_SIZE (`IREQQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (`ISNRQ_SIZE),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),
.LLVQ_SIZE (`ILLVQ_SIZE),
.FFSQ_SIZE (`IFFSQ_SIZE),
.PRFQ_SIZE (`IPRFQ_SIZE),
.PRFQ_STRIDE (`IPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`ISIMULATED_DRAM_LATENCY_CYCLES)
.CACHE_SIZE (`ICACHE_SIZE),
.BANK_LINE_SIZE (`IBANK_LINE_SIZE),
.NUM_BANKS (`INUM_BANKS),
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQUESTS (`INUM_REQUESTS),
.STAGE_1_CYCLES (`ISTAGE_1_CYCLES),
.FUNC_ID (`IFUNC_ID),
.REQQ_SIZE (`IREQQ_SIZE),
.MRVQ_SIZE (`IMRVQ_SIZE),
.DFPQ_SIZE (`IDFPQ_SIZE),
.SNRQ_SIZE (`ISNRQ_SIZE),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DWBQ_SIZE (`IDWBQ_SIZE),
.DFQQ_SIZE (`IDFQQ_SIZE),
.LLVQ_SIZE (`ILLVQ_SIZE),
.FFSQ_SIZE (`IFFSQ_SIZE),
.PRFQ_SIZE (`IPRFQ_SIZE),
.PRFQ_STRIDE (`IPRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`IFILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (`CORE_REQ_TAG_WIDTH),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) gpu_icache (
.clk (clk),
.reset (reset),
// Core req
// Core request
.core_req_valid (icache_core_req_if.core_req_valid),
.core_req_read (icache_core_req_if.core_req_read),
.core_req_write (icache_core_req_if.core_req_write),
.core_req_addr (icache_core_req_if.core_req_addr),
.core_req_data (icache_core_req_if.core_req_data),
.core_req_rd (icache_core_req_if.core_req_rd),
.core_req_wb (icache_core_req_if.core_req_wb),
.core_req_warp_num (icache_core_req_if.core_req_warp_num),
.core_req_pc (icache_core_req_if.core_req_pc),
// Can submit core Req
.core_req_tag (icache_core_req_if.core_req_tag),
.core_req_ready (icache_core_req_if.core_req_ready),
// Core Cache Can't WB
.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
// Cache CWB
// Core response
.core_rsp_valid (icache_core_rsp_if.core_rsp_valid),
.core_rsp_read (icache_core_rsp_if.core_rsp_read),
.core_rsp_write (icache_core_rsp_if.core_rsp_write),
.core_rsp_warp_num (icache_core_rsp_if.core_rsp_warp_num),
.core_rsp_data (icache_core_rsp_if.core_rsp_data),
.core_rsp_pc (icache_core_rsp_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_rsp_addr (),
`IGNORE_WARNINGS_END
// DRAM response
.dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_addr (icache_dram_rsp_if.dram_rsp_addr),
.dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
// DRAM accept response
.dram_rsp_ready (icache_dram_req_if.dram_rsp_ready),
.core_rsp_tag (icache_core_rsp_if.core_rsp_tag),
.core_rsp_ready (icache_core_rsp_if.core_rsp_ready),
// DRAM Req
.dram_req_read (icache_dram_req_if.dram_req_read),
.dram_req_write (icache_dram_req_if.dram_req_write),
.dram_req_addr (icache_dram_req_if.dram_req_addr),
.dram_req_data (icache_dram_req_if.dram_req_data),
.dram_req_ready (icache_dram_req_if.dram_req_ready),
.dram_req_tag (icache_dram_req_if.dram_req_tag),
.dram_req_ready (icache_dram_req_if.dram_req_ready),
// DRAM response
.dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
.dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
.dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag),
.dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
// Snoop Request
.snp_req_valid (icache_snp_req_if.snp_req_valid),

25
hw/rtl/VX_exec_unit.v
View file

@ -8,7 +8,7 @@ module VX_exec_unit (
// Output
// Writeback
VX_inst_exec_wb_if inst_exec_wb_if,
VX_wb_if inst_exec_wb_if,
// JAL Response
VX_jal_rsp_if jal_rsp_if,
// Branch Response
@ -108,24 +108,24 @@ module VX_exec_unit (
endgenerate
// VX_inst_exec_wb_if inst_exec_wb_temp_if();
// VX_wb_if inst_exec_wb_temp_if();
// JAL Response
VX_jal_rsp_if jal_rsp_temp_if();
// Branch Response
VX_branch_rsp_if branch_rsp_temp_if();
// Actual Writeback
assign inst_exec_wb_if.rd = exec_unit_req_if.rd;
assign inst_exec_wb_if.wb = exec_unit_req_if.wb;
assign inst_exec_wb_if.wb_valid = exec_unit_req_if.valid & {`NUM_THREADS{!internal_stall}};
assign inst_exec_wb_if.wb_warp_num = exec_unit_req_if.warp_num;
assign inst_exec_wb_if.alu_result = exec_unit_req_if.jal ? duplicate_PC_data : alu_result;
assign inst_exec_wb_if.rd = exec_unit_req_if.rd;
assign inst_exec_wb_if.wb = exec_unit_req_if.wb;
assign inst_exec_wb_if.valid = exec_unit_req_if.valid & {`NUM_THREADS{!internal_stall}};
assign inst_exec_wb_if.warp_num = exec_unit_req_if.warp_num;
assign inst_exec_wb_if.data = exec_unit_req_if.jal ? duplicate_PC_data : alu_result;
assign inst_exec_wb_if.pc = in_curr_PC;
assign inst_exec_wb_if.exec_wb_pc = in_curr_PC;
// Jal rsp
assign jal_rsp_temp_if.jal = in_jal;
assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num;
assign jal_rsp_temp_if.jal = in_jal;
assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num;
// Branch rsp
assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `NO_BRANCH) && (|exec_unit_req_if.valid);
@ -133,7 +133,6 @@ module VX_exec_unit (
assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num;
assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset
wire zero = 0;
// VX_generic_register #(.N(174)) exec_reg(
@ -143,7 +142,7 @@ module VX_exec_unit (
// .flush(zero),
// .in ({inst_exec_wb_temp_if.rd, inst_exec_wb_temp_if.wb, inst_exec_wb_temp_if.wb_valid, inst_exec_wb_temp_if.wb_warp_num, inst_exec_wb_temp_if.alu_result, inst_exec_wb_temp_if.exec_wb_pc}),
// .out ({inst_exec_wb_if.rd , inst_exec_wb_if.wb , inst_exec_wb_if.wb_valid , inst_exec_wb_if.wb_warp_num , inst_exec_wb_if.alu_result , inst_exec_wb_if.exec_wb_pc })
// );
// );
VX_generic_register #(
.N(33 + `NW_BITS-1 + 1)

9
hw/rtl/VX_fetch.v
View file

@ -22,13 +22,7 @@ module VX_fetch (
wire[31:0] warp_pc;
wire scheduled_warp;
wire pipe_stall;
// Only reason this is there is because there is a hidden assumption that decode is exactly after fetch
// Locals
assign pipe_stall = schedule_delay || icache_stage_delay;
wire pipe_stall = schedule_delay || icache_stage_delay;
VX_warp_sched warp_sched (
.clk (clk),
@ -97,6 +91,7 @@ module VX_fetch (
assign fe_inst_meta_fi.valid = thread_mask;
assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc;
`DEBUG_BEGIN
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);

4
hw/rtl/VX_gpr.v
View file

@ -22,8 +22,8 @@ module VX_gpr (
.waddr (writeback_if.rd),
.raddr1(gpr_read_if.rs1),
.raddr2(gpr_read_if.rs2),
.be (writeback_if.wb_valid),
.wdata (writeback_if.write_data),
.be (writeback_if.valid),
.wdata (writeback_if.data),
.q1 (a_reg_data),
.q2 (b_reg_data)
);

146
hw/rtl/VX_gpr_stage.v
View file

@ -1,14 +1,14 @@
`include "VX_define.vh"
module VX_gpr_stage (
input wire clk,
input wire reset,
input wire schedule_delay,
input wire clk,
input wire reset,
input wire schedule_delay,
input wire memory_delay,
input wire exec_delay,
input wire stall_gpr_csr,
output wire gpr_stage_delay,
input wire memory_delay,
input wire exec_delay,
input wire stall_gpr_csr,
output wire gpr_stage_delay,
// inputs
// Instruction Information
@ -20,14 +20,14 @@ module VX_gpr_stage (
// Outputs
VX_exec_unit_req_if exec_unit_req_if,
VX_lsu_req_if lsu_req_if,
VX_gpgpu_inst_req_if gpgpu_inst_req_if,
VX_gpu_inst_req_if gpu_inst_req_if,
VX_csr_req_if csr_req_if
);
`DEBUG_BEGIN
wire[31:0] curr_PC = bckE_req_if.curr_PC;
wire[2:0] branchType = bckE_req_if.branch_type;
wire is_store = (bckE_req_if.mem_write != `NO_MEM_WRITE);
wire is_load = (bckE_req_if.mem_read != `NO_MEM_READ);
wire is_store = (bckE_req_if.mem_write != `WORD_SEL_NO);
wire is_load = (bckE_req_if.mem_read != `WORD_SEL_NO);
wire jalQual = bckE_req_if.jalQual;
`DEBUG_END
@ -65,16 +65,16 @@ module VX_gpr_stage (
// Outputs
VX_exec_unit_req_if exec_unit_req_temp_if();
VX_lsu_req_if lsu_req_temp_if();
VX_gpgpu_inst_req_if gpu_inst_req_temp_if();
VX_gpu_inst_req_if gpu_inst_req_temp_if();
VX_csr_req_if csr_req_temp_if();
VX_inst_multiplex inst_mult(
.bckE_req_if (bckE_req_if),
.gpr_data_if (gpr_datf_if),
.exec_unit_req_if(exec_unit_req_temp_if),
.lsu_req_if (lsu_req_temp_if),
.gpgpu_inst_req_if (gpu_inst_req_temp_if),
.csr_req_if (csr_req_temp_if)
.bckE_req_if (bckE_req_if),
.gpr_data_if (gpr_datf_if),
.exec_unit_req_if (exec_unit_req_temp_if),
.lsu_req_if (lsu_req_temp_if),
.gpu_inst_req_if (gpu_inst_req_temp_if),
.csr_req_if (csr_req_temp_if)
);
`DEBUG_BEGIN
wire is_lsu = (|lsu_req_temp_if.valid);
@ -98,12 +98,12 @@ module VX_gpr_stage (
VX_generic_register #(
.N(1)
) delayed_reg (
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(stall_rest),
.in (stall_lsu),
.out (delayed_lsu_last_cycle)
.clk (clk),
.reset (reset),
.stall (stall_rest),
.flush (stall_rest),
.in (stall_lsu),
.out (delayed_lsu_last_cycle)
);
wire[`NUM_THREADS-1:0][31:0] temp_store_data;
@ -117,12 +117,12 @@ module VX_gpr_stage (
VX_generic_register #(
.N(`NUM_THREADS*32*2)
) lsu_data (
.clk (clk),
.reset(reset),
.stall(!store_curr_real),
.flush(stall_rest),
.in ({real_store_data, real_base_address}),
.out ({temp_store_data, temp_base_address})
.clk (clk),
.reset (reset),
.stall (!store_curr_real),
.flush (stall_rest),
.in ({real_store_data, real_base_address}),
.out ({temp_store_data, temp_base_address})
);
assign real_store_data = lsu_req_temp_if.store_data;
@ -145,12 +145,12 @@ module VX_gpr_stage (
VX_generic_register #(
.N(224 + `NW_BITS-1 + 1 + (`NUM_THREADS))
) exec_unit_reg (
.clk (clk),
.reset(reset),
.stall(stall_exec),
.flush(flush_exec),
.in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.PC_next, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.jalQual, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.ebreak, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}),
.out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.PC_next , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.jalQual , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.ebreak , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask })
.clk (clk),
.reset (reset),
.stall (stall_exec),
.flush (flush_exec),
.in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.PC_next, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.jalQual, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.ebreak, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}),
.out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.PC_next , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.jalQual , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.ebreak , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask })
);
assign exec_unit_req_if.a_reg_data = real_base_address;
@ -159,26 +159,26 @@ module VX_gpr_stage (
VX_generic_register #(
.N(36 + `NW_BITS-1 + 1 + (`NUM_THREADS))
) gpu_inst_reg (
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(flush_rest),
.in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.pc_next}),
.out ({gpgpu_inst_req_if.valid , gpgpu_inst_req_if.warp_num , gpgpu_inst_req_if.is_wspawn , gpgpu_inst_req_if.is_tmc , gpgpu_inst_req_if.is_split , gpgpu_inst_req_if.is_barrier , gpgpu_inst_req_if.pc_next })
.clk (clk),
.reset (reset),
.stall (stall_rest),
.flush (flush_rest),
.in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.pc_next}),
.out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.pc_next })
);
assign gpgpu_inst_req_if.a_reg_data = real_base_address;
assign gpgpu_inst_req_if.rd2 = real_store_data;
assign gpu_inst_req_if.a_reg_data = real_base_address;
assign gpu_inst_req_if.rd2 = real_store_data;
VX_generic_register #(
.N(`NW_BITS-1 + 1 + `NUM_THREADS + 58)
) csr_reg (
.clk (clk),
.reset(reset),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}),
.out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask })
.clk (clk),
.reset (reset),
.stall (stall_gpr_csr),
.flush (flush_rest),
.in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}),
.out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask })
);
`else
@ -187,45 +187,45 @@ module VX_gpr_stage (
VX_generic_register #(
.N(77 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS))
) lsu_reg (
.clk (clk),
.reset(reset),
.stall(stall_lsu),
.flush(flush_lsu),
.in ({lsu_req_temp_if.valid, lsu_req_temp_if.lsu_pc, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_address, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}),
.out ({lsu_req_if.valid , lsu_req_if.lsu_pc , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_address , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb })
.clk (clk),
.reset (reset),
.stall (stall_lsu),
.flush (flush_lsu),
.in ({lsu_req_temp_if.valid, lsu_req_temp_if.lsu_pc, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_address, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}),
.out ({lsu_req_if.valid , lsu_req_if.lsu_pc , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_address , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb })
);
VX_generic_register #(
.N(224 + `NW_BITS-1 + 1 + 65*(`NUM_THREADS))
) exec_unit_reg (
.clk (clk),
.reset(reset),
.stall(stall_exec),
.flush(flush_exec),
.in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.PC_next, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.jalQual, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.ebreak, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}),
.out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.PC_next , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.jalQual , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.ebreak , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask })
.clk (clk),
.reset (reset),
.stall (stall_exec),
.flush (flush_exec),
.in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.PC_next, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.jalQual, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.ebreak, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}),
.out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.PC_next , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.jalQual , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.ebreak , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask })
);
VX_generic_register #(
.N(68 + `NW_BITS-1 + 1 + 33*(`NUM_THREADS))
) gpu_inst_reg (
.clk (clk),
.reset(reset),
.stall(stall_rest),
.flush(flush_rest),
.in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.pc_next, gpu_inst_req_temp_if.a_reg_data, gpu_inst_req_temp_if.rd2}),
.out ({gpgpu_inst_req_if.valid , gpgpu_inst_req_if.warp_num , gpgpu_inst_req_if.is_wspawn , gpgpu_inst_req_if.is_tmc , gpgpu_inst_req_if.is_split , gpgpu_inst_req_if.is_barrier , gpgpu_inst_req_if.pc_next , gpgpu_inst_req_if.a_reg_data , gpgpu_inst_req_if.rd2 })
.clk (clk),
.reset (reset),
.stall (stall_rest),
.flush (flush_rest),
.in ({gpu_inst_req_temp_if.valid, gpu_inst_req_temp_if.warp_num, gpu_inst_req_temp_if.is_wspawn, gpu_inst_req_temp_if.is_tmc, gpu_inst_req_temp_if.is_split, gpu_inst_req_temp_if.is_barrier, gpu_inst_req_temp_if.pc_next, gpu_inst_req_temp_if.a_reg_data, gpu_inst_req_temp_if.rd2}),
.out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.pc_next , gpu_inst_req_if.a_reg_data , gpu_inst_req_if.rd2 })
);
VX_generic_register #(
.N(`NW_BITS-1 + 1 + `NUM_THREADS + 58)
) csr_reg (
.clk (clk),
.reset(reset),
.stall(stall_gpr_csr),
.flush(flush_rest),
.in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}),
.out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask })
.clk (clk),
.reset (reset),
.stall (stall_gpr_csr),
.flush (flush_rest),
.in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}),
.out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask })
);
`endif

2
hw/rtl/VX_gpr_wrapper.v
View file

@ -50,7 +50,7 @@ module VX_gpr_wrapper (
generate
for (warp_index = 0; warp_index < `NUM_WARPS; warp_index = warp_index + 1) begin : warp_gprs
wire valid_write_request = warp_index == writeback_if.wb_warp_num;
wire valid_write_request = warp_index == writeback_if.warp_num;
VX_gpr gpr(
.clk (clk),
.reset (reset),

46
hw/rtl/VX_gpgpu_inst.v → hw/rtl/VX_gpu_inst.v
View file

@ -1,51 +1,51 @@
`include "VX_define.vh"
module VX_gpgpu_inst (
module VX_gpu_inst (
// Input
VX_gpgpu_inst_req_if gpgpu_inst_req_if,
VX_gpu_inst_req_if gpu_inst_req_if,
// Output
VX_warp_ctl_if warp_ctl_if
);
wire[`NUM_THREADS-1:0] curr_valids = gpgpu_inst_req_if.valid;
wire is_split = (gpgpu_inst_req_if.is_split);
wire[`NUM_THREADS-1:0] curr_valids = gpu_inst_req_if.valid;
wire is_split = (gpu_inst_req_if.is_split);
wire[`NUM_THREADS-1:0] tmc_new_mask;
wire all_threads = `NUM_THREADS < gpgpu_inst_req_if.a_reg_data[0];
wire all_threads = `NUM_THREADS < gpu_inst_req_if.a_reg_data[0];
genvar curr_t;
generate
for (curr_t = 0; curr_t < `NUM_THREADS; curr_t=curr_t+1) begin : tmc_new_mask_init
assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < gpgpu_inst_req_if.a_reg_data[0];
assign tmc_new_mask[curr_t] = all_threads ? 1 : curr_t < gpu_inst_req_if.a_reg_data[0];
end
endgenerate
wire valid_inst = (|curr_valids);
assign warp_ctl_if.warp_num = gpgpu_inst_req_if.warp_num;
assign warp_ctl_if.change_mask = (gpgpu_inst_req_if.is_tmc) && valid_inst;
assign warp_ctl_if.thread_mask = gpgpu_inst_req_if.is_tmc ? tmc_new_mask : 0;
assign warp_ctl_if.warp_num = gpu_inst_req_if.warp_num;
assign warp_ctl_if.change_mask = (gpu_inst_req_if.is_tmc) && valid_inst;
assign warp_ctl_if.thread_mask = gpu_inst_req_if.is_tmc ? tmc_new_mask : 0;
// assign warp_ctl_if.ebreak = (gpgpu_inst_req_if.a_reg_data[0] == 0) && valid_inst;
// assign warp_ctl_if.ebreak = (gpu_inst_req_if.a_reg_data[0] == 0) && valid_inst;
assign warp_ctl_if.ebreak = warp_ctl_if.change_mask && (warp_ctl_if.thread_mask == 0);
wire wspawn = gpgpu_inst_req_if.is_wspawn;
wire[31:0] wspawn_pc = gpgpu_inst_req_if.rd2;
wire all_active = `NUM_WARPS < gpgpu_inst_req_if.a_reg_data[0];
wire wspawn = gpu_inst_req_if.is_wspawn;
wire[31:0] wspawn_pc = gpu_inst_req_if.rd2;
wire all_active = `NUM_WARPS < gpu_inst_req_if.a_reg_data[0];
wire[`NUM_WARPS-1:0] wspawn_new_active;
genvar curr_w;
generate
for (curr_w = 0; curr_w < `NUM_WARPS; curr_w=curr_w+1) begin : wspawn_new_active_init
assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < gpgpu_inst_req_if.a_reg_data[0];
assign wspawn_new_active[curr_w] = all_active ? 1 : curr_w < gpu_inst_req_if.a_reg_data[0];
end
endgenerate
assign warp_ctl_if.is_barrier = gpgpu_inst_req_if.is_barrier && valid_inst;
assign warp_ctl_if.barrier_id = gpgpu_inst_req_if.a_reg_data[0];
assign warp_ctl_if.is_barrier = gpu_inst_req_if.is_barrier && valid_inst;
assign warp_ctl_if.barrier_id = gpu_inst_req_if.a_reg_data[0];
`DEBUG_BEGIN
wire[31:0] num_warps_m1 = gpgpu_inst_req_if.rd2 - 1;
wire[31:0] num_warps_m1 = gpu_inst_req_if.rd2 - 1;
`DEBUG_END
assign warp_ctl_if.num_warps = num_warps_m1[$clog2(`NUM_WARPS):0];
@ -61,7 +61,7 @@ module VX_gpgpu_inst (
genvar curr_s_t;
generate
for (curr_s_t = 0; curr_s_t < `NUM_THREADS; curr_s_t=curr_s_t+1) begin : masks_init
wire curr_bool = (gpgpu_inst_req_if.a_reg_data[curr_s_t] == 32'b1);
wire curr_bool = (gpu_inst_req_if.a_reg_data[curr_s_t] == 32'b1);
assign split_new_use_mask[curr_s_t] = curr_valids[curr_s_t] & (curr_bool);
assign split_new_later_mask[curr_s_t] = curr_valids[curr_s_t] & (!curr_bool);
@ -83,11 +83,11 @@ module VX_gpgpu_inst (
assign warp_ctl_if.dont_split = warp_ctl_if.is_split && ((split_new_use_mask == 0) || (split_new_use_mask == {`NUM_THREADS{1'b1}}));
assign warp_ctl_if.split_new_mask = split_new_use_mask;
assign warp_ctl_if.split_later_mask = split_new_later_mask;
assign warp_ctl_if.split_save_pc = gpgpu_inst_req_if.pc_next;
assign warp_ctl_if.split_warp_num = gpgpu_inst_req_if.warp_num;
assign warp_ctl_if.split_save_pc = gpu_inst_req_if.pc_next;
assign warp_ctl_if.split_warp_num = gpu_inst_req_if.warp_num;
// gpgpu_inst_req_if.is_wspawn
// gpgpu_inst_req_if.is_split
// gpgpu_inst_req_if.is_barrier
// gpu_inst_req_if.is_wspawn
// gpu_inst_req_if.is_split
// gpu_inst_req_if.is_barrier
endmodule

40
hw/rtl/VX_icache_stage.v
View file

@ -19,21 +19,22 @@ module VX_icache_stage (
wire valid_inst = (|fe_inst_meta_fi.valid);
// Icache Request
assign icache_req_if.core_req_valid = valid_inst && !total_freeze;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_data = 32'b0;
assign icache_req_if.core_req_read = `LW_MEM_READ;
assign icache_req_if.core_req_write = `NO_MEM_WRITE;
assign icache_req_if.core_req_rd = 5'b0;
assign icache_req_if.core_req_wb = {1{2'b1}};
assign icache_req_if.core_req_warp_num = fe_inst_meta_fi.warp_num;
assign icache_req_if.core_req_pc = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_valid = valid_inst && !total_freeze;
assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc;
assign icache_req_if.core_req_data = 32'b0;
assign icache_req_if.core_req_read = `WORD_SEL_LW;
assign icache_req_if.core_req_write = `WORD_SEL_NO;
assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num};
`IGNORE_WARNINGS_BEGIN
wire[4:0] rsp_rd;
wire[1:0] rsp_wb;
`IGNORE_WARNINGS_END
assign {fe_inst_meta_id.inst_pc, rsp_wb, rsp_rd, fe_inst_meta_id.warp_num} = icache_rsp_if.core_rsp_tag;
assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_data[0][31:0];
assign fe_inst_meta_id.inst_pc = icache_rsp_if.core_rsp_pc[0];
assign fe_inst_meta_id.warp_num = icache_rsp_if.core_rsp_warp_num;
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? threads_active[icache_rsp_if.core_rsp_warp_num] : 0;
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? threads_active[fe_inst_meta_id.warp_num] : 0;
assign icache_stage_wid = fe_inst_meta_id.warp_num;
assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
@ -47,14 +48,23 @@ module VX_icache_stage (
integer w;
always @(posedge clk) begin
if (reset) begin
for (w = 0; w < `NUM_WARPS; w=w+1) begin
for (w = 0; w < `NUM_WARPS; w = w + 1) begin
threads_active[w] <= 0;
end
end else begin
if (valid_inst && !icache_stage_delay) begin
threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;
threads_active[fe_inst_meta_fi.warp_num] <= fe_inst_meta_fi.valid;
end
end
end
/*always_comb begin
if (1'($time & 1) && icache_req_if.core_req_ready && icache_req_if.core_req_valid) begin
$display("*** %t: I$ req: pc=%0h, warp=%d", $time, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
end
if (1'($time & 1) && icache_rsp_if.core_rsp_ready && icache_rsp_if.core_rsp_valid) begin
$display("*** %t: I$ rsp: pc=%0h, warp=%d, instr=%0h", $time, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
end
end*/
endmodule

22
hw/rtl/VX_inst_multiplex.v
View file

@ -8,7 +8,7 @@ module VX_inst_multiplex (
// Outputs
VX_exec_unit_req_if exec_unit_req_if,
VX_lsu_req_if lsu_req_if,
VX_gpgpu_inst_req_if gpgpu_inst_req_if,
VX_gpu_inst_req_if gpu_inst_req_if,
VX_csr_req_if csr_req_if
);
@ -16,7 +16,7 @@ module VX_inst_multiplex (
wire[`NUM_THREADS-1:0] is_gpu_mask;
wire[`NUM_THREADS-1:0] is_csr_mask;
wire is_mem = (bckE_req_if.mem_write != `NO_MEM_WRITE) || (bckE_req_if.mem_read != `NO_MEM_READ);
wire is_mem = (bckE_req_if.mem_write != `WORD_SEL_NO) || (bckE_req_if.mem_read != `WORD_SEL_NO);
wire is_gpu = (bckE_req_if.is_wspawn || bckE_req_if.is_tmc || bckE_req_if.is_barrier || bckE_req_if.is_split);
wire is_csr = bckE_req_if.is_csr;
// wire is_gpu = 0;
@ -68,15 +68,15 @@ module VX_inst_multiplex (
// GPR Req
assign gpgpu_inst_req_if.valid = bckE_req_if.valid & is_gpu_mask;
assign gpgpu_inst_req_if.warp_num = bckE_req_if.warp_num;
assign gpgpu_inst_req_if.is_wspawn = bckE_req_if.is_wspawn;
assign gpgpu_inst_req_if.is_tmc = bckE_req_if.is_tmc;
assign gpgpu_inst_req_if.is_split = bckE_req_if.is_split;
assign gpgpu_inst_req_if.is_barrier = bckE_req_if.is_barrier;
assign gpgpu_inst_req_if.a_reg_data = gpr_data_if.a_reg_data;
assign gpgpu_inst_req_if.rd2 = gpr_data_if.b_reg_data[0];
assign gpgpu_inst_req_if.pc_next = bckE_req_if.PC_next;
assign gpu_inst_req_if.valid = bckE_req_if.valid & is_gpu_mask;
assign gpu_inst_req_if.warp_num = bckE_req_if.warp_num;
assign gpu_inst_req_if.is_wspawn = bckE_req_if.is_wspawn;
assign gpu_inst_req_if.is_tmc = bckE_req_if.is_tmc;
assign gpu_inst_req_if.is_split = bckE_req_if.is_split;
assign gpu_inst_req_if.is_barrier = bckE_req_if.is_barrier;
assign gpu_inst_req_if.a_reg_data = gpr_data_if.a_reg_data;
assign gpu_inst_req_if.rd2 = gpr_data_if.b_reg_data[0];
assign gpu_inst_req_if.pc_next = bckE_req_if.PC_next;
// CSR Req

54
hw/rtl/VX_l1c_to_dram_arb.v Normal file
View file

@ -0,0 +1,54 @@
`include "VX_define.vh"
module VX_l1c_to_dram_arb #(
parameter REQQ_SIZE = 8
) (
input wire clk,
input wire reset,
VX_cache_dram_req_if dcache_dram_req_if,
VX_cache_dram_rsp_if dcache_dram_rsp_if,
VX_cache_dram_req_if icache_dram_req_if,
VX_cache_dram_rsp_if icache_dram_rsp_if,
VX_cache_dram_req_if dram_req_if,
VX_cache_dram_rsp_if dram_rsp_if
);
reg cache_sel;
wire icache_req_valid, icache_sel_out, icache_sel_in;
assign icache_req_valid = icache_dram_req_if.dram_req_read || icache_dram_req_if.dram_req_write;
assign icache_sel_out = icache_req_valid && (cache_sel == 0);
assign dram_req_if.dram_req_read = icache_sel_out ? icache_dram_req_if.dram_req_read : dcache_dram_req_if.dram_req_read;
assign dram_req_if.dram_req_write = icache_sel_out ? icache_dram_req_if.dram_req_write : dcache_dram_req_if.dram_req_write;
assign dram_req_if.dram_req_addr = icache_sel_out ? icache_dram_req_if.dram_req_addr : dcache_dram_req_if.dram_req_addr;
assign dram_req_if.dram_req_data = icache_sel_out ? icache_dram_req_if.dram_req_data : dcache_dram_req_if.dram_req_data;
assign dram_req_if.dram_req_tag = {icache_sel_out ? icache_dram_req_if.dram_req_tag : dcache_dram_req_if.dram_req_tag, icache_sel_out};
assign icache_dram_req_if.dram_req_ready = dram_req_if.dram_req_ready && (cache_sel == 0);
assign dcache_dram_req_if.dram_req_ready = dram_req_if.dram_req_ready && (cache_sel == 1);
assign icache_sel_in = dram_rsp_if.dram_rsp_tag[0];
assign icache_dram_rsp_if.dram_rsp_valid = dram_rsp_if.dram_rsp_valid && icache_sel_in;
assign icache_dram_rsp_if.dram_rsp_data = dram_rsp_if.dram_rsp_data;
assign icache_dram_rsp_if.dram_rsp_tag = dram_rsp_if.dram_rsp_tag[1 +: $bits(icache_dram_rsp_if.dram_rsp_tag)];
assign dcache_dram_rsp_if.dram_rsp_valid = dram_rsp_if.dram_rsp_valid && ~icache_sel_in;
assign dcache_dram_rsp_if.dram_rsp_data = dram_rsp_if.dram_rsp_data;
assign dcache_dram_rsp_if.dram_rsp_tag = dram_rsp_if.dram_rsp_tag[1 +: $bits(dcache_dram_rsp_if.dram_rsp_tag)];
assign dram_rsp_if.dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready && dcache_dram_rsp_if.dram_rsp_ready;
always @(posedge clk) begin
if (reset) begin
cache_sel <= 0;
end else begin
cache_sel <= ~cache_sel;
end
end
endmodule

65
hw/rtl/VX_lsu_unit.v
View file

@ -3,19 +3,22 @@
module VX_lsu_unit (
input wire clk,
input wire reset,
input wire no_slot_mem,
VX_lsu_req_if lsu_req_if,
// Write back to GPR
VX_inst_mem_wb_if mem_wb_if,
VX_wb_if mem_wb_if,
// Dcache interface
VX_cache_core_rsp_if dcache_rsp_if,
VX_cache_core_req_if dcache_req_if,
output wire delay
);
// Generate Addresses
wire[`NUM_THREADS-1:0][31:0] address;
VX_lsu_addr_gen VX_lsu_addr_gen (
VX_lsu_addr_gen VX_lsu_addr_gen (
.base_address (lsu_req_if.base_address),
.offset (lsu_req_if.offset),
.address (address)
@ -24,12 +27,13 @@ module VX_lsu_unit (
wire[`NUM_THREADS-1:0][31:0] use_address;
wire[`NUM_THREADS-1:0][31:0] use_store_data;
wire[`NUM_THREADS-1:0] use_valid;
wire[2:0] use_mem_read;
wire[2:0] use_mem_write;
wire[`WORD_SEL_BITS-1:0] use_mem_read;
wire[`WORD_SEL_BITS-1:0] use_mem_write;
wire[4:0] use_rd;
wire[`NW_BITS-1:0] use_warp_num;
wire[1:0] use_wb;
wire[31:0] use_pc;
wire[(`LOG2UP(`NUM_THREADS))-1:0] tag_index;
wire zero = 0;
@ -45,44 +49,39 @@ module VX_lsu_unit (
);
// Core Request
assign dcache_req_if.core_req_valid = use_valid;
assign dcache_req_if.core_req_addr = use_address;
assign dcache_req_if.core_req_data = use_store_data;
assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}};
assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}};
assign dcache_req_if.core_req_rd = use_rd;
assign dcache_req_if.core_req_wb = {`NUM_THREADS{use_wb}};
assign dcache_req_if.core_req_warp_num = use_warp_num;
assign dcache_req_if.core_req_pc = use_pc;
// Core can't accept response
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
// Cache can't accept request
assign dcache_req_if.core_req_valid = use_valid;
assign dcache_req_if.core_req_read = {`NUM_THREADS{use_mem_read}};
assign dcache_req_if.core_req_write = {`NUM_THREADS{use_mem_write}};
assign dcache_req_if.core_req_addr = use_address;
assign dcache_req_if.core_req_data = use_store_data;
assign dcache_req_if.core_req_tag = {`NUM_THREADS{use_pc, use_wb, use_rd, use_warp_num}};
assign delay = ~dcache_req_if.core_req_ready;
// Core Response
assign mem_wb_if.rd = dcache_rsp_if.core_rsp_read;
assign mem_wb_if.wb = dcache_rsp_if.core_rsp_write;
assign mem_wb_if.wb_valid = dcache_rsp_if.core_rsp_valid;
assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_rsp_warp_num;
assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_data;
wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
`DEBUG_BEGIN
wire found;
`DEBUG_END
assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid;
assign mem_wb_if.data = dcache_rsp_if.core_rsp_data;
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
assign {mem_wb_if.pc, mem_wb_if.wb, mem_wb_if.rd, mem_wb_if.warp_num} = dcache_rsp_if.core_rsp_tag[tag_index];
// select first valid entry in tag array
VX_generic_priority_encoder #(
.N(`NUM_THREADS)
) pick_first_pc (
) tag_select (
.valids(dcache_rsp_if.core_rsp_valid),
.index (use_pc_index),
.found (found)
.index (tag_index),
`IGNORE_WARNINGS_BEGIN
.found ()
`IGNORE_WARNINGS_END
);
assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_rsp_pc[use_pc_index];
/*always_comb begin
if (1'($time & 1) && dcache_req_if.core_req_ready && |dcache_req_if.core_req_valid) begin
$display("*** %t: D$ req: valid=%b, addr=%0h, r=%d, w=%d, rd=%d, warp=%d, data=%0h", $time, use_valid, use_address, use_mem_read, use_mem_write, use_rd, use_warp_num, use_store_data);
end
if (1'($time & 1) && dcache_rsp_if.core_rsp_ready && |dcache_rsp_if.core_rsp_valid) begin
$display("*** %t: D$ rsp: valid=%b, rd=%d, warp=%d, data=%0h", $time, dcache_rsp_if.core_rsp_valid, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
end
end*/
endmodule // Memory

10
hw/rtl/VX_scheduler.v
View file

@ -18,15 +18,15 @@ module VX_scheduler (
reg[31:0][`NUM_THREADS-1:0] rename_table[`NUM_WARPS-1:0];
wire valid_wb = (writeback_if.wb != 0) && (|writeback_if.wb_valid) && (writeback_if.rd != 0);
wire valid_wb = (writeback_if.wb != 0) && (|writeback_if.valid) && (writeback_if.rd != 0);
wire wb_inc = (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0);
wire rs1_rename = rename_table[bckE_req_if.warp_num][bckE_req_if.rs1] != 0;
wire rs2_rename = rename_table[bckE_req_if.warp_num][bckE_req_if.rs2] != 0;
wire rd_rename = rename_table[bckE_req_if.warp_num][bckE_req_if.rd ] != 0;
wire is_store = (bckE_req_if.mem_write != `NO_MEM_WRITE);
wire is_load = (bckE_req_if.mem_read != `NO_MEM_READ);
wire is_store = (bckE_req_if.mem_write != `WORD_SEL_NO);
wire is_load = (bckE_req_if.mem_read != `WORD_SEL_NO);
// classify our next instruction.
wire is_mem = is_store || is_load;
@ -58,7 +58,7 @@ module VX_scheduler (
end
end else begin
if (valid_wb) begin
rename_table[writeback_if.wb_warp_num][writeback_if.rd] <= rename_table[writeback_if.wb_warp_num][writeback_if.rd] & (~writeback_if.wb_valid);
rename_table[writeback_if.warp_num][writeback_if.rd] <= rename_table[writeback_if.warp_num][writeback_if.rd] & (~writeback_if.valid);
end
if (!schedule_delay && wb_inc) begin
@ -66,7 +66,7 @@ module VX_scheduler (
end
if (valid_wb
&& (0 == (rename_table[writeback_if.wb_warp_num][writeback_if.rd] & ~writeback_if.wb_valid))) begin
&& (0 == (rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid))) begin
count_valid <= count_valid - 1;
end

2
hw/rtl/VX_warp_sched.v
View file

@ -124,7 +124,7 @@ module VX_warp_sched (
end
use_wsapwn_pc <= 0;
use_wsapwn <= 0;
warp_pcs[0] <= (`STARTUP_ADDR - 4);
warp_pcs[0] <= `STARTUP_ADDR;
warp_active[0] <= 1; // Activating first warp
visible_active[0] <= 1; // Activating first warp
thread_masks[0] <= 1; // Activating first thread in first warp

71
hw/rtl/VX_writeback.v
View file

@ -3,12 +3,15 @@
module VX_writeback (
input wire clk,
input wire reset,
// Mem WB info
VX_inst_mem_wb_if mem_wb_if,
VX_wb_if mem_wb_if,
// EXEC Unit WB info
VX_inst_exec_wb_if inst_exec_wb_if,
VX_wb_if inst_exec_wb_if,
// CSR Unit WB info
VX_csr_wb_if csr_wb_if,
VX_wb_if csr_wb_if,
// Actual WB to GPR
VX_wb_if writeback_if,
@ -17,45 +20,45 @@ module VX_writeback (
output wire no_slot_csr
);
VX_wb_if writeback_tempp_if();
VX_wb_if writeback_tmp_if();
wire exec_wb = (inst_exec_wb_if.wb != 0) && (|inst_exec_wb_if.wb_valid);
wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.wb_valid);
wire exec_wb = (inst_exec_wb_if.wb != 0) && (|inst_exec_wb_if.valid);
wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.valid);
wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
assign no_slot_csr = csr_wb && (exec_wb);
assign no_slot_exec = 0;
assign writeback_tempp_if.write_data = exec_wb ? inst_exec_wb_if.alu_result :
csr_wb ? csr_wb_if.csr_result :
mem_wb ? mem_wb_if.loaded_data :
0;
assign writeback_tmp_if.data = exec_wb ? inst_exec_wb_if.data :
csr_wb ? csr_wb_if.data :
mem_wb ? mem_wb_if.data :
0;
assign writeback_tempp_if.wb_valid = exec_wb ? inst_exec_wb_if.wb_valid :
csr_wb ? csr_wb_if.valid :
mem_wb ? mem_wb_if.wb_valid :
0;
assign writeback_tmp_if.valid = exec_wb ? inst_exec_wb_if.valid :
csr_wb ? csr_wb_if.valid :
mem_wb ? mem_wb_if.valid :
0;
assign writeback_tempp_if.rd = exec_wb ? inst_exec_wb_if.rd :
csr_wb ? csr_wb_if.rd :
mem_wb ? mem_wb_if.rd :
0;
assign writeback_tmp_if.rd = exec_wb ? inst_exec_wb_if.rd :
csr_wb ? csr_wb_if.rd :
mem_wb ? mem_wb_if.rd :
0;
assign writeback_tempp_if.wb = exec_wb ? inst_exec_wb_if.wb :
csr_wb ? csr_wb_if.wb :
mem_wb ? mem_wb_if.wb :
0;
assign writeback_tmp_if.wb = exec_wb ? inst_exec_wb_if.wb :
csr_wb ? csr_wb_if.wb :
mem_wb ? mem_wb_if.wb :
0;
assign writeback_tempp_if.wb_warp_num = exec_wb ? inst_exec_wb_if.wb_warp_num :
csr_wb ? csr_wb_if.warp_num :
mem_wb ? mem_wb_if.wb_warp_num :
0;
assign writeback_tmp_if.warp_num = exec_wb ? inst_exec_wb_if.warp_num :
csr_wb ? csr_wb_if.warp_num :
mem_wb ? mem_wb_if.warp_num :
0;
assign writeback_tempp_if.wb_pc = exec_wb ? inst_exec_wb_if.exec_wb_pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? mem_wb_if.mem_wb_pc :
32'hdeadbeef;
assign writeback_tmp_if.pc = exec_wb ? inst_exec_wb_if.pc :
csr_wb ? 32'hdeadbeef :
mem_wb ? mem_wb_if.pc :
32'hdeadbeef;
wire zero = 0;
@ -68,19 +71,19 @@ module VX_writeback (
.reset(reset),
.stall(zero),
.flush(zero),
.in ({writeback_tempp_if.write_data, writeback_tempp_if.wb_valid, writeback_tempp_if.rd, writeback_tempp_if.wb, writeback_tempp_if.wb_warp_num, writeback_tempp_if.wb_pc}),
.out ({use_wb_data , writeback_if.wb_valid, writeback_if.rd, writeback_if.wb, writeback_if.wb_warp_num, writeback_if.wb_pc})
.in ({writeback_tmp_if.data, writeback_tmp_if.valid, writeback_tmp_if.rd, writeback_tmp_if.wb, writeback_tmp_if.warp_num, writeback_tmp_if.pc}),
.out ({use_wb_data, writeback_if.valid, writeback_if.rd, writeback_if.wb, writeback_if.warp_num, writeback_if.pc})
);
reg [31:0] last_data_wb /* verilator public */;
always @(posedge clk) begin
if ((|writeback_if.wb_valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
if ((|writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
last_data_wb <= use_wb_data[0];
end
end
assign writeback_if.write_data = use_wb_data;
assign writeback_if.data = use_wb_data;
endmodule : VX_writeback

253
hw/rtl/Vortex.v
View file

@ -15,41 +15,36 @@ module Vortex #(
// DRAM Dcache Req
output wire D_dram_req_read,
output wire D_dram_req_write,
output wire [31:0] D_dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] D_dram_req_data,
output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
input wire D_dram_req_ready,
// DRAM Dcache Rsp
input wire D_dram_rsp_valid,
input wire [31:0] D_dram_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] D_dram_rsp_data,
input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
output wire D_dram_rsp_ready,
// DRAM Icache Req
output wire I_dram_req_read,
output wire I_dram_req_write,
output wire [31:0] I_dram_req_addr,
output wire [`IBANK_LINE_SIZE-1:0] I_dram_req_data,
output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
input wire I_dram_req_ready,
// DRAM Icache Rsp
input wire I_dram_rsp_valid,
input wire [31:0] I_dram_rsp_addr,
input wire [`IBANK_LINE_SIZE-1:0] I_dram_rsp_data,
input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
output wire I_dram_rsp_ready,
// LLC Snooping
input wire llc_snp_req_valid,
input wire [31:0] llc_snp_req_addr,
input wire [`DDRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
// CSR request
//input wire csr_read_valid;
//input wire csr_write_valid;
//input wire [`CSR_WIDTH-1:0 csr_index;
//input wire csr_data_in;
//output wire [15:0] csr_data_out;
output wire ebreak
);
`DEBUG_BEGIN
@ -61,77 +56,98 @@ module Vortex #(
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_cache_core_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_core_req_qual_if();
// Dcache Interfaces
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_core_req_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) dcache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) dcache_dram_rsp_if();
VX_cache_core_req_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_core_req_qual_if();
assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.dram_rsp_addr = D_dram_rsp_addr;
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) dcache_core_rsp_if();
assign D_dram_req_write = dcache_dram_req_if.dram_req_write;
assign D_dram_req_read = dcache_dram_req_if.dram_req_read;
assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
assign D_dram_rsp_ready = dcache_dram_req_if.dram_rsp_ready;
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_req_if();
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if();
assign D_dram_req_write = dcache_dram_req_if.dram_req_write;
assign D_dram_req_read = dcache_dram_req_if.dram_req_read;
assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr;
assign D_dram_req_data = dcache_dram_req_if.dram_req_data;
assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag;
assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready;
genvar i;
generate
for (i = 0; i < `DBANK_LINE_WORDS; i=i+1) begin
assign dcache_dram_rsp_if.dram_rsp_data[i] = D_dram_rsp_data[i * 32 +: 32];
assign D_dram_req_data[i * 32 +: 32] = dcache_dram_req_if.dram_req_data[i];
end
endgenerate
assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data;
assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag;
assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready;
wire temp_io_valid = (!memory_delay)
&& (|dcache_core_req_if.core_req_valid)
&& (dcache_core_req_if.core_req_write[0] != `NO_MEM_WRITE)
&& (dcache_core_req_if.core_req_addr[0] == `IO_BUS_ADDR);
assign io_valid = (!memory_delay)
&& (|dcache_core_req_if.core_req_valid)
&& (dcache_core_req_if.core_req_write[0] != `WORD_SEL_NO)
&& (dcache_core_req_if.core_req_addr[0] == `IO_BUS_ADDR);
wire [31:0] temp_io_data = dcache_core_req_if.core_req_data[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
assign io_data = dcache_core_req_if.core_req_data[0];
assign dcache_core_req_qual_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~io_valid}};
assign dcache_core_req_qual_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_core_req_qual_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_core_req_qual_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_core_req_qual_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_core_req_qual_if.core_req_valid = dcache_core_req_if.core_req_valid & {`NUM_THREADS{~io_valid}};
assign dcache_core_req_qual_if.core_req_read = dcache_core_req_if.core_req_read;
assign dcache_core_req_qual_if.core_req_write = dcache_core_req_if.core_req_write;
assign dcache_core_req_qual_if.core_req_addr = dcache_core_req_if.core_req_addr;
assign dcache_core_req_qual_if.core_req_data = dcache_core_req_if.core_req_data;
assign dcache_core_req_qual_if.core_req_tag = dcache_core_req_if.core_req_tag;
assign dcache_core_req_if.core_req_ready = dcache_core_req_qual_if.core_req_ready;
assign dcache_core_req_qual_if.core_req_rd = dcache_core_req_if.core_req_rd;
assign dcache_core_req_qual_if.core_req_wb = dcache_core_req_if.core_req_wb;
assign dcache_core_req_qual_if.core_req_warp_num = dcache_core_req_if.core_req_warp_num;
assign dcache_core_req_qual_if.core_req_pc = dcache_core_req_if.core_req_pc;
VX_cache_core_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_rsp_if();
VX_cache_core_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_core_req_if();
// Icache interfaces
VX_cache_core_req_if #(
.NUM_REQUESTS(`INUM_REQUESTS),
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) icache_core_req_if();
VX_cache_dram_req_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_req_if();
VX_cache_dram_rsp_if #(.BANK_LINE_WORDS(`IBANK_LINE_WORDS)) icache_dram_rsp_if();
VX_cache_core_rsp_if #(
.NUM_REQUESTS(`INUM_REQUESTS),
.WORD_SIZE(`IWORD_SIZE),
.CORE_TAG_WIDTH(`CORE_REQ_TAG_WIDTH)
) icache_core_rsp_if();
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_req_if();
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_addr = I_dram_rsp_addr;
assign I_dram_req_write = icache_dram_req_if.dram_req_write;
assign I_dram_req_read = icache_dram_req_if.dram_req_read;
assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
assign I_dram_rsp_ready = icache_dram_req_if.dram_rsp_ready;
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_rsp_if();
assign I_dram_req_write = icache_dram_req_if.dram_req_write;
assign I_dram_req_read = icache_dram_req_if.dram_req_read;
assign I_dram_req_addr = icache_dram_req_if.dram_req_addr;
assign I_dram_req_data = icache_dram_req_if.dram_req_data;
assign I_dram_req_tag = icache_dram_req_if.dram_req_tag;
assign icache_dram_req_if.dram_req_ready = I_dram_req_ready;
genvar j;
generate
for (j = 0; j < `IBANK_LINE_WORDS; j = j + 1) begin
assign icache_dram_rsp_if.dram_rsp_data[j] = I_dram_rsp_data[j * 32 +: 32];
assign I_dram_req_data[j * 32 +: 32] = icache_dram_req_if.dram_req_data[j];
end
endgenerate
assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data;
assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag;
assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready;
///////////////////////////////////////////////////////////////////////////////
@ -139,7 +155,7 @@ module Vortex #(
VX_frE_to_bckE_req_if bckE_req_if(); // New instruction request to EXE/MEM
// Back-end to Front-end
VX_wb_if writeback_if(); // Writeback to GPRs
VX_wb_if writeback_if(); // Writeback to GPRs
VX_branch_rsp_if branch_rsp_if(); // Branch Resolution to Fetch
VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
@ -147,76 +163,77 @@ VX_jal_rsp_if jal_rsp_if(); // Jump resolution to Fetch
VX_warp_ctl_if warp_ctl_if();
// Cache snooping
VX_cache_snp_req_if icache_snp_req_if();
VX_cache_snp_req_if dcache_snp_req_if();
VX_cache_snp_req_if #(.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH)) icache_snp_req_if();
VX_cache_snp_req_if #(.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH)) dcache_snp_req_if();
assign dcache_snp_req_if.snp_req_valid = llc_snp_req_valid;
assign dcache_snp_req_if.snp_req_addr = llc_snp_req_addr;
assign llc_snp_req_ready = dcache_snp_req_if.snp_req_ready;
VX_front_end front_end (
.clk (clk),
.reset (reset),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.schedule_delay (schedule_delay),
.icache_rsp_if (icache_core_rsp_if),
.icache_req_if (icache_core_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.fetch_ebreak (ebreak)
.clk (clk),
.reset (reset),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.schedule_delay (schedule_delay),
.icache_rsp_if (icache_core_rsp_if),
.icache_req_if (icache_core_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.fetch_ebreak (ebreak)
);
VX_scheduler scheduler (
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay),
.bckE_req_if (bckE_req_if),
.writeback_if (writeback_if),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
.clk (clk),
.reset (reset),
.memory_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay(gpr_stage_delay),
.bckE_req_if (bckE_req_if),
.writeback_if (writeback_if),
.schedule_delay (schedule_delay),
.is_empty (scheduler_empty)
);
VX_back_end #(
.CORE_ID(CORE_ID)
) back_end (
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.dcache_rsp_if (dcache_core_rsp_if),
.dcache_req_if (dcache_core_req_if),
.writeback_if (writeback_if),
.mem_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
.clk (clk),
.reset (reset),
.schedule_delay (schedule_delay),
.warp_ctl_if (warp_ctl_if),
.bckE_req_if (bckE_req_if),
.jal_rsp_if (jal_rsp_if),
.branch_rsp_if (branch_rsp_if),
.dcache_rsp_if (dcache_core_rsp_if),
.dcache_req_if (dcache_core_req_if),
.writeback_if (writeback_if),
.mem_delay (memory_delay),
.exec_delay (exec_delay),
.gpr_stage_delay (gpr_stage_delay)
);
VX_dmem_ctrl dmem_ctrl (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Dram <-> Dcache
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
// Dram <-> Icache
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if),
.icache_snp_req_if (icache_snp_req_if),
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if),
.icache_snp_req_if (icache_snp_req_if),
// Core <-> Icache
.icache_core_req_if (icache_core_req_if),
.icache_core_rsp_if (icache_core_rsp_if),
.icache_core_req_if (icache_core_req_if),
.icache_core_rsp_if (icache_core_rsp_if),
// Core <-> Dcache
.dcache_core_req_if (dcache_core_req_qual_if),
.dcache_core_rsp_if (dcache_core_rsp_if)
.dcache_core_req_if (dcache_core_req_qual_if),
.dcache_core_rsp_if (dcache_core_rsp_if)
);
endmodule // Vortex

496
hw/rtl/Vortex_Cluster.v
View file

@ -15,248 +15,330 @@ module Vortex_Cluster #(
// DRAM Req
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
output wire[`L2DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L2DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L2DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM Rsp
input wire dram_rsp_valid,
input wire [31:0] dram_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
input wire[`L2DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L2DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// LLC Snooping
input wire llc_snp_req_valid,
input wire[31:0] llc_snp_req_addr,
input wire[`L2DRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
output wire ebreak
);
// DRAM Dcache Req
wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
wire[`NUM_CORES-1:0] [31:0] per_core_D_dram_req_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_D_dram_req_data;
if (`NUM_CORES == 1) begin
// DRAM Dcache Rsp
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
wire[`NUM_CORES-1:0] [31:0] per_core_D_dram_rsp_addr;
wire[`NUM_CORES-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_core_D_dram_rsp_data;
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_req_if();
// DRAM Icache Req
wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
wire[`NUM_CORES-1:0] per_core_I_dram_req_write;
wire[`NUM_CORES-1:0] [31:0] per_core_I_dram_req_addr;
wire[`NUM_CORES-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_req_data;
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if();
// DRAM Icache Rsp
wire[`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
wire[`NUM_CORES-1:0] [31:0] per_core_I_dram_rsp_addr;
wire[`NUM_CORES-1:0][`IBANK_LINE_WORDS-1:0][31:0] per_core_I_dram_rsp_data;
wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) icache_dram_req_if();
// Out ebreak
wire[`NUM_CORES-1:0] per_core_ebreak;
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_rsp_if();
wire[`NUM_CORES-1:0] per_core_io_valid;
wire[`NUM_CORES-1:0][31:0] per_core_io_data;
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`L2DRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`L2DRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`L2DRAM_TAG_WIDTH)
) dram_req_if();
wire l2c_core_req_ready;
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`L2DRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`L2DRAM_TAG_WIDTH)
) dram_rsp_if();
wire snp_fwd_valid;
wire[31:0] snp_fwd_addr;
wire[`NUM_CORES-1:0] snp_fwd_ready;
assign dram_req_read = dram_req_if.dram_req_read;
assign dram_req_write = dram_req_if.dram_req_write;
assign dram_req_addr = dram_req_if.dram_req_addr;
assign dram_req_data = dram_req_if.dram_req_data;
assign dram_req_tag = dram_req_if.dram_req_tag;
assign dram_req_if.dram_req_ready = dram_req_ready;
assign ebreak = (&per_core_ebreak);
assign dram_rsp_if.dram_rsp_valid = dram_rsp_valid;
assign dram_rsp_if.dram_rsp_data = dram_rsp_data;
assign dram_rsp_if.dram_rsp_tag = dram_rsp_tag;
assign dram_rsp_ready = dram_rsp_if.dram_rsp_ready;
genvar curr_core;
generate
VX_l1c_to_dram_arb #(
.REQQ_SIZE(`L2REQQ_SIZE)
) l1c_to_dram_arb (
.clk (clk),
.reset (reset),
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if),
.dram_req_if (dram_req_if),
.dram_rsp_if (dram_rsp_if)
);
for (curr_core = 0; curr_core < `NUM_CORES; curr_core=curr_core+1) begin
Vortex #(
.CORE_ID(0)
) vortex_core (
.clk (clk),
.reset (reset),
wire [`IBANK_LINE_WORDS-1:0][31:0] curr_core_D_dram_req_data;
wire [`DBANK_LINE_WORDS-1:0][31:0] curr_core_I_dram_req_data ;
.io_valid (io_valid[0]),
.io_data (io_data[0]),
.D_dram_req_read (dcache_dram_req_if.dram_req_read),
.D_dram_req_write (dcache_dram_req_if.dram_req_write),
.D_dram_req_addr (dcache_dram_req_if.dram_req_addr),
.D_dram_req_data (dcache_dram_req_if.dram_req_data),
.D_dram_req_tag (dcache_dram_req_if.dram_req_tag),
.D_dram_req_ready (dcache_dram_req_if.dram_req_ready),
assign io_valid[curr_core] = per_core_io_valid[curr_core];
assign io_data [curr_core] = per_core_io_data [curr_core];
.D_dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid),
.D_dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data),
.D_dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag),
.D_dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready),
.I_dram_req_read (icache_dram_req_if.dram_req_read),
.I_dram_req_write (icache_dram_req_if.dram_req_write),
.I_dram_req_addr (icache_dram_req_if.dram_req_addr),
.I_dram_req_data (icache_dram_req_if.dram_req_data),
.I_dram_req_tag (icache_dram_req_if.dram_req_tag),
.I_dram_req_ready (icache_dram_req_if.dram_req_ready),
.I_dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid),
.I_dram_rsp_data (icache_dram_rsp_if.dram_rsp_data),
.I_dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready),
.I_dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag),
.llc_snp_req_valid (llc_snp_req_valid),
.llc_snp_req_addr (llc_snp_req_addr),
.llc_snp_req_ready (llc_snp_req_ready),
.ebreak (ebreak)
);
end else begin
// DRAM Dcache Req
wire[`NUM_CORES-1:0] per_core_D_dram_req_read;
wire[`NUM_CORES-1:0] per_core_D_dram_req_write;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
// DRAM Dcache Rsp
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_rsp_data;
wire[`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
wire[`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
// DRAM Icache Req
wire[`NUM_CORES-1:0] per_core_I_dram_req_read;
wire[`NUM_CORES-1:0] per_core_I_dram_req_write;
wire[`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
// DRAM Icache Rsp
wire[`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
wire[`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_rsp_data;
wire[`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_rsp_tag;
wire[`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
// Out ebreak
wire[`NUM_CORES-1:0] per_core_ebreak;
wire[`NUM_CORES-1:0] per_core_io_valid;
wire[`NUM_CORES-1:0][31:0] per_core_io_data;
wire l2_core_req_ready;
wire snp_fwd_valid;
wire[`DDRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
wire[`NUM_CORES-1:0] per_core_snp_fwd_ready;
assign ebreak = (& per_core_ebreak);
genvar i;
for (i = 0; i < `NUM_CORES; i = i + 1) begin
wire [`IDRAM_LINE_WIDTH-1:0] curr_core_D_dram_req_data;
wire [`DDRAM_LINE_WIDTH-1:0] curr_core_I_dram_req_data;
assign io_valid[i] = per_core_io_valid[i];
assign io_data[i] = per_core_io_data[i];
Vortex #(
.CORE_ID(curr_core + (CLUSTER_ID * `NUM_CORES))
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) vortex_core (
.clk (clk),
.reset (reset),
.io_valid (per_core_io_valid [curr_core]),
.io_data (per_core_io_data [curr_core]),
.D_dram_req_read (per_core_D_dram_req_read [curr_core]),
.D_dram_req_write (per_core_D_dram_req_write [curr_core]),
.D_dram_req_addr (per_core_D_dram_req_addr [curr_core]),
.D_dram_req_data (curr_core_D_dram_req_data ),
.D_dram_req_ready (l2c_core_req_ready ),
.D_dram_rsp_valid (per_core_D_dram_rsp_valid [curr_core]),
.D_dram_rsp_addr (per_core_D_dram_rsp_addr [curr_core]),
.D_dram_rsp_data (per_core_D_dram_rsp_data [curr_core]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [curr_core]),
.I_dram_req_read (per_core_I_dram_req_read [curr_core]),
.I_dram_req_write (per_core_I_dram_req_write [curr_core]),
.I_dram_req_addr (per_core_I_dram_req_addr [curr_core]),
.I_dram_req_data (curr_core_I_dram_req_data ),
.I_dram_req_ready (l2c_core_req_ready ),
.I_dram_rsp_valid (per_core_I_dram_rsp_valid [curr_core]),
.I_dram_rsp_addr (per_core_I_dram_rsp_addr [curr_core]),
.I_dram_rsp_data (per_core_I_dram_rsp_data [curr_core]),
.I_dram_rsp_ready (per_core_I_dram_rsp_ready [curr_core]),
.llc_snp_req_valid (snp_fwd_valid),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_ready (snp_fwd_ready [curr_core]),
.ebreak (per_core_ebreak [curr_core])
.clk (clk),
.reset (reset),
.io_valid (per_core_io_valid [i]),
.io_data (per_core_io_data [i]),
.D_dram_req_read (per_core_D_dram_req_read [i]),
.D_dram_req_write (per_core_D_dram_req_write [i]),
.D_dram_req_addr (per_core_D_dram_req_addr [i]),
.D_dram_req_data (curr_core_D_dram_req_data ),
.D_dram_req_tag (per_core_D_dram_req_tag [i]),
.D_dram_req_ready (l2_core_req_ready ),
.D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]),
.D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
.I_dram_req_read (per_core_I_dram_req_read [i]),
.I_dram_req_write (per_core_I_dram_req_write [i]),
.I_dram_req_addr (per_core_I_dram_req_addr [i]),
.I_dram_req_data (curr_core_I_dram_req_data ),
.I_dram_req_tag (per_core_I_dram_req_tag [i]),
.I_dram_req_ready (l2_core_req_ready ),
.I_dram_rsp_valid (per_core_I_dram_rsp_valid [i]),
.I_dram_rsp_tag (per_core_I_dram_rsp_tag [i]),
.I_dram_rsp_data (per_core_I_dram_rsp_data [i]),
.I_dram_rsp_ready (per_core_I_dram_rsp_ready [i]),
.llc_snp_req_valid (snp_fwd_valid),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_ready (per_core_snp_fwd_ready [i]),
.ebreak (per_core_ebreak [i])
);
assign per_core_D_dram_req_data [curr_core] = curr_core_D_dram_req_data;
assign per_core_I_dram_req_data [curr_core] = curr_core_I_dram_req_data;
assign per_core_D_dram_req_data [i] = curr_core_D_dram_req_data;
assign per_core_I_dram_req_data [i] = curr_core_I_dram_req_data;
end
endgenerate
//////////////////// L2 Cache ////////////////////
wire[`L2NUM_REQUESTS-1:0] l2c_core_req_valid;
wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_write;
wire[`L2NUM_REQUESTS-1:0][2:0] l2c_core_req_mem_read;
wire[`L2NUM_REQUESTS-1:0][31:0] l2c_core_req_addr;
wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data;
wire[`L2NUM_REQUESTS-1:0][1:0] l2c_core_req_wb;
wire[`L2NUM_REQUESTS-1:0] l2c_core_rsp_ready;
wire[`L2NUM_REQUESTS-1:0] l2c_wb;
wire[`L2NUM_REQUESTS-1:0] [31:0] l2c_wb_addr;
wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_wb_data;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_rsp_data_port;
genvar llb_index;
generate
for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
assign dram_req_data [llb_index * `DWORD_SIZE_BITS +: `DWORD_SIZE_BITS] = dram_req_data_port[llb_index];
assign dram_rsp_data_port [llb_index] = dram_rsp_data[llb_index * `DWORD_SIZE_BITS +: `DWORD_SIZE_BITS];
end
endgenerate
genvar l2c_curr_core;
generate
for (l2c_curr_core = 0; l2c_curr_core < `L2NUM_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
// Core Request
assign l2c_core_req_valid [l2c_curr_core] = (per_core_D_dram_req_read[(l2c_curr_core/2)] | per_core_D_dram_req_write[(l2c_curr_core/2)]);
assign l2c_core_req_valid [l2c_curr_core+1] = (per_core_I_dram_req_read[(l2c_curr_core/2)] | per_core_I_dram_req_write[(l2c_curr_core/2)]);
assign l2c_core_req_mem_write [l2c_curr_core] = per_core_D_dram_req_write[(l2c_curr_core/2)] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l2c_core_req_mem_write [l2c_curr_core+1] = `NO_MEM_WRITE; // I caches don't write
assign l2c_core_req_mem_read [l2c_curr_core] = per_core_D_dram_req_read[(l2c_curr_core/2)] ? `LW_MEM_READ : `NO_MEM_READ;
assign l2c_core_req_mem_read [l2c_curr_core+1] = `LW_MEM_READ; // I caches don't write
assign l2c_core_req_wb [l2c_curr_core] = per_core_D_dram_req_read[(l2c_curr_core/2)] ? 1 : 0;
assign l2c_core_req_wb [l2c_curr_core+1] = 1; // I caches don't write
assign l2c_core_req_addr [l2c_curr_core] = per_core_D_dram_req_addr [(l2c_curr_core/2)];
assign l2c_core_req_addr [l2c_curr_core+1] = per_core_I_dram_req_addr[(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core] = per_core_D_dram_req_data [(l2c_curr_core/2)];
assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)];
// Core can't accept Response
assign l2c_core_rsp_ready [l2c_curr_core] = per_core_D_dram_rsp_ready [(l2c_curr_core/2)];
assign l2c_core_rsp_ready [l2c_curr_core+1] = per_core_I_dram_rsp_ready[(l2c_curr_core/2)];
// Cache Fill Response
assign per_core_D_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
assign per_core_I_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core+1];
assign per_core_D_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core];
assign per_core_I_dram_rsp_data [(l2c_curr_core/2)] = l2c_wb_data[l2c_curr_core+1];
assign per_core_D_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_rsp_addr [(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
end
endgenerate
VX_cache #(
.CACHE_SIZE_BYTES (`L2CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`L2BANK_LINE_SIZE_BYTES),
.NUM_BANKS (`L2NUM_BANKS),
.WORD_SIZE_BYTES (`L2WORD_SIZE_BYTES),
.NUM_REQUESTS (`L2NUM_REQUESTS),
.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
.FUNC_ID (`L2FUNC_ID),
.REQQ_SIZE (`L2REQQ_SIZE),
.MRVQ_SIZE (`L2MRVQ_SIZE),
.DFPQ_SIZE (`L2DFPQ_SIZE),
.SNRQ_SIZE (`L2SNRQ_SIZE),
.CWBQ_SIZE (`L2CWBQ_SIZE),
.DWBQ_SIZE (`L2DWBQ_SIZE),
.DFQQ_SIZE (`L2DFQQ_SIZE),
.LLVQ_SIZE (`L2LLVQ_SIZE),
.FFSQ_SIZE (`L2FFSQ_SIZE),
.PRFQ_SIZE (`L2PRFQ_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`L2SIMULATED_DRAM_LATENCY_CYCLES)
) gpu_l2cache (
.clk (clk),
.reset (reset),
// Core Req (DRAM Fills/WB) To L2 Request
.core_req_valid (l2c_core_req_valid),
.core_req_read (l2c_core_req_mem_read),
.core_req_write (l2c_core_req_mem_write),
.core_req_addr (l2c_core_req_addr),
.core_req_data ({l2c_core_req_data}),
.core_req_rd (0),
.core_req_wb (l2c_core_req_wb),
.core_req_warp_num (0),
.core_req_pc (0),
// L2 can't accept Core Request
.core_req_ready (l2c_core_req_ready),
// Core can't accept L2 Request
.core_rsp_ready (|l2c_core_rsp_ready),
// Core Writeback
.core_rsp_valid (l2c_wb),
`IGNORE_WARNINGS_BEGIN
.core_rsp_read (),
.core_rsp_write (),
.core_rsp_warp_num (),
.core_rsp_pc (),
`IGNORE_WARNINGS_END
.core_rsp_data ({l2c_wb_data}),
.core_rsp_addr (l2c_wb_addr),
// L2 Cache ///////////////////////////////////////////////////////////
// L2 Cache DRAM Fill response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_addr (dram_rsp_addr),
.dram_rsp_data ({dram_rsp_data_port}),
wire[`L2NUM_REQUESTS-1:0] l2_core_req_valid;
wire[`L2NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l2_core_req_mem_write;
wire[`L2NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l2_core_req_mem_read;
wire[`L2NUM_REQUESTS-1:0][31:0] l2_core_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_req_data;
// L2 Cache can't accept Fill Response
.dram_rsp_ready (dram_rsp_ready),
wire[`L2NUM_REQUESTS-1:0] l2_core_rsp_valid;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] l2_core_rsp_data;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] l2_core_rsp_tag;
wire[`L2NUM_REQUESTS-1:0] l2_core_rsp_ready;
// L2 Cache DRAM Fill Request
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data ({dram_req_data_port}),
.dram_req_ready (dram_req_ready),
wire[`DDRAM_LINE_WIDTH-1:0] l2_dram_req_data;
wire[`DDRAM_LINE_WIDTH-1:0] l2_dram_rsp_data;
// Snoop Request
.snp_req_valid (llc_snp_req_valid),
.snp_req_addr (llc_snp_req_addr),
.snp_req_ready (llc_snp_req_ready),
assign dram_req_data = l2_dram_req_data;
assign l2_dram_rsp_data = dram_rsp_data;
.snp_fwd_valid (snp_fwd_valid),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_ready (& snp_fwd_ready)
);
for (i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
// Core Request
assign l2_core_req_valid [i] = (per_core_D_dram_req_read[(i/2)] | per_core_D_dram_req_write[(i/2)]);
assign l2_core_req_valid [i+1] = (per_core_I_dram_req_read[(i/2)] | per_core_I_dram_req_write[(i/2)]);
assign l2_core_req_mem_write [i] = per_core_D_dram_req_write[(i/2)] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l2_core_req_mem_write [i+1] = `WORD_SEL_NO;
assign l2_core_req_mem_read [i] = per_core_D_dram_req_read[(i/2)] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l2_core_req_mem_read [i+1] = `WORD_SEL_NO;
assign l2_core_req_addr [i] = {per_core_D_dram_req_addr[(i/2)], {`LOG2UP(`DBANK_LINE_SIZE){1'b0}}};
assign l2_core_req_addr [i+1] = {per_core_I_dram_req_addr[(i/2)], {`LOG2UP(`IBANK_LINE_SIZE){1'b0}}};
assign l2_core_req_data [i] = per_core_D_dram_req_data[(i/2)];
assign l2_core_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
assign l2_core_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
assign l2_core_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
assign per_core_D_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i];
assign per_core_I_dram_rsp_valid [(i/2)] = l2_core_rsp_valid[i+1];
assign per_core_D_dram_rsp_data [(i/2)] = l2_core_rsp_data[i];
assign per_core_I_dram_rsp_data [(i/2)] = l2_core_rsp_data[i+1];
assign per_core_D_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i];
assign per_core_I_dram_rsp_tag [(i/2)] = l2_core_rsp_tag[i+1];
assign l2_core_rsp_ready [i] = per_core_D_dram_rsp_ready [(i/2)];
assign l2_core_rsp_ready [i+1] = per_core_I_dram_rsp_ready[(i/2)];
end
VX_cache #(
.CACHE_SIZE (`L2CACHE_SIZE),
.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
.NUM_BANKS (`L2NUM_BANKS),
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQUESTS (`L2NUM_REQUESTS),
.STAGE_1_CYCLES (`L2STAGE_1_CYCLES),
.FUNC_ID (`L2FUNC_ID),
.REQQ_SIZE (`L2REQQ_SIZE),
.MRVQ_SIZE (`L2MRVQ_SIZE),
.DFPQ_SIZE (`L2DFPQ_SIZE),
.SNRQ_SIZE (`L2SNRQ_SIZE),
.CWBQ_SIZE (`L2CWBQ_SIZE),
.DWBQ_SIZE (`L2DWBQ_SIZE),
.DFQQ_SIZE (`L2DFQQ_SIZE),
.LLVQ_SIZE (`L2LLVQ_SIZE),
.FFSQ_SIZE (`L2FFSQ_SIZE),
.PRFQ_SIZE (`L2PRFQ_SIZE),
.PRFQ_STRIDE (`L2PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L2FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
) gpu_l2cache (
.clk (clk),
.reset (reset),
// Core request
.core_req_valid (l2_core_req_valid),
.core_req_read (l2_core_req_mem_read),
.core_req_write (l2_core_req_mem_write),
.core_req_addr (l2_core_req_addr),
.core_req_data (l2_core_req_data),
.core_req_tag (l2_core_req_tag),
.core_req_ready (l2_core_req_ready),
// Core response
.core_rsp_valid (l2_core_rsp_valid),
.core_rsp_data (l2_core_rsp_data),
.core_rsp_tag (l2_core_rsp_tag),
.core_rsp_ready (|l2_core_rsp_ready),
// DRAM request
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data (l2_dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
// L2 Cache DRAM Fill response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_data (l2_dram_rsp_data),
.dram_rsp_ready (dram_rsp_ready),
// Snoop request
.snp_req_valid (llc_snp_req_valid),
.snp_req_addr (llc_snp_req_addr),
.snp_req_ready (llc_snp_req_ready),
// Snoop forwarding
.snp_fwd_valid (snp_fwd_valid),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_ready (& per_core_snp_fwd_ready)
);
end
endmodule

290
hw/rtl/Vortex_Socket.v
View file

@ -6,27 +6,28 @@ module Vortex_Socket (
input wire clk,
input wire reset,
// IO
// IO
output wire io_valid[(`NUM_CORES * `NUM_CLUSTERS)-1:0],
output wire[31:0] io_data [(`NUM_CORES * `NUM_CLUSTERS)-1:0],
// DRAM Req
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`DBANK_LINE_SIZE-1:0] dram_req_data,
output wire[`L3DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire[`L3DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire[`L3DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM Rsp
input wire dram_rsp_valid,
input wire [31:0] dram_rsp_addr,
input wire [`DBANK_LINE_SIZE-1:0] dram_rsp_data,
input wire dram_rsp_valid,
input wire[`L3DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire[`L3DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// LLC Snooping
input wire llc_snp_req_valid,
input wire[31:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
input wire[`L3DRAM_ADDR_WIDTH-1:0] llc_snp_req_addr,
output wire llc_snp_req_ready,
output wire ebreak
);
@ -35,10 +36,10 @@ module Vortex_Socket (
wire[`NUM_CORES-1:0] cluster_io_valid;
wire[`NUM_CORES-1:0][31:0] cluster_io_data;
genvar curr_c;
for (curr_c = 0; curr_c < `NUM_CORES; curr_c=curr_c+1) begin
assign io_valid[curr_c] = cluster_io_valid[curr_c];
assign io_data [curr_c] = cluster_io_data [curr_c];
genvar i;
for (i = 0; i < `NUM_CORES; i=i+1) begin
assign io_valid [i] = cluster_io_valid [i];
assign io_data [i] = cluster_io_data [i];
end
Vortex_Cluster #(
@ -46,6 +47,7 @@ module Vortex_Socket (
) Vortex_Cluster (
.clk (clk),
.reset (reset),
.io_valid (cluster_io_valid),
.io_data (cluster_io_data),
@ -53,11 +55,12 @@ module Vortex_Socket (
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_addr (dram_rsp_addr),
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_data (dram_rsp_data),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready),
.llc_snp_req_valid (llc_snp_req_valid),
@ -69,197 +72,178 @@ module Vortex_Socket (
end else begin
wire snp_fwd_valid;
wire[31:0] snp_fwd_addr;
wire[`NUM_CLUSTERS-1:0] snp_fwd_ready;
wire snp_fwd_valid;
wire[`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_addr;
wire[`NUM_CLUSTERS-1:0] per_cluster_snp_fwd_ready;
wire[`NUM_CLUSTERS-1:0] per_cluster_ebreak;
assign ebreak = (&per_cluster_ebreak);
assign ebreak = (& per_cluster_ebreak);
// // DRAM Dcache Req
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_req_addr;
wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_req_data;
wire[31:0] per_cluster_dram_req_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_write;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_req_read;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag;
wire l3c_core_req_ready;
wire[`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data_up;
wire l3_core_req_ready;
// // DRAM Dcache Rsp
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
wire[`NUM_CLUSTERS-1:0] [31:0] per_cluster_dram_rsp_addr;
wire[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0][31:0] per_cluster_dram_rsp_data;
wire[31:0] per_cluster_dram_rsp_data_up[`NUM_CLUSTERS-1:0][`DBANK_LINE_WORDS-1:0];
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready;
wire[`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag;
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid;
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data;
wire[`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data_up;
genvar curr_c, curr_cc, curr_word;
for (curr_c = 0; curr_c < `NUM_CLUSTERS; curr_c =curr_c+1) begin
for (curr_cc = 0; curr_cc < `NUM_CORES; curr_cc=curr_cc+1) begin
assign io_valid[curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_valid[curr_c][curr_cc];
assign io_data [curr_cc+(curr_c*`NUM_CORES)] = per_cluster_io_data [curr_c][curr_cc];
end
for (curr_word = 0; curr_word < `DBANK_LINE_WORDS; curr_word = curr_word+1) begin
assign per_cluster_dram_req_data [curr_c][curr_word] = per_cluster_dram_req_data_up [curr_c][curr_word];
assign per_cluster_dram_rsp_data_up[curr_c][curr_word] = per_cluster_dram_rsp_data[curr_c][curr_word];
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0] per_cluster_io_valid;
wire[`NUM_CLUSTERS-1:0][`NUM_CORES-1:0][31:0] per_cluster_io_data;
genvar i, j;
for (i = 0; i < `NUM_CLUSTERS; i = i + 1) begin
for (j = 0; j < `NUM_CORES; j = j + 1) begin
assign io_valid[j+(i*`NUM_CORES)] = per_cluster_io_valid[i][j];
assign io_data[j+(i*`NUM_CORES)] = per_cluster_io_data[i][j];
end
assign per_cluster_dram_req_data[i] = per_cluster_dram_req_data_up[i];
assign per_cluster_dram_rsp_data_up[i] = per_cluster_dram_rsp_data[i];
end
genvar curr_cluster;
for (curr_cluster = 0; curr_cluster < `NUM_CLUSTERS; curr_cluster=curr_cluster+1) begin
for (i = 0; i < `NUM_CLUSTERS; i=i+1) begin
Vortex_Cluster #(
.CLUSTER_ID(curr_cluster)
.CLUSTER_ID(i)
) Vortex_Cluster (
.clk (clk),
.reset (reset),
.io_valid (per_cluster_io_valid [curr_cluster]),
.io_data (per_cluster_io_data [curr_cluster]),
.clk (clk),
.reset (reset),
.dram_req_write (per_cluster_dram_req_write [curr_cluster]),
.dram_req_read (per_cluster_dram_req_read [curr_cluster]),
.dram_req_addr (per_cluster_dram_req_addr [curr_cluster]),
.dram_req_data (per_cluster_dram_req_data_up [curr_cluster]),
.dram_req_ready (l3c_core_req_ready),
.io_valid (per_cluster_io_valid [i]),
.io_data (per_cluster_io_data [i]),
.dram_rsp_valid (per_cluster_dram_rsp_valid [curr_cluster]),
.dram_rsp_addr (per_cluster_dram_rsp_addr [curr_cluster]),
.dram_rsp_data (per_cluster_dram_rsp_data_up [curr_cluster]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [curr_cluster]),
.dram_req_write (per_cluster_dram_req_write [i]),
.dram_req_read (per_cluster_dram_req_read [i]),
.dram_req_addr (per_cluster_dram_req_addr [i]),
.dram_req_data (per_cluster_dram_req_data_up [i]),
.dram_req_tag (per_cluster_dram_req_tag [i]),
.dram_req_ready (l3_core_req_ready),
.llc_snp_req_valid (snp_fwd_valid),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_ready (snp_fwd_ready [curr_cluster]),
.dram_rsp_valid (per_cluster_dram_rsp_valid [i]),
.dram_rsp_data (per_cluster_dram_rsp_data_up [i]),
.dram_rsp_tag (per_cluster_dram_rsp_tag [i]),
.dram_rsp_ready (per_cluster_dram_rsp_ready [i]),
.ebreak (per_cluster_ebreak [curr_cluster])
.llc_snp_req_valid (snp_fwd_valid),
.llc_snp_req_addr (snp_fwd_addr),
.llc_snp_req_ready (per_cluster_snp_fwd_ready [i]),
.ebreak (per_cluster_ebreak [i])
);
end
//////////////////// L3 Cache ////////////////////
// L3 Cache ///////////////////////////////////////////////////////////
wire[`L3NUM_REQUESTS-1:0] l3c_core_req_valid;
wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_write;
wire[`L3NUM_REQUESTS-1:0][2:0] l3c_core_req_mem_read;
wire[`L3NUM_REQUESTS-1:0][31:0] l3c_core_req_addr;
wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data;
wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb;
wire[`L3NUM_REQUESTS-1:0] l3_core_req_valid;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_mem_write;
wire[`L3NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] l3_core_req_mem_read;
wire[`L3NUM_REQUESTS-1:0][31:0] l3_core_req_addr;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag;
wire[`L3NUM_REQUESTS-1:0] l3c_core_rsp_ready;
wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_valid;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data;
wire[`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag;
wire[`L3NUM_REQUESTS-1:0] l3_core_rsp_ready;
wire[`L3NUM_REQUESTS-1:0] l3c_wb;
wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr;
wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_wb_data;
wire[`L3DRAM_LINE_WIDTH-1:0] l3_dram_req_data;
wire[`L3DRAM_LINE_WIDTH-1:0] l3_dram_rsp_data;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_req_data_port;
wire[`DBANK_LINE_WORDS-1:0][31:0] dram_rsp_data_port;
assign dram_req_data = l3_dram_req_data;
assign l3_dram_rsp_data = dram_rsp_data;
genvar llb_index;
for (llb_index = 0; llb_index < `DBANK_LINE_WORDS; llb_index=llb_index+1) begin
assign dram_req_data [llb_index] = dram_req_data_port[llb_index];
assign dram_rsp_data_port[llb_index] = dram_rsp_data[llb_index];
end
genvar l3c_curr_cluster;
for (l3c_curr_cluster = 0; l3c_curr_cluster < `L3NUM_REQUESTS; l3c_curr_cluster=l3c_curr_cluster+1) begin
for (i = 0; i < `L3NUM_REQUESTS; i=i+1) begin
// Core Request
assign l3c_core_req_valid [l3c_curr_cluster] = per_cluster_dram_req_valid[l3c_curr_cluster];
assign l3c_core_req_mem_read [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? `LW_MEM_READ : `NO_MEM_READ;
assign l3c_core_req_mem_write [l3c_curr_cluster] = per_cluster_dram_req_write[l3c_curr_cluster] ? `SW_MEM_WRITE : `NO_MEM_WRITE;
assign l3c_core_req_wb [l3c_curr_cluster] = per_cluster_dram_req_read [l3c_curr_cluster] ? 1 : 0;
assign l3c_core_req_addr [l3c_curr_cluster] = per_cluster_dram_req_addr [l3c_curr_cluster];
assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
assign l3_core_req_valid [i] = (per_cluster_dram_req_read[i] | per_cluster_dram_req_write[i]);
assign l3_core_req_mem_read [i] = per_cluster_dram_req_read [i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_mem_write [i] = per_cluster_dram_req_write[i] ? `WORD_SEL_LW : `WORD_SEL_NO;
assign l3_core_req_addr [i] = {per_cluster_dram_req_addr [i], {`LOG2UP(`L2BANK_LINE_SIZE){1'b0}}};
assign l3_core_req_tag [i] = per_cluster_dram_req_tag [i];
assign l3_core_req_data [i] = per_cluster_dram_req_data [i];
// Core can't accept Response
assign l3c_core_rsp_ready [l3c_curr_cluster] = per_cluster_dram_rsp_ready[l3c_curr_cluster];
assign l3_core_rsp_ready [i] = per_cluster_dram_rsp_ready[i];
// Cache Fill Response
assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
assign per_cluster_dram_rsp_data [l3c_curr_cluster] = l3c_wb_data [l3c_curr_cluster];
assign per_cluster_dram_rsp_addr [l3c_curr_cluster] = l3c_wb_addr [l3c_curr_cluster];
assign per_cluster_dram_rsp_valid [i] = l3_core_rsp_valid [i];
assign per_cluster_dram_rsp_data [i] = l3_core_rsp_data [i];
assign per_cluster_dram_rsp_tag [i] = l3_core_rsp_tag [i];
end
VX_cache #(
.CACHE_SIZE_BYTES (`L3CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (`L3BANK_LINE_SIZE_BYTES),
.NUM_BANKS (`L3NUM_BANKS),
.WORD_SIZE_BYTES (`L3WORD_SIZE_BYTES),
.NUM_REQUESTS (`L3NUM_REQUESTS),
.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
.FUNC_ID (`L2FUNC_ID),
.REQQ_SIZE (`L3REQQ_SIZE),
.MRVQ_SIZE (`L3MRVQ_SIZE),
.DFPQ_SIZE (`L3DFPQ_SIZE),
.SNRQ_SIZE (`L3SNRQ_SIZE),
.CWBQ_SIZE (`L3CWBQ_SIZE),
.DWBQ_SIZE (`L3DWBQ_SIZE),
.DFQQ_SIZE (`L3DFQQ_SIZE),
.LLVQ_SIZE (`L3LLVQ_SIZE),
.FFSQ_SIZE (`L3FFSQ_SIZE),
.PRFQ_SIZE (`L3PRFQ_SIZE),
.PRFQ_STRIDE (`L3PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`L3SIMULATED_DRAM_LATENCY_CYCLES)
.CACHE_SIZE (`L3CACHE_SIZE),
.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
.NUM_BANKS (`L3NUM_BANKS),
.WORD_SIZE (`L3WORD_SIZE),
.NUM_REQUESTS (`L3NUM_REQUESTS),
.STAGE_1_CYCLES (`L3STAGE_1_CYCLES),
.FUNC_ID (`L2FUNC_ID),
.REQQ_SIZE (`L3REQQ_SIZE),
.MRVQ_SIZE (`L3MRVQ_SIZE),
.DFPQ_SIZE (`L3DFPQ_SIZE),
.SNRQ_SIZE (`L3SNRQ_SIZE),
.CWBQ_SIZE (`L3CWBQ_SIZE),
.DWBQ_SIZE (`L3DWBQ_SIZE),
.DFQQ_SIZE (`L3DFQQ_SIZE),
.LLVQ_SIZE (`L3LLVQ_SIZE),
.FFSQ_SIZE (`L3FFSQ_SIZE),
.PRFQ_SIZE (`L3PRFQ_SIZE),
.PRFQ_STRIDE (`L3PRFQ_STRIDE),
.FILL_INVALIDAOR_SIZE (`L3FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.DRAM_TAG_WIDTH (`L3DRAM_TAG_WIDTH)
) gpu_l3cache (
.clk (clk),
.reset (reset),
// Core Req (DRAM Fills/WB) To L2 Request
.core_req_valid (l3c_core_req_valid),
.core_req_read (l3c_core_req_mem_read),
.core_req_write (l3c_core_req_mem_write),
.core_req_addr (l3c_core_req_addr),
.core_req_data ({l3c_core_req_data}),
.core_req_rd (0),
.core_req_wb (l3c_core_req_wb),
.core_req_warp_num (0),
.core_req_pc (0),
// Core request
.core_req_valid (l3_core_req_valid),
.core_req_read (l3_core_req_mem_read),
.core_req_write (l3_core_req_mem_write),
.core_req_addr (l3_core_req_addr),
.core_req_data (l3_core_req_data),
.core_req_tag (l3_core_req_tag),
.core_req_ready (l3_core_req_ready),
// L2 can't accept Core Request
.core_req_ready (l3c_core_req_ready),
// Core response
.core_rsp_valid (l3_core_rsp_valid),
.core_rsp_data (l3_core_rsp_data),
.core_rsp_tag (l3_core_rsp_tag),
.core_rsp_ready (|l3_core_rsp_ready),
// Core can't accept L2 Request
.core_rsp_ready (|l3c_core_rsp_ready),
// Core Writeback
.core_rsp_valid (l3c_wb),
`IGNORE_WARNINGS_BEGIN
.core_rsp_read (),
.core_rsp_write (),
.core_rsp_warp_num (),
.core_rsp_pc (),
`IGNORE_WARNINGS_END
.core_rsp_data ({l3c_wb_data}),
.core_rsp_addr (l3c_wb_addr),
// L2 Cache DRAM Fill response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_addr (dram_rsp_addr),
.dram_rsp_data ({dram_rsp_data_port}),
// L2 Cache can't accept Fill Response
.dram_rsp_ready (dram_rsp_ready),
// L2 Cache DRAM Fill Request
// DRAM request
.dram_req_write (dram_req_write),
.dram_req_read (dram_req_read),
.dram_req_addr (dram_req_addr),
.dram_req_data ({dram_req_data_port}),
.dram_req_data (l3_dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
// Snoop Request
// DRAM response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_data (l3_dram_rsp_data),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_ready (dram_rsp_ready),
// Snoop request
.snp_req_valid (llc_snp_req_valid),
.snp_req_addr (llc_snp_req_addr),
.snp_req_ready (llc_snp_req_ready),
// Snoop Forward
// Snoop forwarding
.snp_fwd_valid (snp_fwd_valid),
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_ready (& snp_fwd_ready)
.snp_fwd_ready (& per_cluster_snp_fwd_ready)
);
end

492
hw/rtl/cache/VX_bank.v vendored
View file

@ -2,13 +2,13 @@
`include "VX_define.vh"
module VX_bank #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -39,63 +39,56 @@ module VX_bank #(
parameter FFSQ_SIZE = 8,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
// caceh requests tag size
parameter CORE_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
// Input Core Request
// Core Request
input wire core_req_ready,
input wire [NUM_REQUESTS-1:0] core_req_valids,
input wire [NUM_REQUESTS-1:0][2:0] core_req_read,
input wire [NUM_REQUESTS-1:0][2:0] core_req_write,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data,
input wire [4:0] core_req_rd,
input wire [NUM_REQUESTS-1:0][1:0] core_req_wb,
input wire [31:0] core_req_pc,
input wire [`NW_BITS-1:0] core_req_warp_num,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_full,
// Output Core WB
// Core Response
output wire core_rsp_valid,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] core_rsp_tid,
output wire [4:0] core_rsp_rd,
output wire [1:0] core_rsp_wb,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output wire [`WORD_SIZE_RNG] core_rsp_data,
output wire [31:0] core_rsp_pc,
output wire [31:0] core_rsp_addr,
output wire [`WORD_WIDTH-1:0] core_rsp_data,
output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_pop,
// Dram Fill Requests
output wire dram_fill_req_valid,
output wire[31:0] dram_fill_req_addr,
output wire[`LINE_ADDR_WIDTH-1:0] dram_fill_req_addr,
output wire dram_fill_req_is_snp,
input wire dram_fill_req_full,
// Dram Fill Response
input wire dram_fill_rsp_valid,
input wire [31:0] dram_fill_rsp_addr,
input wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_fill_rsp_data,
input wire dram_fill_rsp_valid,
input wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_fill_rsp_data,
input wire [`LINE_ADDR_WIDTH-1:0] dram_fill_rsp_addr,
output wire dram_fill_rsp_ready,
// Dram WB Requests
output wire dram_wb_req_valid,
output wire [31:0] dram_wb_req_addr,
output wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data,
output wire [`LINE_ADDR_WIDTH-1:0] dram_wb_req_addr,
output wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dram_wb_req_data,
input wire dram_wb_req_pop,
// Snp Request
input wire snp_req_valid,
input wire [31:0] snp_req_addr,
input wire [`LINE_ADDR_WIDTH-1:0] snp_req_addr,
output wire snp_req_full,
output wire snp_fwd_valid,
output wire [31:0] snp_fwd_addr,
output wire [`LINE_ADDR_WIDTH-1:0] snp_fwd_addr,
input wire snp_fwd_pop
);
@ -109,17 +102,16 @@ module VX_bank #(
end
end
wire snrq_pop;
wire snrq_empty;
wire snrq_valid_st0;
wire[31:0] snrq_addr_st0;
wire[`LINE_ADDR_WIDTH-1:0] snrq_addr_st0;
assign snrq_valid_st0 = !snrq_empty;
VX_generic_queue #(
.DATAW(32),
.DATAW($bits(snp_req_addr)),
.SIZE(SNRQ_SIZE)
) snr_queue (
.clk (clk),
@ -132,16 +124,16 @@ module VX_bank #(
.full (snp_req_full)
);
wire dfpq_pop;
wire dfpq_empty;
wire dfpq_full;
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dfpq_filldata_st0;
wire dfpq_pop;
wire dfpq_empty;
wire dfpq_full;
wire [`LINE_ADDR_WIDTH-1:0] dfpq_addr_st0;
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dfpq_filldata_st0;
assign dram_fill_rsp_ready = !dfpq_full;
VX_generic_queue #(
.DATAW(32 + (`BANK_LINE_WORDS*`WORD_SIZE)),
.DATAW($bits(dram_fill_rsp_addr) + $bits(dram_fill_rsp_data)),
.SIZE(DFPQ_SIZE)
) dfp_queue (
.clk (clk),
@ -159,34 +151,33 @@ module VX_bank #(
wire reqq_empty;
wire reqq_req_st0;
wire[`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0;
`IGNORE_WARNINGS_BEGIN
wire [31:0] reqq_req_addr_st0;
wire [`WORD_SIZE_RNG] reqq_req_writeword_st0;
wire [4:0] reqq_req_rd_st0;
wire [1:0] reqq_req_wb_st0;
wire [`NW_BITS-1:0] reqq_req_warp_num_st0;
wire [2:0] reqq_req_mem_read_st0;
wire [2:0] reqq_req_mem_write_st0;
wire [31:0] reqq_req_pc_st0;
`IGNORE_WARNINGS_END
wire [`WORD_WIDTH-1:0] reqq_req_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0;
wire [`WORD_SEL_BITS-1:0] reqq_req_mem_read_st0;
wire [`WORD_SEL_BITS-1:0] reqq_req_mem_write_st0;
assign reqq_push = core_req_ready && (|core_req_valids);
VX_cache_req_queue #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) req_queue (
.clk (clk),
.reset (reset),
@ -195,10 +186,7 @@ module VX_bank #(
.bank_valids (core_req_valids),
.bank_addr (core_req_addr),
.bank_writedata (core_req_data),
.bank_rd (core_req_rd),
.bank_pc (core_req_pc),
.bank_wb (core_req_wb),
.bank_warp_num (core_req_warp_num),
.bank_tag (core_req_tag),
.bank_mem_read (core_req_read),
.bank_mem_write (core_req_write),
@ -208,12 +196,9 @@ module VX_bank #(
.reqq_req_tid_st0 (reqq_req_tid_st0),
.reqq_req_addr_st0 (reqq_req_addr_st0),
.reqq_req_writedata_st0(reqq_req_writeword_st0),
.reqq_req_rd_st0 (reqq_req_rd_st0),
.reqq_req_wb_st0 (reqq_req_wb_st0),
.reqq_req_warp_num_st0 (reqq_req_warp_num_st0),
.reqq_req_tag_st0 (reqq_req_tag_st0),
.reqq_req_mem_read_st0 (reqq_req_mem_read_st0),
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_req_pc_st0 (reqq_req_pc_st0),
.reqq_empty (reqq_empty),
.reqq_full (core_req_full)
);
@ -223,92 +208,33 @@ module VX_bank #(
wire mrvq_stop;
wire mrvq_valid_st0;
wire[`LOG2UP(NUM_REQUESTS)-1:0] mrvq_tid_st0;
wire [31:0] mrvq_addr_st0;
wire [`WORD_SIZE_RNG] mrvq_writeword_st0;
wire [4:0] mrvq_rd_st0;
wire [1:0] mrvq_wb_st0;
wire [31:0] miss_resrv_pc_st0;
wire [`NW_BITS-1:0] mrvq_warp_num_st0;
wire [2:0] mrvq_mem_read_st0;
wire [2:0] mrvq_mem_write_st0;
wire [`LINE_ADDR_WIDTH-1:0] mrvq_addr_st0;
wire [`BASE_ADDR_BITS-1:0] mrvq_wsel_st0;
wire [`WORD_WIDTH-1:0] mrvq_writeword_st0;
wire [CORE_TAG_WIDTH-1:0] mrvq_tag_st0;
wire [`WORD_SEL_BITS-1:0] mrvq_mem_read_st0;
wire [`WORD_SEL_BITS-1:0] mrvq_mem_write_st0;
wire miss_add;
wire[31:0] miss_add_addr;
wire[`WORD_SIZE_RNG] miss_add_data;
wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr;
wire[`BASE_ADDR_BITS-1:0] miss_add_wsel;
wire[`WORD_WIDTH-1:0] miss_add_data;
wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid;
wire[4:0] miss_add_rd;
wire[1:0] miss_add_wb;
wire[`NW_BITS-1:0] miss_add_warp_num;
wire[2:0] miss_add_mem_read;
wire[2:0] miss_add_mem_write;
wire[CORE_TAG_WIDTH-1:0] miss_add_tag;
wire[`WORD_SEL_BITS-1:0] miss_add_mem_read;
wire[`WORD_SEL_BITS-1:0] miss_add_mem_write;
wire[31:0] miss_add_pc;
wire[31:0] addr_st2;
wire[`LINE_ADDR_WIDTH-1:0] addr_st2;
wire is_fill_st2;
VX_cache_miss_resrv #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) mrvq_queue (
.clk (clk),
.reset (reset),
// Enqueue
.miss_add (miss_add), // Need to do all
.miss_add_addr (miss_add_addr),
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_rd (miss_add_rd),
.miss_add_wb (miss_add_wb),
.miss_add_warp_num (miss_add_warp_num),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_add_pc (miss_add_pc),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
// Broadcast
.is_fill_st1 (is_fill_st2),
.fill_addr_st1 (addr_st2),
// Dequeue
.miss_resrv_pop (mrvq_pop),
.miss_resrv_valid_st0 (mrvq_valid_st0),
.miss_resrv_addr_st0 (mrvq_addr_st0),
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_rd_st0 (mrvq_rd_st0),
.miss_resrv_wb_st0 (mrvq_wb_st0),
.miss_resrv_pc_st0 (miss_resrv_pc_st0),
.miss_resrv_warp_num_st0 (mrvq_warp_num_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
wire stall_bank_pipe;
reg is_fill_in_pipe;
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire is_fill_st1 [STAGE_1_CYCLES-1:0];
`DEBUG_BEGIN
wire going_to_write_st1[STAGE_1_CYCLES-1:0];
`DEBUG_END
wire [31:0] addr_st1 [STAGE_1_CYCLES-1:0];
integer i;
always @(*) begin
is_fill_in_pipe = 0;
@ -323,8 +249,6 @@ module VX_bank #(
end
end
// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe;
assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe;
assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !is_fill_in_pipe;
@ -332,123 +256,114 @@ module VX_bank #(
wire qual_is_fill_st0;
wire qual_valid_st0;
wire [31:0] qual_addr_st0;
wire [`WORD_SIZE_RNG] qual_writeword_st0;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] qual_writedata_st0;
wire [`REQ_INST_META_SIZE-1:0] qual_inst_meta_st0;
wire [`LINE_ADDR_WIDTH-1:0] qual_addr_st0;
wire [`WORD_SELECT_ADDR_END:0] qual_wsel_st0;
wire [`WORD_WIDTH-1:0] qual_writeword_st0;
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] qual_writedata_st0;
wire [`REQ_INST_META_WIDTH-1:0] qual_inst_meta_st0;
wire qual_going_to_write_st0;
wire qual_is_snp;
wire [31:0] qual_pc_st0;
wire [`WORD_SIZE_RNG] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_SIZE-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire valid_st1 [STAGE_1_CYCLES-1:0];
wire [`LINE_ADDR_WIDTH-1:0] addr_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_SELECT_ADDR_END:0] wsel_st1 [STAGE_1_CYCLES-1:0];
wire [`WORD_WIDTH-1:0] writeword_st1 [STAGE_1_CYCLES-1:0];
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st1 [STAGE_1_CYCLES-1:0];
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] writedata_st1[STAGE_1_CYCLES-1:0];
wire is_snp_st1 [STAGE_1_CYCLES-1:0];
wire [31:0] pc_st1 [STAGE_1_CYCLES-1:0];
assign qual_is_fill_st0 = dfpq_pop;
// always @(*) begin
// if (qual_is_fill_st0 && (FUNC_ID == 3)) begin
// $display("WHAT THE FUCK FUNC_ID: %x", FUNC_ID);
// end
// end
assign qual_valid_st0 = dfpq_pop || mrvq_pop || reqq_pop || snrq_pop;
assign qual_addr_st0 = dfpq_pop ? dfpq_addr_st0 :
mrvq_pop ? mrvq_addr_st0 :
reqq_pop ? reqq_req_addr_st0 :
reqq_pop ? reqq_req_addr_st0[31:`LINE_SELECT_ADDR_START] :
snrq_pop ? snrq_addr_st0 :
0;
0;
assign qual_wsel_st0 = reqq_pop ? reqq_req_addr_st0[`BASE_ADDR_BITS-1:0] :
mrvq_pop ? mrvq_wsel_st0 :
0;
assign qual_writedata_st0 = dfpq_pop ? dfpq_filldata_st0 : 57;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_rd_st0 , mrvq_wb_st0 , mrvq_warp_num_st0 , mrvq_mem_read_st0 , mrvq_mem_write_st0 , mrvq_tid_st0 } :
reqq_pop ? {reqq_req_rd_st0, reqq_req_wb_st0, reqq_req_warp_num_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
assign qual_inst_meta_st0 = mrvq_pop ? {mrvq_tag_st0 , mrvq_mem_read_st0, mrvq_mem_write_st0, mrvq_tid_st0} :
reqq_pop ? {reqq_req_tag_st0, reqq_req_mem_read_st0, reqq_req_mem_write_st0, reqq_req_tid_st0} :
0;
assign qual_going_to_write_st0 = dfpq_pop ? 1 :
(mrvq_pop && (mrvq_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
(reqq_pop && (reqq_req_mem_write_st0 != `NO_MEM_WRITE)) ? 1 :
(mrvq_pop && (mrvq_mem_write_st0 != `WORD_SEL_NO)) ? 1 :
(reqq_pop && (reqq_req_mem_write_st0 != `WORD_SEL_NO)) ? 1 :
(snrq_pop) ? 1 :
0;
assign qual_pc_st0 = (reqq_pop) ? reqq_req_pc_st0 :
(mrvq_pop) ? miss_resrv_pc_st0 :
(dfpq_pop) ? 32'hdeadbeef :
(snrq_pop) ? 32'hb00b0000 :
32'h0;
assign qual_is_snp = snrq_pop ? 1 : 0;
assign qual_is_snp = snrq_pop ? 1 : 0;
assign qual_writeword_st0 = mrvq_pop ? mrvq_writeword_st0 :
reqq_pop ? reqq_req_writeword_st0 :
0;
VX_generic_register #(
.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)
.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH))
) s0_1_c0 (
.clk (clk),
.reset (reset),
.stall (stall_bank_pipe),
.flush (0),
.in ({qual_is_snp , qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0, qual_pc_st0 }),
.out ({is_snp_st1[0], going_to_write_st1[0] , valid_st1[0] , addr_st1[0] , writeword_st1[0] , inst_meta_st1[0] , is_fill_st1[0] , writedata_st1[0] , pc_st1[0]})
.in ({qual_is_snp, qual_going_to_write_st0, qual_valid_st0, qual_addr_st0, qual_wsel_st0, qual_writeword_st0, qual_inst_meta_st0, qual_is_fill_st0, qual_writedata_st0}),
.out ({is_snp_st1[0], going_to_write_st1[0], valid_st1[0], addr_st1[0], wsel_st1[0], writeword_st1[0], inst_meta_st1[0], is_fill_st1[0], writedata_st1[0]})
);
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES; curr_stage = curr_stage + 1) begin
VX_generic_register #(.N( 1 + 1 + 1 + `WORD_SIZE + 32 + `REQ_INST_META_SIZE + (`BANK_LINE_WORDS*`WORD_SIZE) + 1 + 32)) s0_1_cc (
genvar stage;
for (stage = 1; stage < STAGE_1_CYCLES; stage = stage + 1) begin
VX_generic_register #(
.N(1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `REQ_INST_META_WIDTH + 1 + (`BANK_LINE_WORDS*`WORD_WIDTH))
) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1[curr_stage-1], going_to_write_st1[curr_stage-1], valid_st1[curr_stage-1], addr_st1[curr_stage-1], writeword_st1[curr_stage-1], inst_meta_st1[curr_stage-1], is_fill_st1[curr_stage-1] , writedata_st1[curr_stage-1], pc_st1[curr_stage-1]}),
.out ({is_snp_st1[curr_stage] , going_to_write_st1[curr_stage] , valid_st1[curr_stage] , addr_st1[curr_stage] , writeword_st1[curr_stage] , inst_meta_st1[curr_stage] , is_fill_st1[curr_stage] , writedata_st1[curr_stage] , pc_st1[curr_stage]})
);
end
endgenerate
.in ({is_snp_st1[stage-1], going_to_write_st1[stage-1], valid_st1[stage-1], addr_st1[stage-1], wsel_st1[stage-1], writeword_st1[stage-1], inst_meta_st1[stage-1], is_fill_st1[stage-1], writedata_st1[stage-1]}),
.out ({is_snp_st1[stage], going_to_write_st1[stage], valid_st1[stage], addr_st1[stage], wsel_st1[stage], writeword_st1[stage], inst_meta_st1[stage], is_fill_st1[stage], writedata_st1[stage]})
);
end
wire[`WORD_SIZE_RNG] readword_st1e;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st1e;
wire[`WORD_WIDTH-1:0] readword_st1e;
wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st1e;
wire[`TAG_SELECT_BITS-1:0] readtag_st1e;
wire miss_st1e;
wire dirty_st1e;
wire[31:0] pc_st1e;
`DEBUG_BEGIN
wire [4:0] rd_st1e;
wire [1:0] wb_st1e;
wire [`NW_BITS-1:0] warp_num_st1e;
wire [CORE_TAG_WIDTH-1:0] tag_st1e;
wire [`LOG2UP(NUM_REQUESTS)-1:0] tid_st1e;
`DEBUG_END
wire [2:0] mem_read_st1e;
wire [2:0] mem_write_st1e;
wire [`WORD_SEL_BITS-1:0] mem_read_st1e;
wire [`WORD_SEL_BITS-1:0] mem_write_st1e;
wire fill_saw_dirty_st1e;
wire is_snp_st1e;
assign is_snp_st1e = is_snp_st1[STAGE_1_CYCLES-1];
assign pc_st1e = pc_st1[STAGE_1_CYCLES-1];
assign {rd_st1e, wb_st1e, warp_num_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
assign {tag_st1e, mem_read_st1e, mem_write_st1e, tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1];
VX_tag_data_access #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
VX_tag_data_access #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
) tag_data_access (
.clk (clk),
.reset (reset),
@ -456,12 +371,13 @@ module VX_bank #(
.stall_bank_pipe(stall_bank_pipe),
// Initial Read
.readaddr_st10 (addr_st1[0]),
.readaddr_st10 (addr_st1[0][`LINE_SELECT_BITS-1:0]),
// Actual Read/Write
.valid_req_st1e(valid_st1[STAGE_1_CYCLES-1]),
.writefill_st1e(is_fill_st1[STAGE_1_CYCLES-1]),
.writeaddr_st1e(addr_st1[STAGE_1_CYCLES-1]),
.writewsel_st1e(wsel_st1[STAGE_1_CYCLES-1]),
.writeword_st1e(writeword_st1[STAGE_1_CYCLES-1]),
.writedata_st1e(writedata_st1[STAGE_1_CYCLES-1]),
@ -482,26 +398,26 @@ module VX_bank #(
wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1];
wire valid_st2;
wire[`WORD_SIZE_RNG] writeword_st2;
wire[`WORD_SIZE_RNG] readword_st2;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] readdata_st2;
wire [`BASE_ADDR_BITS-1:0] wsel_st2;
wire [`WORD_WIDTH-1:0] writeword_st2;
wire [`WORD_WIDTH-1:0] readword_st2;
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] readdata_st2;
wire miss_st2;
wire dirty_st2;
wire[`REQ_INST_META_SIZE-1:0] inst_meta_st2;
wire[`TAG_SELECT_BITS-1:0] readtag_st2;
wire [`REQ_INST_META_WIDTH-1:0] inst_meta_st2;
wire [`TAG_SELECT_BITS-1:0] readtag_st2;
wire fill_saw_dirty_st2;
wire is_snp_st2;
wire [31:0] pc_st2;
VX_generic_register #(
.N( 1+1+1+1+32+`WORD_SIZE+`WORD_SIZE+(`BANK_LINE_WORDS * `WORD_SIZE) + `REQ_INST_META_SIZE + `TAG_SELECT_BITS + 32 + 2)
.N(1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `BASE_ADDR_BITS + `WORD_WIDTH + `WORD_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH) + `TAG_SELECT_BITS + 1 + 1 + `REQ_INST_META_WIDTH)
) st_1e_2 (
.clk (clk),
.reset(reset),
.stall(stall_bank_pipe),
.flush(0),
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, pc_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , pc_st2 , inst_meta_st2 })
.in ({is_snp_st1e, fill_saw_dirty_st1e, is_fill_st1[STAGE_1_CYCLES-1] , qual_valid_st1e_2, addr_st1[STAGE_1_CYCLES-1], wsel_st1[STAGE_1_CYCLES-1], writeword_st1[STAGE_1_CYCLES-1], readword_st1e, readdata_st1e, readtag_st1e, miss_st1e, dirty_st1e, inst_meta_st1[STAGE_1_CYCLES-1]}),
.out ({is_snp_st2 , fill_saw_dirty_st2 , is_fill_st2 , valid_st2 , addr_st2 , wsel_st2, writeword_st2 , readword_st2 , readdata_st2 , readtag_st2 , miss_st2 , dirty_st2 , inst_meta_st2 })
);
wire should_flush;
@ -514,73 +430,119 @@ module VX_bank #(
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !(should_flush && dwbq_push) && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_wsel = wsel_st2;
assign miss_add_data = writeword_st2;
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
assign {miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
VX_cache_miss_resrv #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) cache_miss_resrv (
.clk (clk),
.reset (reset),
// Enqueue
.miss_add (miss_add), // Need to do all
.miss_add_addr (miss_add_addr),
.miss_add_wsel (miss_add_wsel),
.miss_add_data (miss_add_data),
.miss_add_tid (miss_add_tid),
.miss_add_tag (miss_add_tag),
.miss_add_mem_read (miss_add_mem_read),
.miss_add_mem_write (miss_add_mem_write),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
// Broadcast
.is_fill_st1 (is_fill_st2),
.fill_addr_st1 (addr_st2),
// Dequeue
.miss_resrv_pop (mrvq_pop),
.miss_resrv_valid_st0 (mrvq_valid_st0),
.miss_resrv_addr_st0 (mrvq_addr_st0),
.miss_resrv_wsel_st0 (mrvq_wsel_st0),
.miss_resrv_data_st0 (mrvq_writeword_st0),
.miss_resrv_tid_st0 (mrvq_tid_st0),
.miss_resrv_tag_st0 (mrvq_tag_st0),
.miss_resrv_mem_read_st0 (mrvq_mem_read_st0),
.miss_resrv_mem_write_st0(mrvq_mem_write_st0)
);
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
wire [1:0] cwbq_wb = miss_add_wb;
wire [`NW_BITS-1:0] cwbq_warp_num = miss_add_warp_num;
wire [31:0] cwbq_pc = pc_st2;
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_mem_write == `WORD_SEL_NO)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire [`WORD_WIDTH-1:0] cwbq_data = readword_st2;
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [CORE_TAG_WIDTH-1:0] cwbq_tag = miss_add_tag;
wire cwbq_empty;
wire cwbq_empty;
assign core_rsp_valid = !cwbq_empty;
VX_generic_queue #(
.DATAW(`LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32),
.DATAW(`LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `WORD_WIDTH),
.SIZE(CWBQ_SIZE)
) cwb_queue(
) cwb_queue (
.clk (clk),
.reset (reset),
.push (cwbq_push),
.data_in ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.data_in ({cwbq_tid, cwbq_tag, cwbq_data}),
.pop (core_rsp_pop),
.data_out({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}),
.data_out({core_rsp_tid, core_rsp_tag, core_rsp_data}),
.empty (cwbq_empty),
.full (cwbq_full)
);
assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `NO_MEM_WRITE) && !is_snp_st2 && !is_fill_st2;
assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `WORD_SEL_NO) && !is_snp_st2 && !is_fill_st2;
// Enqueue to DWB Queue
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire[31:0] dwbq_req_addr;
wire[`LINE_ADDR_WIDTH-1:0] dwbq_req_addr;
wire dwbq_empty;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dwbq_req_data;
wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] dwbq_req_data;
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
assign dwbq_req_data = (should_flush && dwbq_push) ? writeword_st2 : readdata_st2;
assign dwbq_req_addr = (should_flush && dwbq_push) ? (addr_st2) : ({readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK);
assign dwbq_req_addr = (should_flush && dwbq_push) ? (addr_st2) : {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
end else begin
assign dwbq_req_data = readdata_st2;
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_BITS-1:0]};
end
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_full && !is_snp_st2;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
wire [`LINE_ADDR_WIDTH-1:0] fill_invalidator_addr = addr_st2;
VX_fill_invalidator #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
VX_fill_invalidator #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
) fill_invalidator (
.clk (clk),
.reset (reset),
@ -594,12 +556,12 @@ module VX_bank #(
// Enqueue in dram_fill_req
assign dram_fill_req_valid = possible_fill && !invalidate_fill;
assign dram_fill_req_is_snp = is_snp_st2 && valid_st2 && miss_st2;
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;
assign dram_fill_req_addr = addr_st2;
assign dram_wb_req_valid = !dwbq_empty;
VX_generic_queue #(
.DATAW(32 + (`BANK_LINE_WORDS * `WORD_SIZE)),
.DATAW(`LINE_ADDR_WIDTH + (`BANK_LINE_WORDS * `WORD_WIDTH)),
.SIZE(DWBQ_SIZE)
) dwb_queue (
.clk (clk),
@ -621,15 +583,15 @@ module VX_bank #(
assign snp_fwd_valid = !ffsq_empty;
VX_generic_queue #(
.DATAW(32),
.DATAW(`LINE_ADDR_WIDTH),
.SIZE(FFSQ_SIZE)
) ffs_queue (
.clk (clk),
.reset (reset),
.push (snp_fwd_push),
.data_in ({addr_st2}),
.data_in (addr_st2),
.pop (snp_fwd_pop),
.data_out({snp_fwd_addr}),
.data_out(snp_fwd_addr),
.empty (ffsq_empty),
.full (ffsq_full)
);

599
hw/rtl/cache/VX_cache.v vendored
View file

@ -2,13 +2,13 @@
module VX_cache #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 16,
parameter WORD_SIZE = 16,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -46,119 +46,313 @@ module VX_cache #(
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 0,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
// caceh requests tag size
parameter CORE_TAG_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][2:0] core_req_read,
input wire [NUM_REQUESTS-1:0][2:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data,
output wire core_req_ready,
// Core request meta data
input wire [4:0] core_req_rd,
input wire [NUM_REQUESTS-1:0][1:0] core_req_wb,
input wire [`NW_BITS-1:0] core_req_warp_num,
input wire [31:0] core_req_pc,
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_read,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire core_req_ready,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [4:0] core_rsp_read,
output wire [1:0] core_rsp_write,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_addr,
output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
input wire core_rsp_ready,
// Core response meta data
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready,
// DRAM request
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data,
input wire dram_req_ready,
output wire dram_req_read,
output wire dram_req_write,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire [31:0] dram_rsp_addr,
input wire [`IBANK_LINE_WORDS-1:0][31:0] dram_rsp_data,
output wire dram_rsp_ready,
input wire dram_rsp_valid,
input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop Req
input wire snp_req_valid,
input wire [31:0] snp_req_addr,
output wire snp_req_ready,
input wire snp_req_valid,
input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
output wire snp_req_ready,
// Snoop Forward
output wire snp_fwd_valid,
output wire [31:0] snp_fwd_addr,
input wire snp_fwd_ready
output wire snp_fwd_valid,
output wire [`DRAM_ADDR_WIDTH-1:0] snp_fwd_addr,
input wire snp_fwd_ready
);
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
wire [NUM_BANKS-1:0] per_bank_core_rsp_pop;
wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid;
wire [NUM_BANKS-1:0][4:0] per_bank_core_rsp_rd;
wire [NUM_BANKS-1:0][1:0] per_bank_core_rsp_wb;
wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_core_rsp_warp_num;
wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_core_rsp_data;
wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_pc;
wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_addr;
wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid;
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
wire dfqq_full;
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
`DEBUG_BEGIN
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
`DEBUG_END
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr;
wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
wire [NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr;
wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data;
wire [NUM_BANKS-1:0] per_bank_reqq_full;
wire [NUM_BANKS-1:0] per_bank_snp_req_full;
wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid;
wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr;
wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr;
wire [NUM_BANKS-1:0] per_bank_snp_fwd_pop;
assign core_req_ready = ~(|per_bank_reqq_full);
assign snp_req_ready = ~(|per_bank_snp_req_full);
`DEBUG_BEGIN
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
`DEBUG_END
// assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_fill_rsp_ready[0] : per_bank_dram_fill_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]];
assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready);
assign dram_req_tag = dram_req_addr;
assign core_req_ready = ~(|per_bank_reqq_full);
assign snp_req_ready = ~(|per_bank_snp_req_full);
assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready);
VX_cache_dram_req_arb #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
VX_cache_core_req_bank_sel #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
) cache_core_req_bank_sell (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids (per_bank_valids)
);
genvar i;
generate
for (i = 0; i < NUM_BANKS; i = i + 1) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] curr_bank_core_req_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] curr_bank_core_req_write;
wire curr_bank_core_rsp_pop;
wire curr_bank_core_rsp_valid;
wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_core_rsp_tid;
wire [`WORD_WIDTH-1:0] curr_bank_core_rsp_data;
wire [CORE_TAG_WIDTH-1:0] curr_bank_core_rsp_tag;
wire curr_bank_dram_fill_rsp_valid;
wire [`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_fill_rsp_data;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_rsp_addr;
wire curr_bank_dram_fill_rsp_ready;
wire curr_bank_dram_fill_req_full;
wire curr_bank_dram_fill_req_valid;
wire curr_bank_dram_fill_req_is_snp;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_req_pop;
wire curr_bank_dram_wb_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_snp_req_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_req_addr;
wire curr_bank_snp_req_full;
wire curr_bank_snp_fwd_valid;
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_snp_fwd_addr;
wire curr_bank_snp_fwd_pop;
wire curr_bank_reqq_full;
// Core Req
assign curr_bank_core_req_valids = per_bank_valids[i];
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_data = core_req_data;
assign curr_bank_core_req_tag = core_req_tag;
assign curr_bank_core_req_read = core_req_read;
assign curr_bank_core_req_write = core_req_write;
assign per_bank_reqq_full[i] = curr_bank_reqq_full;
// Core WB
assign curr_bank_core_rsp_pop = per_bank_core_rsp_pop[i];
assign per_bank_core_rsp_valid [i] = curr_bank_core_rsp_valid;
assign per_bank_core_rsp_tid [i] = curr_bank_core_rsp_tid;
assign per_bank_core_rsp_tag [i] = curr_bank_core_rsp_tag;
assign per_bank_core_rsp_data [i] = curr_bank_core_rsp_data;
// Dram fill request
assign curr_bank_dram_fill_req_full = dfqq_full;
assign per_bank_dram_fill_req_valid[i] = curr_bank_dram_fill_req_valid;
assign per_bank_dram_fill_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_fill_req_addr, i);
assign per_bank_dram_fill_req_is_snp[i] = curr_bank_dram_fill_req_is_snp;
// Dram fill response
assign curr_bank_dram_fill_rsp_valid = dram_rsp_valid && (`DRAM_ADDR_BANK(dram_rsp_tag) == i);
assign curr_bank_dram_fill_rsp_addr = `DRAM_TO_LINE_ADDR(dram_rsp_tag);
assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
assign per_bank_dram_fill_rsp_ready[i] = curr_bank_dram_fill_rsp_ready;
// Dram writeback request
assign curr_bank_dram_wb_req_pop = per_bank_dram_wb_queue_pop[i];
assign per_bank_dram_wb_req_valid[i] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_dram_wb_req_addr, i);
assign per_bank_dram_wb_req_data[i] = curr_bank_dram_wb_req_data;
// Snoop Request
assign curr_bank_snp_req_valid = snp_req_valid && (`DRAM_ADDR_BANK(snp_req_addr) == i);
assign curr_bank_snp_req_addr = `DRAM_TO_LINE_ADDR(snp_req_addr);
assign per_bank_snp_req_full[i] = curr_bank_snp_req_full;
// Snoop Fwd
assign per_bank_snp_fwd_valid[i] = curr_bank_snp_fwd_valid;
assign per_bank_snp_fwd_addr[i] = `LINE_TO_DRAM_ADDR(curr_bank_snp_fwd_addr, i);
assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[i];
VX_bank #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FFSQ_SIZE (FFSQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) bank (
.clk (clk),
.reset (reset),
// Core request
.core_req_valids (curr_bank_core_req_valids),
.core_req_read (curr_bank_core_req_read),
.core_req_write (curr_bank_core_req_write),
.core_req_addr (curr_bank_core_req_addr),
.core_req_data (curr_bank_core_req_data),
.core_req_tag (curr_bank_core_req_tag),
.core_req_full (curr_bank_reqq_full),
.core_req_ready (core_req_ready),
// Core response
.core_rsp_valid (curr_bank_core_rsp_valid),
.core_rsp_tid (curr_bank_core_rsp_tid),
.core_rsp_data (curr_bank_core_rsp_data),
.core_rsp_tag (curr_bank_core_rsp_tag),
.core_rsp_pop (curr_bank_core_rsp_pop),
// Dram fill request
.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp),
.dram_fill_req_full (curr_bank_dram_fill_req_full),
// Dram fill response
.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
// Dram writeback request
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_wb_req_pop (curr_bank_dram_wb_req_pop),
// Snoop request
.snp_req_valid (curr_bank_snp_req_valid),
.snp_req_addr (curr_bank_snp_req_addr),
.snp_req_full (curr_bank_snp_req_full),
// Snoop forwarding
.snp_fwd_valid (curr_bank_snp_fwd_valid),
.snp_fwd_addr (curr_bank_snp_fwd_addr),
.snp_fwd_pop (curr_bank_snp_fwd_pop)
);
end
endgenerate
VX_cache_core_rsp_merge #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
) cache_core_rsp_merge (
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
.per_bank_core_rsp_data (per_bank_core_rsp_data),
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
.per_bank_core_rsp_pop (per_bank_core_rsp_pop),
.core_rsp_valid (core_rsp_valid),
.core_rsp_data (core_rsp_data),
.core_rsp_tag (core_rsp_tag),
.core_rsp_ready (core_rsp_ready)
);
VX_cache_dram_req_arb #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE)
) cache_dram_req_arb (
.clk (clk),
.reset (reset),
@ -174,73 +368,11 @@ module VX_cache #(
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_ready (dram_req_ready)
);
);
VX_cache_core_req_bank_sel #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
) cache_core_req_bank_sell (
.core_req_valid (core_req_valid),
.core_req_addr (core_req_addr),
.per_bank_valids (per_bank_valids)
);
VX_cache_wb_sel_merge #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) cache_core_rsp_sel_merge (
.per_bank_wb_valid (per_bank_core_rsp_valid),
.per_bank_wb_tid (per_bank_core_rsp_tid),
.per_bank_wb_rd (per_bank_core_rsp_rd),
.per_bank_wb_pc (per_bank_core_rsp_pc),
.per_bank_wb_wb (per_bank_core_rsp_wb),
.per_bank_wb_warp_num(per_bank_core_rsp_warp_num),
.per_bank_wb_data (per_bank_core_rsp_data),
.per_bank_wb_pop (per_bank_core_rsp_pop),
.per_bank_wb_addr (per_bank_core_rsp_addr),
.core_rsp_ready (core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_read (core_rsp_read),
.core_rsp_write (core_rsp_write),
.core_rsp_warp_num (core_rsp_warp_num),
.core_rsp_data (core_rsp_data),
.core_rsp_addr (core_rsp_addr),
.core_rsp_pc (core_rsp_pc)
);
// Snoop Forward Logic
VX_snp_fwd_arb #(
.NUM_BANKS(NUM_BANKS)
.NUM_BANKS(NUM_BANKS),
.BANK_LINE_SIZE(BANK_LINE_SIZE)
) snp_fwd_arb (
.per_bank_snp_fwd_valid (per_bank_snp_fwd_valid),
.per_bank_snp_fwd_addr (per_bank_snp_fwd_addr),
@ -249,184 +381,5 @@ module VX_cache #(
.snp_fwd_addr (snp_fwd_addr),
.snp_fwd_ready (snp_fwd_ready)
);
// Snoop Forward Logic
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_core_req_data;
wire [4:0] curr_bank_core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] curr_bank_core_req_wb;
wire [`NW_BITS-1:0] curr_bank_core_warp_num;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_read;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_write;
wire [31:0] curr_bank_core_req_pc;
wire curr_bank_core_rsp_pop;
wire curr_bank_core_rsp_valid;
wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_core_rsp_tid;
wire [31:0] curr_bank_core_rsp_pc;
wire [4:0] curr_bank_core_rsp_rd;
wire [1:0] curr_bank_core_rsp_wb;
wire [`NW_BITS-1:0] curr_bank_core_rsp_warp_num;
wire [`WORD_SIZE_RNG] curr_bank_core_rsp_data;
wire [31:0] curr_bank_core_rsp_addr;
wire curr_bank_dram_fill_rsp_valid;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_rsp_ready;
wire curr_bank_dram_fill_req_full;
wire curr_bank_dram_fill_req_valid;
wire curr_bank_dram_fill_req_is_snp;
wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_req_pop;
wire curr_bank_dram_wb_req_valid;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
wire curr_bank_snp_req;
wire[31:0] curr_bank_snp_req_addr;
wire curr_bank_reqq_full;
wire curr_bank_snp_fwd_valid;
wire[31:0] curr_bank_snp_fwd_addr;
wire curr_bank_snp_fwd_pop;
wire curr_bank_snp_req_full;
// Core Req
assign curr_bank_core_req_valids = per_bank_valids[curr_bank];
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_data = core_req_data;
assign curr_bank_core_req_rd = core_req_rd;
assign curr_bank_core_req_wb = core_req_wb;
assign curr_bank_core_req_pc = core_req_pc;
assign curr_bank_core_warp_num = core_req_warp_num;
assign curr_bank_core_req_read = core_req_read;
assign curr_bank_core_req_write = core_req_write;
assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
// Core WB
assign curr_bank_core_rsp_pop = per_bank_core_rsp_pop[curr_bank];
assign per_bank_core_rsp_valid [curr_bank] = curr_bank_core_rsp_valid;
assign per_bank_core_rsp_tid [curr_bank] = curr_bank_core_rsp_tid;
assign per_bank_core_rsp_rd [curr_bank] = curr_bank_core_rsp_rd;
assign per_bank_core_rsp_wb [curr_bank] = curr_bank_core_rsp_wb;
assign per_bank_core_rsp_warp_num[curr_bank] = curr_bank_core_rsp_warp_num;
assign per_bank_core_rsp_data [curr_bank] = curr_bank_core_rsp_data;
assign per_bank_core_rsp_pc [curr_bank] = curr_bank_core_rsp_pc;
assign per_bank_core_rsp_addr [curr_bank] = curr_bank_core_rsp_addr;
// Dram fill request
assign curr_bank_dram_fill_req_full = dfqq_full;
assign per_bank_dram_fill_req_valid[curr_bank] = curr_bank_dram_fill_req_valid;
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
assign per_bank_dram_fill_req_is_snp[curr_bank] = curr_bank_dram_fill_req_is_snp;
// Dram fill response
assign curr_bank_dram_fill_rsp_valid = (NUM_BANKS == 1) || (dram_rsp_valid && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
assign curr_bank_dram_fill_rsp_addr = dram_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
assign per_bank_dram_fill_rsp_ready[curr_bank] = curr_bank_dram_fill_rsp_ready;
// Dram writeback request
assign curr_bank_dram_wb_req_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign per_bank_dram_wb_req_valid[curr_bank] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
// Snoop Request
assign curr_bank_snp_req = snp_req_valid && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
assign curr_bank_snp_req_addr = snp_req_addr;
assign per_bank_snp_req_full[curr_bank] = curr_bank_snp_req_full;
// Snoop Fwd
assign per_bank_snp_fwd_valid[curr_bank] = curr_bank_snp_fwd_valid;
assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr;
assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank];
VX_bank #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FFSQ_SIZE (FFSQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) bank (
.clk (clk),
.reset (reset),
// Core request
.core_req_valids (curr_bank_core_req_valids),
.core_req_read (curr_bank_core_req_read),
.core_req_write (curr_bank_core_req_write),
.core_req_addr (curr_bank_core_req_addr),
.core_req_data (curr_bank_core_req_data),
.core_req_rd (curr_bank_core_req_rd),
.core_req_wb (curr_bank_core_req_wb),
.core_req_pc (curr_bank_core_req_pc),
.core_req_warp_num (curr_bank_core_warp_num),
.core_req_full (curr_bank_reqq_full),
.core_req_ready (core_req_ready),
// Core response
.core_rsp_valid (curr_bank_core_rsp_valid),
.core_rsp_tid (curr_bank_core_rsp_tid),
.core_rsp_rd (curr_bank_core_rsp_rd),
.core_rsp_wb (curr_bank_core_rsp_wb),
.core_rsp_warp_num (curr_bank_core_rsp_warp_num),
.core_rsp_data (curr_bank_core_rsp_data),
.core_rsp_pc (curr_bank_core_rsp_pc),
.core_rsp_addr (curr_bank_core_rsp_addr),
.core_rsp_pop (curr_bank_core_rsp_pop),
// Dram fill request
.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp),
.dram_fill_req_full (curr_bank_dram_fill_req_full),
// Dram fill response
.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
// Dram writeback request
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_wb_req_pop (curr_bank_dram_wb_req_pop),
// Snoop request
.snp_req_valid (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr),
.snp_req_full (curr_bank_snp_req_full),
// Snoop forwarding
.snp_fwd_valid (curr_bank_snp_fwd_valid),
.snp_fwd_addr (curr_bank_snp_fwd_addr),
.snp_fwd_pop (curr_bank_snp_fwd_pop)
);
end
endgenerate
endmodule

101
hw/rtl/cache/VX_cache_config.vh vendored
View file

@ -3,71 +3,80 @@
`include "VX_define.vh"
// data tid rd wb warp_num read write
`define MRVQ_METADATA_SIZE (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3)
`define WORD_SEL_NO 3'h7
`define WORD_SEL_LB 3'h0
`define WORD_SEL_LH 3'h1
`define WORD_SEL_LW 3'h2
`define WORD_SEL_HB 3'h4
`define WORD_SEL_HH 3'h5
`define WORD_SEL_BITS 3
// rd wb warp_num read write + reqs
`define REQ_INST_META_SIZE (5 + 2 + (`NW_BITS) + 3 + 3 + `LOG2UP(NUM_REQUESTS))
// data tid tag read write base addr
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `LOG2UP(NUM_REQUESTS) + CORE_TAG_WIDTH + `WORD_SEL_BITS + `WORD_SEL_BITS + `BASE_ADDR_BITS)
`define WORD_SIZE (8 * WORD_SIZE_BYTES)
`define WORD_SIZE_RNG (`WORD_SIZE)-1:0
// tag read write reqs
`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + `WORD_SEL_BITS + `WORD_SEL_BITS + `LOG2UP(NUM_REQUESTS))
// 128
`define BANK_SIZE_BYTES (CACHE_SIZE_BYTES / NUM_BANKS)
`define WORD_WIDTH (8 * WORD_SIZE)
`define BYTE_WIDTH (`WORD_WIDTH / 4)
// 8
`define BANK_LINE_COUNT (`BANK_SIZE_BYTES / BANK_LINE_SIZE_BYTES)
// 4
`define BANK_LINE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
`define BANK_LINE_WIDTH (8 * BANK_LINE_SIZE)
// Offset is fixed
`define OFFSET_ADDR_BITS 2
`define OFFSET_SIZE_END 1
`define BANK_SIZE (CACHE_SIZE / NUM_BANKS)
`define BANK_LINE_COUNT (`BANK_SIZE / BANK_LINE_SIZE)
`define BANK_LINE_WORDS (BANK_LINE_SIZE / WORD_SIZE)
// Offset select
`define OFFSET_ADDR_BITS `CLOG2(WORD_SIZE)
`define OFFSET_ADDR_START 0
`define OFFSET_ADDR_END 1
`define OFFSET_ADDR_END (`OFFSET_ADDR_START+`OFFSET_ADDR_BITS-1)
`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
// 2
`define WORD_SELECT_BITS (`LOG2UP(`BANK_LINE_WORDS))
// 2
`define WORD_SELECT_SIZE_END (`WORD_SELECT_BITS)
// 2
// Word select
`define WORD_SELECT_BITS `CLOG2(`BANK_LINE_WORDS)
`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
// 3
`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END)
// 3:2
`define WORD_SELECT_ADDR_END (`WORD_SELECT_ADDR_START+`WORD_SELECT_BITS-1)
`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
// 3
`define BANK_SELECT_BITS (`LOG2UP(NUM_BANKS))
// 3
`define BANK_SELECT_SIZE_END (`BANK_SELECT_BITS)
// 4
// Bank select
`define BANK_SELECT_BITS `CLOG2(NUM_BANKS)
`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
// 6
`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1)
// 6:4
`define BANK_SELECT_ADDR_END (`BANK_SELECT_ADDR_START+`BANK_SELECT_BITS-1)
`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
// 3
`define LINE_SELECT_BITS (`LOG2UP(`BANK_LINE_COUNT))
// 7
// Line select
`define LINE_SELECT_BITS `CLOG2(`BANK_LINE_COUNT)
`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
// 9
`define LINE_SELECT_ADDR_END (`LINE_SELECT_BITS+`LINE_SELECT_ADDR_START-1)
// 9:7
`define LINE_SELECT_ADDR_END (`LINE_SELECT_ADDR_START+`LINE_SELECT_BITS-1)
`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
// 10
// Tag select
`define TAG_SELECT_BITS (31-`LINE_SELECT_ADDR_END)
`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
// 31:10
`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START
// 22
`define TAG_SELECT_BITS (32-`TAG_SELECT_ADDR_START)
`define TAG_SELECT_ADDR_END 31
`define TAG_SELECT_ADDR_RNG `TAG_SELECT_ADDR_END:`TAG_SELECT_ADDR_START
`define TAG_LINE_SELECT_BITS (`TAG_SELECT_BITS+`LINE_SELECT_BITS)
`define DRAM_ADDR_WIDTH (32-`CLOG2(BANK_LINE_SIZE))
`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1))
`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
`define TAG_LINE_ADDR_RNG `LINE_ADDR_WIDTH-1:`LINE_SELECT_BITS
`define BASE_ADDR_BITS (`WORD_SELECT_BITS+`OFFSET_ADDR_BITS)
///////////////////////////////////////////////////////////////////////////////
// Core request tag width pc, wb, rd, warp_num
`define CORE_REQ_TAG_WIDTH (32 + 2 + 5 + `NW_BITS)
// Core request tag info rd + warp_num
`define CORE_REQ_TAG_WARP(x) x[(5 + `NW_BITS)-1:0]
// DRAM response tag bank info
`define DRAM_ADDR_BANK(x) x[`BANK_SELECT_BITS-1:0]
`define DRAM_TO_LINE_ADDR(x) x[`DRAM_ADDR_WIDTH-1:`BANK_SELECT_BITS]
`define LINE_TO_DRAM_ADDR(x, i) {x, (`BANK_SELECT_BITS)'(i)};
`endif

11
hw/rtl/cache/VX_cache_core_req_bank_sel.v vendored
View file

@ -3,13 +3,13 @@
module VX_cache_core_req_bank_sel #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -38,10 +38,7 @@ module VX_cache_core_req_bank_sel #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,

115
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored Normal file
View file

@ -0,0 +1,115 @@
`include "VX_cache_config.vh"
module VX_cache_core_rsp_merge #(
// Size of cache in bytes
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// caceh requests tag size
parameter CORE_TAG_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) (
// Per Bank WB
input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid,
input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid,
input wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data,
input wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag,
output wire [NUM_BANKS-1:0] per_bank_core_rsp_pop,
// Core Writeback
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
output reg [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire core_rsp_ready
);
reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual;
assign per_bank_core_rsp_pop = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}};
wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank (
.valids(per_bank_core_rsp_valid),
.index (main_bank_index),
.found (found_bank)
);
integer i;
generate
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_tag = 0;
for (i = 0; i < NUM_BANKS; i = i + 1) begin
if ((FUNC_ID == `L2FUNC_ID)
|| (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_tag[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i];
per_bank_core_rsp_pop_unqual[i] = 1;
end else begin
per_bank_core_rsp_pop_unqual[i] = 0;
end
end else begin
if (found_bank
&& per_bank_core_rsp_valid[i]
&& !core_rsp_valid[per_bank_core_rsp_tid[i]]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
|| (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))
&& (`CORE_REQ_TAG_WARP(per_bank_core_rsp_tag[i]) == `CORE_REQ_TAG_WARP(per_bank_core_rsp_tag[main_bank_index]))) begin
core_rsp_valid[per_bank_core_rsp_tid[i]] = 1;
core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i];
core_rsp_tag[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_tag[i];
per_bank_core_rsp_pop_unqual[i] = 1;
end else begin
per_bank_core_rsp_pop_unqual[i] = 0;
end
end
end
end
endgenerate
endmodule

69
hw/rtl/cache/VX_cache_dfq_queue.v vendored
View file

@ -2,13 +2,13 @@
module VX_cache_dfq_queue #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -35,45 +35,42 @@ module VX_cache_dfq_queue #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire clk,
input wire reset,
input wire dfqq_push,
input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
input wire[NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
input wire clk,
input wire reset,
input wire dfqq_push,
input wire[NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
input wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr,
input wire dfqq_pop,
output wire dfqq_req,
output wire[31:0] dfqq_req_addr,
output wire dfqq_empty,
output wire dfqq_full
input wire dfqq_pop,
output wire dfqq_req,
output wire[`DRAM_ADDR_WIDTH-1:0] dfqq_req_addr,
output wire dfqq_empty,
output wire dfqq_full
);
wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req;
wire[NUM_BANKS-1:0][31:0] out_per_bank_dram_fill_req_addr;
wire[NUM_BANKS-1:0] out_per_bank_dram_fill_req_valid;
wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] out_per_bank_dram_fill_req_addr;
reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req;
reg [NUM_BANKS-1:0][31:0] use_per_bank_dram_fill_req_addr;
reg [NUM_BANKS-1:0] use_per_bank_dram_fill_req_valid;
reg [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] use_per_bank_dram_fill_req_addr;
wire[NUM_BANKS-1:0] qual_bank_dram_fill_req;
wire[NUM_BANKS-1:0][31:0] qual_bank_dram_fill_req_addr;
wire[NUM_BANKS-1:0] use_per_bqual_bank_dram_fill_req_valid;
wire[NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] qual_bank_dram_fill_req_addr;
wire[NUM_BANKS-1:0] updated_bank_dram_fill_req;
wire[NUM_BANKS-1:0] updated_bank_dram_fill_req_valid;
wire o_empty;
wire use_empty = !(|use_per_bank_dram_fill_req);
wire out_empty = !(|out_per_bank_dram_fill_req) || o_empty;
wire use_empty = !(|use_per_bank_dram_fill_req_valid);
wire out_empty = !(|out_per_bank_dram_fill_req_valid) || o_empty;
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty;
wire pop_qual = dfqq_pop && use_empty && !out_empty;
VX_generic_queue #(
.DATAW(NUM_BANKS * (1+32)),
.DATAW(NUM_BANKS * (1+`DRAM_ADDR_WIDTH)),
.SIZE(DFQQ_SIZE)
) dfqq_queue (
.clk (clk),
@ -81,38 +78,38 @@ module VX_cache_dfq_queue #(
.push (push_qual),
.data_in ({per_bank_dram_fill_req_valid, per_bank_dram_fill_req_addr}),
.pop (pop_qual),
.data_out({out_per_bank_dram_fill_req, out_per_bank_dram_fill_req_addr}),
.data_out({out_per_bank_dram_fill_req_valid, out_per_bank_dram_fill_req_addr}),
.empty (o_empty),
.full (dfqq_full)
);
assign qual_bank_dram_fill_req = use_empty ? (out_per_bank_dram_fill_req & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req & {NUM_BANKS{!use_empty}});
assign use_per_bqual_bank_dram_fill_req_valid = use_empty ? (out_per_bank_dram_fill_req_valid & {NUM_BANKS{!o_empty}}) : (use_per_bank_dram_fill_req_valid & {NUM_BANKS{!use_empty}});
assign qual_bank_dram_fill_req_addr = use_empty ? out_per_bank_dram_fill_req_addr : use_per_bank_dram_fill_req_addr;
wire[`LOG2UP(NUM_BANKS)-1:0] qual_request_index;
wire qual_has_request;
wire qual_has_request;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank (
.valids(qual_bank_dram_fill_req),
.valids(use_per_bqual_bank_dram_fill_req_valid),
.index (qual_request_index),
.found (qual_has_request)
);
assign dfqq_empty = !qual_has_request;
assign dfqq_req = qual_bank_dram_fill_req [qual_request_index];
assign dfqq_req = use_per_bqual_bank_dram_fill_req_valid [qual_request_index];
assign dfqq_req_addr = qual_bank_dram_fill_req_addr[qual_request_index];
assign updated_bank_dram_fill_req = qual_bank_dram_fill_req & (~(1 << qual_request_index));
assign updated_bank_dram_fill_req_valid = use_per_bqual_bank_dram_fill_req_valid & (~(1 << qual_request_index));
always @(posedge clk) begin
if (reset) begin
use_per_bank_dram_fill_req <= 0;
use_per_bank_dram_fill_req_valid <= 0;
use_per_bank_dram_fill_req_addr <= 0;
end else begin
if (dfqq_pop && qual_has_request) begin
use_per_bank_dram_fill_req <= updated_bank_dram_fill_req;
use_per_bank_dram_fill_req_valid <= updated_bank_dram_fill_req_valid;
use_per_bank_dram_fill_req_addr <= qual_bank_dram_fill_req_addr;
end
end

53
hw/rtl/cache/VX_cache_dram_req_arb.v vendored
View file

@ -2,13 +2,13 @@
module VX_cache_dram_req_arb #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -40,37 +40,34 @@ module VX_cache_dram_req_arb #(
// Prefetcher
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter PRFQ_STRIDE = 2
) (
input wire clk,
input wire reset,
// Fill Request
output wire dfqq_full,
// Fill Request
input wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid,
input wire [NUM_BANKS-1:0][31:0] per_bank_dram_fill_req_addr,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_fill_req_addr,
output wire dfqq_full,
// DFQ Request
output wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop,
// Writeback Request
input wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid,
input wire [NUM_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
input wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] per_bank_dram_wb_req_data,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_dram_wb_req_addr,
input wire [NUM_BANKS-1:0][`BANK_LINE_WORDS-1:0][`WORD_WIDTH-1:0] per_bank_dram_wb_req_data,
output wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop,
// real Dram request
// Merged Request
output wire dram_req_read,
output wire dram_req_write,
output wire [31:0] dram_req_addr,
output wire [`IBANK_LINE_WORDS-1:0][31:0] dram_req_data,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
input wire dram_req_ready
);
wire pref_pop;
wire pref_valid;
wire[31:0] pref_addr;
wire[`DRAM_ADDR_WIDTH-1:0] pref_addr;
wire dwb_valid;
wire dfqq_req;
@ -78,10 +75,10 @@ module VX_cache_dram_req_arb #(
assign pref_pop = !dwb_valid && !dfqq_req && dram_req_ready && pref_valid;
VX_prefetcher #(
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.BANK_LINE_SIZE_BYTES(BANK_LINE_SIZE_BYTES),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES)
.PRFQ_SIZE (PRFQ_SIZE),
.PRFQ_STRIDE (PRFQ_STRIDE),
.BANK_LINE_SIZE(BANK_LINE_SIZE),
.WORD_SIZE (WORD_SIZE)
) prfqq (
.clk (clk),
.reset (reset),
@ -94,7 +91,7 @@ module VX_cache_dram_req_arb #(
.pref_addr (pref_addr)
);
wire[31:0] dfqq_req_addr;
wire[`DRAM_ADDR_WIDTH-1:0] dfqq_req_addr;
`DEBUG_BEGIN
wire dfqq_empty;
@ -130,10 +127,10 @@ module VX_cache_dram_req_arb #(
assign per_bank_dram_wb_queue_pop = dram_req_ready ? (use_wb_valid & ((1 << dwb_bank))) : 0;
wire dram_req = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req;
assign dram_req_write = dwb_valid && dram_req;
assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr)) & `BASE_ADDR_MASK;
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
wire dram_req_valid = dwb_valid || dfqq_req || pref_pop;
assign dram_req_read = ((dfqq_req && !dwb_valid) || pref_pop) && dram_req_valid;
assign dram_req_write = dwb_valid && dram_req_valid;
assign dram_req_addr = dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : (dfqq_req ? dfqq_req_addr : pref_addr);
assign {dram_req_data} = dwb_valid ? {per_bank_dram_wb_req_data[dwb_bank] }: 0;
endmodule

73
hw/rtl/cache/VX_cache_miss_resrv.v vendored
View file

@ -3,13 +3,13 @@
module VX_cache_miss_resrv #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -36,25 +36,23 @@ module VX_cache_miss_resrv #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
// caceh requests tag size
parameter CORE_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
// Miss enqueue
input wire miss_add,
input wire[31:0] miss_add_addr,
input wire[`WORD_SIZE_RNG] miss_add_data,
input wire[`LINE_ADDR_WIDTH-1:0] miss_add_addr,
input wire[`BASE_ADDR_BITS-1:0] miss_add_wsel,
input wire[`WORD_WIDTH-1:0] miss_add_data,
input wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_add_tid,
input wire[4:0] miss_add_rd,
input wire[1:0] miss_add_wb,
input wire[`NW_BITS-1:0] miss_add_warp_num,
input wire[2:0] miss_add_mem_read,
input wire[2:0] miss_add_mem_write,
input wire[31:0] miss_add_pc,
input wire[CORE_TAG_WIDTH-1:0] miss_add_tag,
input wire[`WORD_SEL_BITS-1:0] miss_add_mem_read,
input wire[`WORD_SEL_BITS-1:0] miss_add_mem_write,
output wire miss_resrv_full,
output wire miss_resrv_stop,
@ -63,37 +61,31 @@ module VX_cache_miss_resrv #(
`IGNORE_WARNINGS_BEGIN
// TODO: should fix this
input wire[31:0] fill_addr_st1,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr_st1,
`IGNORE_WARNINGS_END
// Miss dequeue
input wire miss_resrv_pop,
output wire miss_resrv_valid_st0,
output wire[31:0] miss_resrv_addr_st0,
output wire[`WORD_SIZE_RNG] miss_resrv_data_st0,
output wire[`LINE_ADDR_WIDTH-1:0] miss_resrv_addr_st0,
output wire[`BASE_ADDR_BITS-1:0] miss_resrv_wsel_st0,
output wire[`WORD_WIDTH-1:0] miss_resrv_data_st0,
output wire[`LOG2UP(NUM_REQUESTS)-1:0] miss_resrv_tid_st0,
output wire[4:0] miss_resrv_rd_st0,
output wire[1:0] miss_resrv_wb_st0,
output wire[`NW_BITS-1:0] miss_resrv_warp_num_st0,
output wire[2:0] miss_resrv_mem_read_st0,
output wire[31:0] miss_resrv_pc_st0,
output wire[2:0] miss_resrv_mem_write_st0
output wire[CORE_TAG_WIDTH-1:0] miss_resrv_tag_st0,
output wire[`WORD_SEL_BITS-1:0] miss_resrv_mem_read_st0,
output wire[`WORD_SEL_BITS-1:0] miss_resrv_mem_write_st0
);
// Size of metadata = 32 + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1 + 1)
reg [`MRVQ_METADATA_SIZE-1:0] metadata_table[MRVQ_SIZE-1:0];
reg [MRVQ_SIZE-1:0][31:0] addr_table;
reg [MRVQ_SIZE-1:0][31:0] pc_table;
reg [`MRVQ_METADATA_WIDTH-1:0] metadata_table[MRVQ_SIZE-1:0];
reg [MRVQ_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table;
reg [MRVQ_SIZE-1:0] valid_table;
reg [MRVQ_SIZE-1:0] ready_table;
reg [`LOG2UP(MRVQ_SIZE)-1:0] head_ptr;
reg [`LOG2UP(MRVQ_SIZE)-1:0] tail_ptr;
reg [31:0] size;
reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size;
// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE );
assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size > (MRVQ_SIZE-5));
assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE));
assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5));
wire enqueue_possible = !miss_resrv_full;
wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;
@ -102,8 +94,7 @@ module VX_cache_miss_resrv #(
genvar curr_e;
generate
for (curr_e = 0; curr_e < MRVQ_SIZE; curr_e=curr_e+1) begin
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e]
&& addr_table[curr_e][31:`LINE_SELECT_ADDR_START] == fill_addr_st1[31:`LINE_SELECT_ADDR_START];
assign make_ready[curr_e] = is_fill_st1 && valid_table[curr_e] && (addr_table[curr_e] == fill_addr_st1);
end
endgenerate
@ -111,24 +102,19 @@ module VX_cache_miss_resrv #(
wire [`LOG2UP(MRVQ_SIZE)-1:0] dequeue_index = head_ptr;
assign miss_resrv_valid_st0 = (MRVQ_SIZE != 2) && dequeue_possible;
assign miss_resrv_pc_st0 = pc_table[dequeue_index];
assign miss_resrv_addr_st0 = addr_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_tag_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0, miss_resrv_wsel_st0} = metadata_table[dequeue_index];
wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
wire mrvq_pop = miss_resrv_pop && dequeue_possible;
wire update_ready = (|make_ready);
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < MRVQ_SIZE; i=i+1) begin
metadata_table[i] <= 0;
end
valid_table <= 0;
ready_table <= 0;
addr_table <= 0;
pc_table <= 0;
size <= 0;
head_ptr <= 0;
tail_ptr <= 0;
@ -136,9 +122,8 @@ module VX_cache_miss_resrv #(
if (mrvq_push) begin
valid_table[enqueue_index] <= 1;
ready_table[enqueue_index] <= 0;
pc_table[enqueue_index] <= miss_add_pc;
addr_table[enqueue_index] <= miss_add_addr;
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write};
metadata_table[enqueue_index] <= {miss_add_data, miss_add_tid, miss_add_tag, miss_add_mem_read, miss_add_mem_write, miss_add_wsel};
tail_ptr <= tail_ptr + 1;
end
@ -151,7 +136,6 @@ module VX_cache_miss_resrv #(
ready_table[dequeue_index] <= 0;
addr_table[dequeue_index] <= 0;
metadata_table[dequeue_index] <= 0;
pc_table[dequeue_index] <= 0;
head_ptr <= head_ptr + 1;
end
@ -159,7 +143,6 @@ module VX_cache_miss_resrv #(
if (mrvq_push) begin
size <= size + 1;
end
if (mrvq_pop) begin
size <= size - 1;
end

133
hw/rtl/cache/VX_cache_req_queue.v vendored
View file

@ -2,13 +2,13 @@
module VX_cache_req_queue #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -34,77 +34,62 @@ module VX_cache_req_queue #(
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
// caceh requests tag size
parameter CORE_TAG_WIDTH = 1
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Enqueue Data
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUM_REQUESTS-1:0][1:0] bank_wb,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write,
input wire [31:0] bank_pc,
input wire reqq_push,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] bank_mem_write,
input wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] bank_writedata,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] bank_tag,
// Dequeue Data
input wire reqq_pop,
output wire reqq_req_st0,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] reqq_req_tid_st0,
output wire [`WORD_SEL_BITS-1:0] reqq_req_mem_read_st0,
output wire [`WORD_SEL_BITS-1:0] reqq_req_mem_write_st0,
output wire [`WORD_WIDTH-1:0] reqq_req_writedata_st0,
output wire [31:0] reqq_req_addr_st0,
output wire [`WORD_SIZE_RNG] reqq_req_writedata_st0,
output wire [4:0] reqq_req_rd_st0,
output wire [1:0] reqq_req_wb_st0,
output wire [`NW_BITS-1:0] reqq_req_warp_num_st0,
output wire [2:0] reqq_req_mem_read_st0,
output wire [2:0] reqq_req_mem_write_st0,
output wire [31:0] reqq_req_pc_st0,
output wire [CORE_TAG_WIDTH-1:0] reqq_req_tag_st0,
// State Data
output wire reqq_empty,
output wire reqq_full
);
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] out_per_writedata;
wire [4:0] out_per_rd;
wire [NUM_REQUESTS-1:0][1:0] out_per_wb;
wire [`NW_BITS-1:0] out_per_warp_num;
wire [NUM_REQUESTS-1:0][2:0] out_per_mem_read;
wire [NUM_REQUESTS-1:0][2:0] out_per_mem_write;
wire [31:0] out_per_pc;
wire [NUM_REQUESTS-1:0] out_per_valids;
wire [NUM_REQUESTS-1:0][31:0] out_per_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] out_per_writedata;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] out_per_mem_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] out_per_mem_write;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] out_per_tag;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] use_per_writedata;
reg [4:0] use_per_rd;
reg [NUM_REQUESTS-1:0][1:0] use_per_wb;
reg [31:0] use_per_pc;
reg [`NW_BITS-1:0] use_per_warp_num;
reg [NUM_REQUESTS-1:0][2:0] use_per_mem_read;
reg [NUM_REQUESTS-1:0][2:0] use_per_mem_write;
reg [NUM_REQUESTS-1:0] use_per_valids;
reg [NUM_REQUESTS-1:0][31:0] use_per_addr;
reg [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] use_per_writedata;
reg [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] use_per_mem_read;
reg [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] use_per_mem_write;
reg [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] use_per_tag;
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0][31:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] qual_writedata;
wire [4:0] qual_rd;
wire [NUM_REQUESTS-1:0][1:0] qual_wb;
wire [`NW_BITS-1:0] qual_warp_num;
wire [NUM_REQUESTS-1:0][2:0] qual_mem_read;
wire [NUM_REQUESTS-1:0][2:0] qual_mem_write;
wire [31:0] qual_pc;
wire [NUM_REQUESTS-1:0] qual_valids;
wire [NUM_REQUESTS-1:0][31:0] qual_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] qual_writedata;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] qual_mem_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] qual_mem_write;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] qual_tag;
`DEBUG_BEGIN
reg [NUM_REQUESTS-1:0] updated_valids;
reg [NUM_REQUESTS-1:0] updated_valids;
`DEBUG_END
wire o_empty;
@ -116,15 +101,15 @@ module VX_cache_req_queue #(
wire pop_qual = !out_empty && use_empty;
VX_generic_queue #(
.DATAW( (NUM_REQUESTS * (1+32+`WORD_SIZE)) + 5 + (NUM_REQUESTS*2) + (`NW_BITS-1+1) + (NUM_REQUESTS * (3 + 3)) + 32 ),
.DATAW($bits(bank_valids) + $bits(bank_addr) + $bits(bank_writedata) + $bits(bank_tag) + $bits(bank_mem_read) + $bits(bank_mem_write)),
.SIZE(REQQ_SIZE)
) reqq_queue (
.clk (clk),
.reset (reset),
.push (push_qual),
.data_in ({bank_valids , bank_addr , bank_writedata , bank_rd , bank_wb , bank_warp_num , bank_mem_read , bank_mem_write , bank_pc}),
.data_in ({bank_valids, bank_addr, bank_writedata, bank_tag, bank_mem_read, bank_mem_write}),
.pop (pop_qual),
.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_rd, out_per_wb, out_per_warp_num, out_per_mem_read, out_per_mem_write, out_per_pc}),
.data_out ({out_per_valids, out_per_addr, out_per_writedata, out_per_tag, out_per_mem_read, out_per_mem_write}),
.empty (o_empty),
.full (reqq_full)
);
@ -134,15 +119,12 @@ module VX_cache_req_queue #(
assign qual_valids = use_per_valids;
assign qual_addr = use_per_addr;
assign qual_writedata = use_per_writedata;
assign qual_rd = use_per_rd;
assign qual_wb = use_per_wb;
assign qual_warp_num = use_per_warp_num;
assign qual_tag = use_per_tag;
assign qual_mem_read = use_per_mem_read;
assign qual_mem_write = use_per_mem_write;
assign qual_pc = use_per_pc;
wire[`LOG2UP(NUM_REQUESTS)-1:0] qual_request_index;
wire qual_has_request;
wire[`LOG2UP(NUM_REQUESTS)-1:0]qual_request_index;
wire qual_has_request;
VX_generic_priority_encoder #(
.N(NUM_REQUESTS)
@ -157,12 +139,9 @@ module VX_cache_req_queue #(
assign reqq_req_tid_st0 = qual_request_index;
assign reqq_req_addr_st0 = qual_addr[qual_request_index];
assign reqq_req_writedata_st0 = qual_writedata[qual_request_index];
assign reqq_req_rd_st0 = qual_rd;
assign reqq_req_wb_st0 = qual_wb[qual_request_index];
assign reqq_req_warp_num_st0 = qual_warp_num;
assign reqq_req_tag_st0 = qual_tag[qual_request_index];
assign reqq_req_mem_read_st0 = qual_mem_read [qual_request_index];
assign reqq_req_mem_write_st0 = qual_mem_write[qual_request_index];
assign reqq_req_pc_st0 = qual_pc;
always @(*) begin
updated_valids = qual_valids;
@ -173,32 +152,18 @@ module VX_cache_req_queue #(
always @(posedge clk) begin
if (reset) begin
use_per_valids <= 0;
use_per_addr <= 0;
use_per_writedata <= 0;
use_per_rd <= 0;
use_per_wb <= 0;
use_per_warp_num <= 0;
use_per_mem_read <= 0;
use_per_mem_write <= 0;
use_per_pc <= 0;
use_per_valids <= 0;
end else begin
if (pop_qual) begin
use_per_valids <= real_out_per_valids;
use_per_addr <= out_per_addr;
use_per_writedata <= out_per_writedata;
use_per_rd <= out_per_rd;
use_per_wb <= out_per_wb;
use_per_warp_num <= out_per_warp_num;
use_per_tag <= out_per_tag;
use_per_mem_read <= out_per_mem_read;
use_per_mem_write <= out_per_mem_write;
use_per_pc <= out_per_pc;
end else if (reqq_pop) begin
use_per_valids[qual_request_index] <= 0;
end
// else if (reqq_pop) begin
// use_per_valids[qual_request_index] <= updated_valids;
// end
end
end

137
hw/rtl/cache/VX_cache_wb_sel_merge.v vendored
View file

@ -1,137 +0,0 @@
`include "VX_cache_config.vh"
module VX_cache_wb_sel_merge #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
parameter STAGE_1_CYCLES = 2,
// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
parameter FUNC_ID = 0,
// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
// Core Request Queue Size
parameter REQQ_SIZE = 8,
// Miss Reserv Queue Knob
parameter MRVQ_SIZE = 8,
// Dram Fill Rsp Queue Size
parameter DFPQ_SIZE = 2,
// Snoop Req Queue
parameter SNRQ_SIZE = 8,
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
// Core Writeback Queue Size
parameter CWBQ_SIZE = 8,
// Dram Writeback Queue Size
parameter DWBQ_SIZE = 4,
// Dram Fill Req Queue Size
parameter DFQQ_SIZE = 8,
// Lower Level Cache Hit Queue Size
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
) (
// Per Bank WB
input wire [NUM_BANKS-1:0] per_bank_wb_valid,
input wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid,
input wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd,
input wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb,
input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num,
input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc,
input wire [NUM_BANKS-1:0][31:0] per_bank_wb_addr,
output wire [NUM_BANKS-1:0] per_bank_wb_pop,
// Core Writeback
input wire core_rsp_ready,
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
output wire [4:0] core_rsp_read,
output wire [1:0] core_rsp_write,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_addr
);
reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual;
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUM_BANKS{core_rsp_ready}};
// wire[NUM_BANKS-1:0] bank_wants_wb;
// genvar curr_bank;
// generate
// for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin
// assign bank_wants_wb[curr_bank] = (|per_bank_wb_valid[curr_bank]);
// end
// endgenerate
wire [`LOG2UP(NUM_BANKS)-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(
.N(NUM_BANKS)
) sel_bank (
.valids(per_bank_wb_valid),
.index (main_bank_index),
.found (found_bank)
);
assign core_rsp_read = per_bank_wb_rd[main_bank_index];
assign core_rsp_write = per_bank_wb_wb[main_bank_index];
assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index];
integer i;
generate
always @(*) begin
core_rsp_valid = 0;
core_rsp_data = 0;
core_rsp_pc = 0;
core_rsp_addr = 0;
for (i = 0; i < NUM_BANKS; i = i + 1) begin
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank
&& !core_rsp_valid[per_bank_wb_tid[i]]
&& per_bank_wb_valid[i]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
|| (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index]))) begin
core_rsp_valid[per_bank_wb_tid[i]] = 1;
core_rsp_data[per_bank_wb_tid[i]] = per_bank_wb_data[i];
core_rsp_pc[per_bank_wb_tid[i]] = per_bank_wb_pc[i];
core_rsp_addr[per_bank_wb_tid[i]] = per_bank_wb_addr[i];
per_bank_wb_pop_unqual[i] = 1;
end else begin
per_bank_wb_pop_unqual[i] = 0;
end
end else begin
if (((main_bank_index == `LOG2UP(NUM_BANKS)'(i))
|| (per_bank_wb_tid[i] != per_bank_wb_tid[main_bank_index]))
&& found_bank
&& !core_rsp_valid[per_bank_wb_tid[i]]
&& (per_bank_wb_valid[i])
&& (per_bank_wb_rd[i] == per_bank_wb_rd[main_bank_index])
&& (per_bank_wb_warp_num[i] == per_bank_wb_warp_num[main_bank_index])) begin
core_rsp_valid[per_bank_wb_tid[i]] = 1;
core_rsp_data[per_bank_wb_tid[i]] = per_bank_wb_data[i];
core_rsp_pc[per_bank_wb_tid[i]] = per_bank_wb_pc[i];
core_rsp_addr[per_bank_wb_tid[i]] = per_bank_wb_addr[i];
per_bank_wb_pop_unqual[i] = 1;
end else begin
per_bank_wb_pop_unqual[i] = 0;
end
end
end
end
endgenerate
endmodule

81
hw/rtl/cache/VX_fill_invalidator.v vendored
View file

@ -2,13 +2,13 @@
module VX_fill_invalidator #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -35,20 +35,17 @@ module VX_fill_invalidator #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire possible_fill,
input wire success_fill,
input wire possible_fill,
input wire success_fill,
input wire[31:0] fill_addr,
input wire[`LINE_ADDR_WIDTH-1:0] fill_addr,
output reg invalidate_fill
output reg invalidate_fill
);
if (FILL_INVALIDAOR_SIZE == 0) begin
@ -57,15 +54,16 @@ module VX_fill_invalidator #(
end else begin
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg [FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
reg [FILL_INVALIDAOR_SIZE-1:0] fills_active;
reg [FILL_INVALIDAOR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] fills_address;
reg [FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
always @(*) begin
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi][31:`LINE_SELECT_ADDR_START] == fill_addr[31:`LINE_SELECT_ADDR_START]);
matched_fill[fi] = fills_active[fi] && (fills_address[fi] == fill_addr);
end
end
@ -89,7 +87,6 @@ module VX_fill_invalidator #(
fills_active <= 0;
fills_address <= 0;
end else begin
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
@ -99,56 +96,6 @@ module VX_fill_invalidator #(
end
end
// reg success_found;
// reg[(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] success_index;
// integer curr_fill;
// always @(*) begin
// invalidate_fill = 0;
// success_found = 0;
// success_index = 0;
// for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
// if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
// if (possible_fill && fills_active[curr_fill]) begin
// invalidate_fill = 1;
// end
// if (success_fill) begin
// success_found = 1;
// success_index = curr_fill;
// end
// end
// end
// end
// wire [(`LOG2UP(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)
// );
// always @(posedge clk) begin
// if (reset) begin
// fills_active <= 0;
// fills_address <= 0;
// end else begin
// if (possible_fill && !invalidate_fill) begin
// fills_active[enqueue_index] <= 1;
// fills_address[enqueue_index] <= fill_addr;
// end
// if (success_found) begin
// fills_active[success_index] <= 0;
// end
// end
// end
end
endmodule

40
hw/rtl/cache/VX_prefetcher.v vendored
View file

@ -1,29 +1,29 @@
`include "VX_cache_config.vh"
module VX_prefetcher #(
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
parameter PRFQ_SIZE = 64,
parameter PRFQ_STRIDE = 2,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4
parameter WORD_SIZE = 4
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
input wire dram_req,
input wire[31:0] dram_req_addr,
input wire dram_req,
input wire[`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
input wire pref_pop,
output wire pref_valid,
output wire[31:0] pref_addr
input wire pref_pop,
output wire pref_valid,
output wire[`DRAM_ADDR_WIDTH-1:0] pref_addr
);
reg[`LOG2UP(PRFQ_STRIDE):0] use_valid;
reg[31:0] use_addr;
reg[`LOG2UP(PRFQ_STRIDE):0] use_valid;
reg[`DRAM_ADDR_WIDTH-1:0] use_addr;
wire current_valid;
wire[31:0] current_addr;
wire current_valid;
wire[`DRAM_ADDR_WIDTH-1:0] current_addr;
wire current_full;
wire current_empty;
@ -33,14 +33,14 @@ module VX_prefetcher #(
wire update_use = ((use_valid == 0) || ((use_valid-1) == 0)) && current_valid;
VX_generic_queue #(
.DATAW(32),
.DATAW(`DRAM_ADDR_WIDTH),
.SIZE(PRFQ_SIZE)
) pfq_queue (
.clk (clk),
.reset (reset),
.push (dram_req && !current_full && !pref_pop),
.data_in (dram_req_addr & `BASE_ADDR_MASK),
.data_in (dram_req_addr),
.pop (update_use),
.data_out(current_addr),
@ -49,7 +49,7 @@ module VX_prefetcher #(
.full (current_full)
);
assign pref_valid = use_valid != 0;
assign pref_valid = 0; // TODO use_valid != 0;
assign pref_addr = use_addr;
always @(posedge clk) begin
@ -59,10 +59,10 @@ module VX_prefetcher #(
end else begin
if (update_use) begin
use_valid <= PRFQ_STRIDE;
use_addr <= current_addr + BANK_LINE_SIZE_BYTES;
use_addr <= current_addr + BANK_LINE_SIZE;
end else if (pref_valid && pref_pop) begin
use_valid <= use_valid - 1;
use_addr <= use_addr + BANK_LINE_SIZE_BYTES;
use_addr <= use_addr + BANK_LINE_SIZE;
end
end
end

7
hw/rtl/cache/VX_snp_fwd_arb.v vendored
View file

@ -1,14 +1,15 @@
`include "VX_cache_config.vh"
module VX_snp_fwd_arb #(
parameter NUM_BANKS = 8
parameter NUM_BANKS = 1,
parameter BANK_LINE_SIZE = 1
) (
input wire [NUM_BANKS-1:0] per_bank_snp_fwd_valid,
input wire [NUM_BANKS-1:0][31:0] per_bank_snp_fwd_addr,
input wire [NUM_BANKS-1:0][`DRAM_ADDR_WIDTH-1:0] per_bank_snp_fwd_addr,
output reg [NUM_BANKS-1:0] per_bank_snp_fwd_pop,
output wire snp_fwd_valid,
output wire [31:0] snp_fwd_addr,
output wire [`DRAM_ADDR_WIDTH-1:0] snp_fwd_addr,
input wire snp_fwd_ready
);

342
hw/rtl/cache/VX_tag_data_access.v vendored
View file

@ -2,13 +2,13 @@
module VX_tag_data_access #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -37,85 +37,86 @@ module VX_tag_data_access #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire clk,
input wire reset,
input wire stall,
input wire is_snp_st1e,
input wire stall_bank_pipe,
// Initial Reading
`IGNORE_WARNINGS_BEGIN
// TODO: should fix this
input wire[31:0] readaddr_st10,
input wire[31:0] writeaddr_st1e,
`IGNORE_WARNINGS_END
input wire valid_req_st1e,
input wire writefill_st1e,
input wire[`WORD_SIZE_RNG] writeword_st1e,
input wire[`DBANK_LINE_WORDS-1:0][31:0] writedata_st1e,
input wire[2:0] mem_write_st1e,
input wire[2:0] mem_read_st1e,
input wire clk,
input wire reset,
input wire stall,
input wire is_snp_st1e,
input wire stall_bank_pipe,
output wire[`WORD_SIZE_RNG] readword_st1e,
output wire[`DBANK_LINE_WORDS-1:0][31:0] readdata_st1e,
output wire[`TAG_SELECT_BITS-1:0] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
output wire fill_saw_dirty_st1e
input wire[`LINE_SELECT_BITS-1:0] readaddr_st10,
input wire[`LINE_ADDR_WIDTH-1:0] writeaddr_st1e,
input wire valid_req_st1e,
input wire writefill_st1e,
input wire[`WORD_WIDTH-1:0] writeword_st1e,
input wire[`BANK_LINE_WIDTH-1:0] writedata_st1e,
`IGNORE_WARNINGS_BEGIN
input wire[`WORD_SELECT_ADDR_END:0] writewsel_st1e,
input wire[`WORD_SEL_BITS-1:0] mem_write_st1e,
input wire[`WORD_SEL_BITS-1:0] mem_read_st1e,
`IGNORE_WARNINGS_END
output wire[`WORD_WIDTH-1:0] readword_st1e,
output wire[`BANK_LINE_WIDTH-1:0] readdata_st1e,
output wire[`TAG_SELECT_BITS-1:0] readtag_st1e,
output wire miss_st1e,
output wire dirty_st1e,
output wire fill_saw_dirty_st1e
);
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`DBANK_LINE_WORDS-1:0][31:0] read_data_st1c [STAGE_1_CYCLES-1:0];
reg read_valid_st1c[STAGE_1_CYCLES-1:0];
reg read_dirty_st1c[STAGE_1_CYCLES-1:0];
reg[`TAG_SELECT_BITS-1:0] read_tag_st1c [STAGE_1_CYCLES-1:0];
reg[`BANK_LINE_WIDTH-1:0] read_data_st1c [STAGE_1_CYCLES-1:0];
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1;
wire[`DBANK_LINE_WORDS-1:0][31:0] qual_read_data_st1;
wire qual_read_valid_st1;
wire qual_read_dirty_st1;
wire[`TAG_SELECT_BITS-1:0] qual_read_tag_st1;
wire[`BANK_LINE_WIDTH-1:0] qual_read_data_st1;
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e;
wire[`DBANK_LINE_WORDS-1:0][31:0] use_read_data_st1e;
wire[`DBANK_LINE_WORDS-1:0][3:0] use_write_enable;
wire[`DBANK_LINE_WORDS-1:0][31:0] use_write_data;
wire sw, sb, sh;
wire real_writefill = writefill_st1e && ((valid_req_st1e && !use_read_valid_st1e) || (valid_req_st1e && use_read_valid_st1e && (writeaddr_st1e[`TAG_SELECT_ADDR_RNG] != use_read_tag_st1e)));
wire use_read_valid_st1e;
wire use_read_dirty_st1e;
wire[`TAG_SELECT_BITS-1:0] use_read_tag_st1e;
wire[`BANK_LINE_WIDTH-1:0] use_read_data_st1e;
wire[`BANK_LINE_WORDS-1:0][3:0] use_write_enable;
wire[`BANK_LINE_WIDTH-1:0] use_write_data;
wire fill_sent;
wire invalidate_line;
VX_tag_data_structure #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
wire real_writefill = writefill_st1e
&& ((valid_req_st1e
&& !use_read_valid_st1e)
|| (valid_req_st1e
&& use_read_valid_st1e
&& (writeaddr_st1e[`TAG_LINE_ADDR_RNG] != use_read_tag_st1e)));
VX_tag_data_structure #(
.CACHE_SIZE (CACHE_SIZE),
.BANK_LINE_SIZE (BANK_LINE_SIZE),
.NUM_BANKS (NUM_BANKS),
.WORD_SIZE (WORD_SIZE),
.NUM_REQUESTS (NUM_REQUESTS),
.STAGE_1_CYCLES (STAGE_1_CYCLES),
.FUNC_ID (FUNC_ID),
.REQQ_SIZE (REQQ_SIZE),
.MRVQ_SIZE (MRVQ_SIZE),
.DFPQ_SIZE (DFPQ_SIZE),
.SNRQ_SIZE (SNRQ_SIZE),
.CWBQ_SIZE (CWBQ_SIZE),
.DWBQ_SIZE (DWBQ_SIZE),
.DFQQ_SIZE (DFQQ_SIZE),
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE)
) tag_data_structure (
.clk (clk),
.reset (reset),
.stall_bank_pipe(stall_bank_pipe),
.read_addr (readaddr_st10[`LINE_SELECT_ADDR_RNG]),
.read_addr (readaddr_st10),
.read_valid (qual_read_valid_st1),
.read_dirty (qual_read_dirty_st1),
.read_tag (qual_read_tag_st1),
@ -124,15 +125,14 @@ module VX_tag_data_access #(
.invalidate (invalidate_line),
.write_enable(use_write_enable),
.write_fill (real_writefill),
.write_addr (writeaddr_st1e[`LINE_SELECT_ADDR_RNG]),
.tag_index (writeaddr_st1e[`TAG_SELECT_ADDR_RNG]),
.write_addr (writeaddr_st1e[`LINE_SELECT_BITS-1:0]),
.tag_index (writeaddr_st1e[`TAG_LINE_ADDR_RNG]),
.write_data (use_write_data),
.fill_sent (fill_sent)
);
// VX_generic_register #(.N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32) )) s0_1_c0 (
VX_generic_register #(
.N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32) ),
.N(1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH),
.PassThru(1)
) s0_1_c0 (
.clk (clk),
@ -140,134 +140,120 @@ module VX_tag_data_access #(
.stall(stall),
.flush(0),
.in ({qual_read_valid_st1, qual_read_dirty_st1, qual_read_tag_st1, qual_read_data_st1}),
.out ({read_valid_st1c[0] , read_dirty_st1c[0] , read_tag_st1c[0] , read_data_st1c[0]})
.out ({read_valid_st1c[0], read_dirty_st1c[0], read_tag_st1c[0], read_data_st1c[0]})
);
genvar curr_stage;
generate
for (curr_stage = 1; curr_stage < STAGE_1_CYCLES-1; curr_stage = curr_stage + 1) begin
VX_generic_register #(
.N( 1 + 1 + `TAG_SELECT_BITS + (`DBANK_LINE_WORDS*32))
) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({read_valid_st1c[curr_stage-1] , read_dirty_st1c[curr_stage-1] , read_tag_st1c[curr_stage-1] , read_data_st1c[curr_stage-1]}),
.out ({read_valid_st1c[curr_stage] , read_dirty_st1c[curr_stage] , read_tag_st1c[curr_stage] , read_data_st1c[curr_stage] })
);
end
endgenerate
genvar i;
for (i = 1; i < STAGE_1_CYCLES-1; i = i + 1) begin
VX_generic_register #(
.N( 1 + 1 + `TAG_SELECT_BITS + `BANK_LINE_WIDTH)
) s0_1_cc (
.clk (clk),
.reset(reset),
.stall(stall),
.flush(0),
.in ({read_valid_st1c[i-1], read_dirty_st1c[i-1], read_tag_st1c[i-1], read_data_st1c[i-1]}),
.out ({read_valid_st1c[i], read_dirty_st1c[i], read_tag_st1c[i], read_data_st1c[i]})
);
end
assign use_read_valid_st1e = read_valid_st1c[STAGE_1_CYCLES-1] || (FUNC_ID == `SFUNC_ID); // If shared memory, always valid
assign use_read_dirty_st1e = read_dirty_st1c[STAGE_1_CYCLES-1] && (FUNC_ID != `SFUNC_ID); // Dirty only applies in Dcache
assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_SELECT_ADDR_RNG] : read_tag_st1c [STAGE_1_CYCLES-1]; // Tag is always the same in SM
assign use_read_tag_st1e = (FUNC_ID == `SFUNC_ID) ? writeaddr_st1e[`TAG_LINE_ADDR_RNG] : read_tag_st1c[STAGE_1_CYCLES-1]; // Tag is always the same in SM
genvar curr_w;
for (curr_w = 0; curr_w < `DBANK_LINE_WORDS; curr_w = curr_w+1) assign use_read_data_st1e[curr_w][31:0] = read_data_st1c[STAGE_1_CYCLES-1][curr_w][31:0];
// assign use_read_data_st1e = read_data_st1c [STAGE_1_CYCLES-1];
for (i = 0; i < `BANK_LINE_WORDS; i = i + 1) begin
assign use_read_data_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] = read_data_st1c[STAGE_1_CYCLES-1][i * `WORD_WIDTH +: `WORD_WIDTH];
end
/////////////////////// LOAD LOGIC ///////////////////
wire[`OFFSET_SIZE_RNG] byte_select = writeaddr_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_BITS-1:0] block_offset = writeaddr_st1e[`WORD_SELECT_ADDR_RNG];
`IGNORE_WARNINGS_BEGIN
wire lw = valid_req_st1e && (mem_read_st1e == `LW_MEM_READ);
wire lb = valid_req_st1e && (mem_read_st1e == `LB_MEM_READ);
wire lh = valid_req_st1e && (mem_read_st1e == `LH_MEM_READ);
wire lhu = valid_req_st1e && (mem_read_st1e == `LHU_MEM_READ);
wire lbu = valid_req_st1e && (mem_read_st1e == `LBU_MEM_READ);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
`IGNORE_WARNINGS_END
`DEBUG_BEGIN
wire[31:0] w0 = read_data_st1c[STAGE_1_CYCLES-1][0][31:0];
wire[31:0] w1 = read_data_st1c[STAGE_1_CYCLES-1][1][31:0];
wire[31:0] w2 = read_data_st1c[STAGE_1_CYCLES-1][2][31:0];
wire[31:0] w3 = read_data_st1c[STAGE_1_CYCLES-1][3][31:0];
`DEBUG_END
/////////////////////// STORE LOGIC ///////////////////
assign sw = valid_req_st1e && (mem_write_st1e == `SW_MEM_WRITE);
assign sb = valid_req_st1e && (mem_write_st1e == `SB_MEM_WRITE);
assign sh = valid_req_st1e && (mem_write_st1e == `SH_MEM_WRITE);
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
wire force_write = real_writefill;
wire[`DBANK_LINE_WORDS-1:0][3:0] we;
wire[`DBANK_LINE_WORDS-1:0][31:0] data_write;
wire [`BANK_LINE_WORDS-1:0][3:0] we;
wire [`BANK_LINE_WIDTH-1:0] data_write;
genvar g;
generate
for (g = 0; g < `DBANK_LINE_WORDS; g = g + 1) begin : write_enables
wire normal_write = (block_offset == g[`WORD_SELECT_BITS-1:0]) && should_write && !real_writefill;
if (WORD_SIZE == 4) begin
assign we[g] = (force_write) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `L2FUNC_ID)) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
wire[`OFFSET_ADDR_BITS-1:0] byte_select = writewsel_st1e[`OFFSET_ADDR_RNG];
wire[`WORD_SELECT_BITS-1:0] block_offset = writewsel_st1e[`WORD_SELECT_ADDR_RNG];
if (FUNC_ID != `L2FUNC_ID) begin
wire[31:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e[31:0];
wire[31:0] sw_data = writeword_st1e[31:0];
wire[31:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0];
wire[31:0] use_write_dat = sb ? sb_data : sh ? sh_data : sw_data;
assign data_write[g] = force_write ? writedata_st1e[g] : use_write_dat;
end
wire lb = valid_req_st1e && (mem_read_st1e == `WORD_SEL_LB);
wire lh = valid_req_st1e && (mem_read_st1e == `WORD_SEL_LH);
wire lbu = valid_req_st1e && (mem_read_st1e == `WORD_SEL_HB);
wire lhu = valid_req_st1e && (mem_read_st1e == `WORD_SEL_HH);
wire lw = valid_req_st1e && (mem_read_st1e == `WORD_SEL_LW);
wire b0 = (byte_select == 0);
wire b1 = (byte_select == 1);
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire sb = valid_req_st1e && (mem_write_st1e == `WORD_SEL_LB);
wire sh = valid_req_st1e && (mem_write_st1e == `WORD_SEL_LH);
wire sw = valid_req_st1e && (mem_write_st1e == `WORD_SEL_LW);
wire [3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire [3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
wire[`WORD_WIDTH-1:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset * 32 +: 32];
wire[`WORD_WIDTH-1:0] data_unQual = (b0 || lw) ? (data_unmod) :
b1 ? (data_unmod >> 8) :
b2 ? (data_unmod >> 16) :
(data_unmod >> 24);
wire[`WORD_WIDTH-1:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lbu_data = (data_unQual & 32'hFF);
wire[`WORD_WIDTH-1:0] lhu_data = (data_unQual & 32'hFFFF);
wire[`WORD_WIDTH-1:0] lw_data = (data_unQual);
wire[`WORD_WIDTH-1:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readword_st1e = data_Qual;
for (i = 0; i < `BANK_LINE_WORDS; i = i + 1) begin
wire normal_write = (block_offset == i[`WORD_SELECT_BITS-1:0]) && should_write && !real_writefill;
assign we[i] = (force_write) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :
4'b0000;
wire [`WORD_WIDTH-1:0] sb_data = b1 ? {{16{1'b0}}, writeword_st1e[7:0], { 8{1'b0}}} :
b2 ? {{ 8{1'b0}}, writeword_st1e[7:0], {16{1'b0}}} :
b3 ? {{ 0{1'b0}}, writeword_st1e[7:0], {24{1'b0}}} :
writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sw_data = writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] sh_data = b2 ? {writeword_st1e[15:0], {16{1'b0}}} : writeword_st1e[31:0];
wire [`WORD_WIDTH-1:0] use_write_dat = sb ? sb_data : sh ? sh_data : sw_data;
assign data_write[i * `WORD_WIDTH +: `WORD_WIDTH] = force_write ? writedata_st1e[i * `WORD_WIDTH +: `WORD_WIDTH] : use_write_dat;
end
if (FUNC_ID == `L2FUNC_ID) begin
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end
endgenerate
end else begin
wire should_write = ((mem_write_st1e != `WORD_SEL_NO)) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
for (i = 0; i < `BANK_LINE_WORDS; i = i + 1) begin
assign we[i] = (force_write || (should_write && !real_writefill)) ? 4'b1111 : 4'b0000;
end
assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1];
assign data_write = force_write ? writedata_st1e : writeword_st1e;
end
assign use_write_enable = (writefill_st1e && !real_writefill) ? 0 : we;
assign use_write_data = data_write;
if (FUNC_ID == `L2FUNC_ID) begin
assign readword_st1e = read_data_st1c[STAGE_1_CYCLES-1];
end else begin
wire[31:0] data_unmod = read_data_st1c[STAGE_1_CYCLES-1][block_offset][31:0];
wire[31:0] data_unQual = (b0 || lw) ? (data_unmod) :
b1 ? (data_unmod >> 8) :
b2 ? (data_unmod >> 16) :
(data_unmod >> 24);
wire[31:0] lb_data = (data_unQual[7] ) ? (data_unQual | 32'hFFFFFF00) : (data_unQual & 32'hFF);
wire[31:0] lh_data = (data_unQual[15]) ? (data_unQual | 32'hFFFF0000) : (data_unQual & 32'hFFFF);
wire[31:0] lbu_data = (data_unQual & 32'hFF);
wire[31:0] lhu_data = (data_unQual & 32'hFFFF);
wire[31:0] lw_data = (data_unQual);
wire[31:0] data_Qual = lb ? lb_data :
lh ? lh_data :
lhu ? lhu_data :
lbu ? lbu_data :
lw_data;
assign readword_st1e = data_Qual;
end
wire[`TAG_SELECT_ADDR_RNG] writeaddr_tag = writeaddr_st1e[`TAG_SELECT_ADDR_RNG];
wire[`TAG_SELECT_BITS-1:0] writeaddr_tag = writeaddr_st1e[`TAG_LINE_ADDR_RNG];
wire tags_mismatch = writeaddr_tag != use_read_tag_st1e;
wire tags_match = writeaddr_tag == use_read_tag_st1e;
wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch;
wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match && use_read_dirty_st1e;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch;
assign miss_st1e = snoop_hit || req_invalid || req_miss;
assign dirty_st1e = valid_req_st1e && use_read_valid_st1e && use_read_dirty_st1e;

47
hw/rtl/cache/VX_tag_data_structure.v vendored
View file

@ -2,13 +2,13 @@
module VX_tag_data_structure #(
// Size of cache in bytes
parameter CACHE_SIZE_BYTES = 1024,
parameter CACHE_SIZE = 1024,
// Size of line inside a bank in bytes
parameter BANK_LINE_SIZE_BYTES = 16,
parameter BANK_LINE_SIZE = 16,
// Number of banks {1, 2, 4, 8,...}
parameter NUM_BANKS = 8,
// Size of a word in bytes
parameter WORD_SIZE_BYTES = 4,
parameter WORD_SIZE = 4,
// Number of Word requests per cycle {1, 2, 4, 8, ...}
parameter NUM_REQUESTS = 2,
// Number of cycles to complete stage 1 (read from memory)
@ -37,10 +37,7 @@ module VX_tag_data_structure #(
parameter LLVQ_SIZE = 16,
// Fill Invalidator Size {Fill invalidator must be active}
parameter FILL_INVALIDAOR_SIZE = 16,
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
parameter FILL_INVALIDAOR_SIZE = 16
) (
input wire clk,
input wire reset,
@ -50,21 +47,21 @@ module VX_tag_data_structure #(
output wire read_valid,
output wire read_dirty,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire[`DBANK_LINE_WORDS-1:0][31:0] read_data,
output wire[`BANK_LINE_WIDTH-1:0] read_data,
input wire invalidate,
input wire[`DBANK_LINE_WORDS-1:0][3:0] write_enable,
input wire[`BANK_LINE_WORDS-1:0][3:0] write_enable,
input wire write_fill,
input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire[`TAG_SELECT_BITS-1:0] tag_index,
input wire[`DBANK_LINE_WORDS-1:0][31:0] write_data,
input wire[`BANK_LINE_WIDTH-1:0] write_data,
input wire fill_sent
);
reg [`DBANK_LINE_WORDS-1:0][3:0][7:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0];
reg [`BANK_LINE_WORDS-1:0][3:0][`BYTE_WIDTH-1:0] data [`BANK_LINE_COUNT-1:0];
reg [`TAG_SELECT_BITS-1:0] tag [`BANK_LINE_COUNT-1:0];
reg valid [`BANK_LINE_COUNT-1:0];
reg dirty [`BANK_LINE_COUNT-1:0];
assign read_valid = valid [read_addr];
assign read_dirty = dirty [read_addr];
@ -73,15 +70,12 @@ module VX_tag_data_structure #(
wire going_to_write = (|write_enable);
integer f;
integer l;
integer i;
always @(posedge clk) begin
if (reset) begin
for (l = 0; l < `BANK_LINE_COUNT; l=l+1) begin
valid[l] <= 0;
// tag [l] <= 0;
dirty[l] <= 0;
// data [l] <= 0;
for (i = 0; i < `BANK_LINE_COUNT; i = i + 1) begin
valid[i] <= 0;
dirty[i] <= 0;
end
end else if (!stall_bank_pipe) begin
if (going_to_write) begin
@ -94,18 +88,17 @@ module VX_tag_data_structure #(
end
end else if (fill_sent) begin
dirty[write_addr] <= 0;
// valid[write_addr] <= 0;
end
if (invalidate) begin
valid[write_addr] <= 0;
end
for (f = 0; f < `DBANK_LINE_WORDS; f = f + 1) begin
if (write_enable[f][0]) data[write_addr][f][0] <= write_data[f][7 :0 ];
if (write_enable[f][1]) data[write_addr][f][1] <= write_data[f][15:8 ];
if (write_enable[f][2]) data[write_addr][f][2] <= write_data[f][23:16];
if (write_enable[f][3]) data[write_addr][f][3] <= write_data[f][31:24];
for (i = 0; i < `BANK_LINE_WORDS; i = i + 1) begin
if (write_enable[i][0]) data[write_addr][i][0] <= write_data[i * `WORD_WIDTH + 0 * `BYTE_WIDTH +: `BYTE_WIDTH];
if (write_enable[i][1]) data[write_addr][i][1] <= write_data[i * `WORD_WIDTH + 1 * `BYTE_WIDTH +: `BYTE_WIDTH];
if (write_enable[i][2]) data[write_addr][i][2] <= write_data[i * `WORD_WIDTH + 2 * `BYTE_WIDTH +: `BYTE_WIDTH];
if (write_enable[i][3]) data[write_addr][i][3] <= write_data[i * `WORD_WIDTH + 3 * `BYTE_WIDTH +: `BYTE_WIDTH];
end
end
end

24
hw/rtl/interfaces/VX_cache_core_req_if.v
View file

@ -4,22 +4,18 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_req_if #(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
// Core request
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][2:0] core_req_read;
wire [NUM_REQUESTS-1:0][2:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_data;
wire core_req_ready;
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire [NUM_REQUESTS-1:0] core_req_valid;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_read;
wire [NUM_REQUESTS-1:0][`WORD_SEL_BITS-1:0] core_req_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag;
wire core_req_ready;
endinterface

20
hw/rtl/interfaces/VX_cache_core_rsp_if.v
View file

@ -4,21 +4,15 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_core_rsp_if #(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 1,
parameter WORD_SIZE = 1,
parameter CORE_TAG_WIDTH = 1
) ();
// Core response
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_rsp_read;
wire [1:0] core_rsp_write;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_data;
wire core_rsp_ready;
// Core response meta data
wire [`NW_BITS-1:0] core_rsp_warp_num;
wire [NUM_REQUESTS-1:0] core_rsp_valid;
wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data;
wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag;
wire core_rsp_ready;
endinterface

18
hw/rtl/interfaces/VX_cache_dram_req_if.v
View file

@ -4,17 +4,17 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_dram_req_if #(
parameter BANK_LINE_WORDS = 2
parameter DRAM_LINE_WIDTH = 1,
parameter DRAM_ADDR_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) ();
// DRAM Request
wire dram_req_write;
wire dram_req_read;
wire [31:0] dram_req_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_req_data;
wire dram_req_ready;
wire dram_rsp_ready;
wire dram_req_read;
wire dram_req_write;
wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr;
wire [DRAM_LINE_WIDTH-1:0] dram_req_data;
wire [DRAM_TAG_WIDTH-1:0] dram_req_tag;
wire dram_req_ready;
endinterface

12
hw/rtl/interfaces/VX_cache_dram_rsp_if.v
View file

@ -4,12 +4,14 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_dram_rsp_if #(
parameter BANK_LINE_WORDS = 2
parameter DRAM_LINE_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
) ();
// DRAM Response
wire dram_rsp_valid;
wire [31:0] dram_rsp_addr;
wire [BANK_LINE_WORDS-1:0][31:0] dram_rsp_data;
wire dram_rsp_valid;
wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data;
wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag;
wire dram_rsp_ready;
endinterface

10
hw/rtl/interfaces/VX_cache_snp_req_if.v
View file

@ -3,11 +3,13 @@
`include "../cache/VX_cache_config.vh"
interface VX_cache_snp_req_if ();
interface VX_cache_snp_req_if #(
parameter DRAM_ADDR_WIDTH = 1
) ();
wire snp_req_valid;
wire [31:0] snp_req_addr;
wire snp_req_ready;
wire snp_req_valid;
wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr;
wire snp_req_ready;
endinterface

17
hw/rtl/interfaces/VX_csr_wb_if.v
View file

@ -1,17 +0,0 @@
`ifndef VX_CSR_WB_IF
`define VX_CSR_WB_IF
`include "VX_define.vh"
interface VX_csr_wb_if ();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0][31:0] csr_result;
endinterface
`endif

4
hw/rtl/interfaces/VX_frE_to_bckE_req_if.v
View file

@ -16,8 +16,8 @@ interface VX_frE_to_bckE_req_if ();
wire [1:0] wb;
wire rs2_src;
wire [31:0] itype_immed;
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [2:0] branch_type;
wire [19:0] upper_immed;
wire [31:0] curr_PC;

2
hw/rtl/interfaces/VX_gpgpu_inst_req_if.v → hw/rtl/interfaces/VX_gpu_inst_req_if.v
View file

@ -3,7 +3,7 @@
`include "VX_define.vh"
interface VX_gpgpu_inst_req_if();
interface VX_gpu_inst_req_if();
wire [`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;

18
hw/rtl/interfaces/VX_inst_exec_wb_if.v
View file

@ -1,18 +0,0 @@
`ifndef VX_INST_EXEC_WB_IF
`define VX_INST_EXEC_WB_IF
`include "VX_define.vh"
interface VX_inst_exec_wb_if ();
wire [`NUM_THREADS-1:0][31:0] alu_result;
wire [31:0] exec_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

18
hw/rtl/interfaces/VX_inst_mem_wb_if.v
View file

@ -1,18 +0,0 @@
`ifndef VX_INST_MEM_WB_IF
`define VX_INST_MEM_WB_IF
`include "VX_define.vh"
interface VX_inst_mem_wb_if ();
wire [`NUM_THREADS-1:0][31:0] loaded_data;
wire [31:0] mem_wb_pc;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

2
hw/rtl/interfaces/VX_inst_meta_if.v
View file

@ -8,7 +8,7 @@ interface VX_inst_meta_if ();
wire [31:0] instruction;
wire [31:0] inst_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0] valid;
wire [`NUM_THREADS-1:0] valid;
endinterface

20
hw/rtl/interfaces/VX_lsu_req_if.v
View file

@ -6,16 +6,16 @@
interface VX_lsu_req_if ();
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [2:0] mem_read;
wire [2:0] mem_write;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] valid;
wire [31:0] lsu_pc;
wire [`NW_BITS-1:0] warp_num;
wire [`NUM_THREADS-1:0][31:0] store_data;
wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire [31:0] offset; // itype_immed
wire [`WORD_SEL_BITS-1:0] mem_read;
wire [`WORD_SEL_BITS-1:0] mem_write;
wire [4:0] rd; // dest register
wire [1:0] wb; //
endinterface

10
hw/rtl/interfaces/VX_wb_if.v
View file

@ -5,12 +5,12 @@
interface VX_wb_if ();
wire [`NUM_THREADS-1:0][31:0] write_data;
wire [31:0] wb_pc;
wire [`NUM_THREADS-1:0] valid;
wire [`NUM_THREADS-1:0][31:0] data;
wire [`NW_BITS-1:0] warp_num;
wire [4:0] rd;
wire [1:0] wb;
wire [`NUM_THREADS-1:0] wb_valid;
wire [`NW_BITS-1:0] wb_warp_num;
wire [1:0] wb;
wire [31:0] pc;
endinterface

32
hw/rtl/libs/VX_priority_encoder_w_mask.v
View file

@ -1,32 +0,0 @@
`include "VX_define.vh"
module VX_priority_encoder_w_mask #(
parameter N = 10
) (
input wire[N-1:0] valids,
output reg [N-1:0] mask,
//output reg[$clog2(N)-1:0] index,
output reg[(`LOG2UP(N))-1:0] index,
//output reg[`LOG2UP(N):0] index, // eh
output reg found
);
integer i;
always @(valids) begin
index = 0;
found = 0;
// mask = 0;
for (i = 0; i < N; i=i+1) begin
if (valids[i]) begin
//index = i[$clog2(N)-1:0];
index = i[(`LOG2UP(N))-1:0];
found = 1;
// mask[index] = (1 << i);
// $display("%h",(1 << i));
end
end
end
assign mask = found ? (1 << index) : 0;
endmodule

277
hw/simulate/simulator.cpp
View file

@ -2,17 +2,16 @@
#include <iostream>
#include <iomanip>
Simulator::Simulator(RAM *ram)
: total_cycles_(0)
, dram_stalled_(false)
, I_dram_stalled_(false) {
ram_ = ram;
uint64_t time_stamp = 0;
#ifdef USE_MULTICORE
double sc_time_stamp() {
return time_stamp;
}
Simulator::Simulator(RAM *ram)
: dram_stalled_(false) {
ram_ = ram;
vortex_ = new VVortex_Socket();
#else
vortex_ = new VVortex();
#endif
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
@ -31,46 +30,44 @@ Simulator::~Simulator() {
void Simulator::print_stats(std::ostream& out) {
out << std::left;
out << std::setw(24) << "# of total cycles:" << std::dec << total_cycles_ << std::endl;
out << std::setw(24) << "# of total cycles:" << std::dec << time_stamp/2 << std::endl;
}
void Simulator::dbus_driver() {
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < dram_req_vec_.size(); i++) {
if (dram_req_vec_[i].cycles_left > 0) {
dram_req_vec_[i].cycles_left -= 1;
}
if ((dram_req_vec_[i].cycles_left == 0) && (!dequeue_valid)) {
if ((dequeue_index == -1)
&& (dram_req_vec_[i].cycles_left == 0)) {
dequeue_index = i;
dequeue_valid = true;
}
}
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
if ((dequeue_index != -1)
&& vortex_->dram_rsp_ready) {
vortex_->dram_rsp_valid = 1;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
vortex_->dram_rsp_tag = dram_req_vec_[dequeue_index].tag;
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
}
#ifdef USE_MULTICORE
if (!dram_stalled_) {
if (!dram_stalled_) {
if (vortex_->dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
dram_req.cycles_left = DRAM_LATENCY;
dram_req.data = (unsigned*)malloc(GLOBAL_BLOCK_SIZE);
dram_req.tag = vortex_->dram_req_tag;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
@ -79,9 +76,8 @@ void Simulator::dbus_driver() {
}
if (vortex_->dram_req_write) {
unsigned base_addr = vortex_->dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned base_addr = (vortex_->dram_req_addr * GLOBAL_BLOCK_SIZE);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
@ -89,156 +85,20 @@ void Simulator::dbus_driver() {
}
}
if (vortex_->dram_rsp_ready && dequeue_valid) {
vortex_->dram_rsp_valid = 1;
vortex_->dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->dram_rsp_valid = 0;
vortex_->dram_rsp_addr = 0;
}
vortex_->dram_req_ready = ~dram_stalled_;
#else
if (!dram_stalled_) {
if (vortex_->D_dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->D_dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
dram_req_vec_.push_back(dram_req);
}
if (vortex_->D_dram_req_write) {
unsigned base_addr = vortex_->D_dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->D_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->D_dram_rsp_ready && dequeue_valid) {
vortex_->D_dram_rsp_valid = 1;
vortex_->D_dram_rsp_addr = dram_req_vec_[dequeue_index].base_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->D_dram_rsp_data[i] = dram_req_vec_[dequeue_index].data[i];
}
free(dram_req_vec_[dequeue_index].data);
dram_req_vec_.erase(dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->D_dram_rsp_valid = 0;
vortex_->D_dram_rsp_addr = 0;
}
vortex_->D_dram_req_ready = ~dram_stalled_;
#endif
}
#ifndef USE_MULTICORE
void Simulator::ibus_driver() {
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < I_dram_req_vec_.size(); i++) {
if (I_dram_req_vec_[i].cycles_left > 0) {
I_dram_req_vec_[i].cycles_left -= 1;
}
if ((I_dram_req_vec_[i].cycles_left == 0) && (!dequeue_valid)) {
dequeue_index = i;
dequeue_valid = true;
}
}
#ifdef ENABLE_DRAM_STALLS
I_dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
I_dram_stalled_ = true;
dram_stalled_ = false;
if (0 == ((time_stamp/2) % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (I_dram_req_vec_.size() >= DRAM_RQ_SIZE) {
I_dram_stalled_ = true;
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
if (!I_dram_stalled_) {
// std::cout << "Icache Dram Request received!\n";
if (vortex_->I_dram_req_read) {
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = DRAM_LATENCY;
dram_req.base_addr = vortex_->I_dram_req_addr;
dram_req.data = (unsigned *)malloc(GLOBAL_BLOCK_SIZE_BYTES);
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram_->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
I_dram_req_vec_.push_back(dram_req);
}
if (vortex_->I_dram_req_write) {
unsigned base_addr = vortex_->I_dram_req_addr;
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex_->I_dram_req_data[i];
ram_->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex_->I_dram_rsp_ready && dequeue_valid) {
// std::cout << "Icache Dram Response Sending...!\n";
vortex_->I_dram_rsp_valid = 1;
vortex_->I_dram_rsp_addr = I_dram_req_vec_[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (I_dram_req_vec_[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < (GLOBAL_BLOCK_SIZE_BYTES / 4); i++) {
vortex_->I_dram_rsp_data[i] = I_dram_req_vec_[dequeue_index].data[i];
}
free(I_dram_req_vec_[dequeue_index].data);
I_dram_req_vec_.erase(I_dram_req_vec_.begin() + dequeue_index);
} else {
vortex_->I_dram_rsp_valid = 0;
vortex_->I_dram_rsp_addr = 0;
}
vortex_->I_dram_req_ready = ~I_dram_stalled_;
vortex_->dram_req_ready = ~dram_stalled_;
}
#endif
void Simulator::io_handler() {
#ifdef USE_MULTICORE
bool io_valid = false;
for (int c = 0; c < NUM_CORES; c++) {
if (vortex_->io_valid[c]) {
@ -251,17 +111,10 @@ void Simulator::io_handler() {
if (io_valid) {
std::cout << std::flush;
}
#else
if (vortex_->io_valid) {
uint32_t data_write = (uint32_t)vortex_->io_data;
char c = (char)data_write;
std::cerr << c;
std::cout << std::flush;
}
#endif
}
void Simulator::reset() {
time_stamp = 0;
vortex_->reset = 1;
this->step();
vortex_->reset = 0;
@ -269,37 +122,21 @@ void Simulator::reset() {
void Simulator::step() {
vortex_->clk = 0;
vortex_->eval();
#ifdef VCD_OUTPUT
trace_->dump(2 * total_cycles_ + 0);
#endif
this->eval();
vortex_->clk = 1;
vortex_->eval();
#ifdef ENABLE_DRAM_STALLS
dram_stalled_ = false;
if (0 == (total_cycles_ % DRAM_STALLS_MODULO)) {
dram_stalled_ = true;
} else
if (dram_req_vec_.size() >= DRAM_RQ_SIZE) {
dram_stalled_ = true;
}
#endif
#ifndef USE_MULTICORE
ibus_driver();
#endif
this->eval();
dbus_driver();
io_handler();
}
void Simulator::eval() {
vortex_->eval();
#ifdef VCD_OUTPUT
trace_->dump(2 * total_cycles_ + 1);
trace_->dump(time_stamp);
#endif
++total_cycles_;
++time_stamp;
}
void Simulator::wait(uint32_t cycles) {
@ -314,8 +151,8 @@ bool Simulator::is_busy() {
void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
// align address to LLC block boundaries
auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * (mem_addr / GLOBAL_BLOCK_SIZE_BYTES);
auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
auto aligned_addr_start = mem_addr / GLOBAL_BLOCK_SIZE;
auto aligned_addr_end = (mem_addr + size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
// submit snoop requests for the needed blocks
vortex_->llc_snp_req_addr = aligned_addr_start;
@ -326,7 +163,7 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
vortex_->llc_snp_req_valid = false;
if (vortex_->llc_snp_req_addr >= aligned_addr_end)
break;
vortex_->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
vortex_->llc_snp_req_addr += 1;
}
if (vortex_->llc_snp_req_ready) {
vortex_->llc_snp_req_valid = true;
@ -334,9 +171,9 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
}
}
void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
printf("[sim] total cycles: %ld\n", this->total_cycles_);
void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
// send snoop requests to the caches
printf("[sim] total cycles: %ld\n", time_stamp/2);
this->send_snoops(mem_addr, size);
this->wait(PIPELINE_FLUSH_LATENCY);
}
@ -353,11 +190,15 @@ bool Simulator::run() {
// wait 5 cycles to flush the pipeline
this->wait(5);
#ifdef USE_MULTICORE
int status = 0;
#else
// check riscv-tests PASSED/FAILED status
int status = (int)vortex_->Vortex->back_end->writeback->last_data_wb & 0xf;
#if (NUM_CLUSTERS == 1 && NUM_CORES == 1)
int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk1__DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
#else
#if (NUM_CLUSTERS == 1)
int status = (int)vortex_->Vortex_Socket->genblk1__DOT__Vortex_Cluster->genblk2__DOT__genblk1__BRA__0__KET____DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
#else
int status = (int)vortex_->Vortex_Socket->genblk2__DOT__genblk2__BRA__0__KET____DOT__Vortex_Cluster->genblk2__DOT__genblk1__BRA__0__KET____DOT__vortex_core->back_end->writeback->last_data_wb & 0xf;
#endif
#endif
return (status == 1);

25
hw/simulate/simulator.h
View file

@ -1,12 +1,7 @@
#pragma once
#ifdef USE_MULTICORE
#include "VVortex_Socket.h"
#include "VVortex_Socket__Syms.h"
#else
#include "VVortex.h"
#include "VVortex__Syms.h"
#endif
#include "verilated.h"
#ifdef VCD_OUTPUT
@ -26,9 +21,9 @@
#define PIPELINE_FLUSH_LATENCY 300
typedef struct {
int cycles_left;
unsigned base_addr;
int cycles_left;
unsigned *data;
unsigned tag;
} dram_req_t;
class Simulator {
@ -46,26 +41,18 @@ public:
private:
#ifndef USE_MULTICORE
void ibus_driver();
#endif
void eval();
void wait(uint32_t cycles);
void dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
uint64_t total_cycles_;
bool dram_stalled_;
bool I_dram_stalled_;
std::vector<dram_req_t> dram_req_vec_;
std::vector<dram_req_t> I_dram_req_vec_;
RAM *ram_;
#ifdef USE_MULTICORE
VVortex_Socket *vortex_;
#else
VVortex *vortex_;
#endif
#ifdef VCD_OUTPUT
VerilatedVcdC *trace_;
#endif

8
hw/simulate/testbench.cpp
View file

@ -3,8 +3,6 @@
#include <fstream>
#include <iomanip>
#define NUM_TESTS 46
int main(int argc, char **argv)
{
@ -14,9 +12,9 @@ int main(int argc, char **argv)
//#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
bool passed = true;
std::string tests[NUM_TESTS] = {
std::string tests[] = {
"../../benchmarks/riscv_tests/rv32ui-p-add.hex",
"../../benchmarks/riscv_tests/rv32ui-p-addi.hex",
"../../benchmarks/riscv_tests/rv32ui-p-and.hex",
@ -29,7 +27,7 @@ int main(int argc, char **argv)
"../../benchmarks/riscv_tests/rv32ui-p-bltu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-bne.hex",
"../../benchmarks/riscv_tests/rv32ui-p-jal.hex",
"../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
"../../benchmarks/riscv_tests/rv32ui-p-jalr.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lb.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lbu.hex",
"../../benchmarks/riscv_tests/rv32ui-p-lh.hex",

4
runtime/startup/vx_start.S
View file

@ -5,7 +5,7 @@
.type _start, @function
_start:
la a1, vx_set_sp
li a0, NW # activate all warps
li a0, NUM_WARPS # activate all warps
.word 0x00b5106b # wspawn a0(numWarps), a1(PC SPAWN)
jal vx_set_sp
li a0, 1
@ -29,7 +29,7 @@ _start:
.type vx_set_sp, @function
.global vx_set_sp
vx_set_sp:
li a0, NT
li a0, NUM_THREADS
.word 0x0005006b # activate all threads
.option push

14
runtime/tests/simple/Makefile
View file

@ -1,9 +1,11 @@
COMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-g++
COMP = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-g++
#COMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-g++
CC_FLAGS = -march=rv32im -mabi=ilp32 -O0 -Wl,-Bstatic,-T,../../startup/vx_link.ld -ffreestanding -nostdlib
DMP = /opt/riscv-new/drops/bin/riscv32-unknown-elf-objdump
CPY = /opt/riscv-new/drops/bin/riscv32-unknown-elf-objcopy
DMP = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objdump
CPY = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objcopy
NEWLIB = ../../newlib/newlib.c
@ -12,7 +14,11 @@ VX_INT = ../../intrinsics/vx_intrinsics.s
VX_IO = ../../io/vx_io.s ../../io/vx_io.c
VX_API = ../../vx_api/vx_api.c
VX_FIO = ../../fileio/fileio.s
LIBS = /opt/riscv-new/drops/riscv32-unknown-elf/lib/libc.a /opt/riscv-new/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_MAIN = vx_simple_main
LIBS = ~/dev/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libc.a ~/dev/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
#LIBS = /opt/riscv-new/drops/riscv32-unknown-elf/lib/libc.a /opt/riscv-new/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_SRCS = vx_simple_main.c tests.c

2
runtime/tests/simple/tests.c
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@ -8,7 +8,7 @@ int tmc_array[4] = {5,5,5,5};
void test_tmc()
{
vx_print_str("testing_tmc\n");
//vx_print_str("testing_tmc\n");
vx_tmc(4);

2
runtime/tests/simple/vx_simple_main.c
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@ -1,7 +1,7 @@
#include "../../intrinsics/vx_intrinsics.h"
#include "../../io/vx_io.h"
#include "../common/tests.h"
#include "tests.h"
#include "../../vx_api/vx_api.h"

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