mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
Added ifndef statements for the vector extension anywhere they didn't exist already
Added ifndef statements for the vector extension anywhere they didn't exist already more ifdef statements more ifdef Update decode.cpp Update decode.cpp Update decode.cpp
This commit is contained in:
MichaelJSr
parent
cb491ddb53
commit
a2cfeffcfe
11 changed files with 101 additions and 18 deletions
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@ -17,7 +17,7 @@ CXXFLAGS += $(CONFIGS)
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LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
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LDFLAGS += -Wl,-rpath,$(THIRD_PARTY_DIR)/ramulator -L$(THIRD_PARTY_DIR)/ramulator -lramulator
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SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
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SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
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SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(SRC_DIR)/core.cpp $(SRC_DIR)/emulator.cpp $(SRC_DIR)/decode.cpp $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp
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# Add V extension sources
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@ -47,7 +47,9 @@ static const std::unordered_map<Opcode, InstType> sc_instTable = {
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{Opcode::FMSUB, InstType::R4},
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{Opcode::FMNMADD, InstType::R4},
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{Opcode::FMNMSUB, InstType::R4},
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#ifdef EXT_V_ENABLE
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{Opcode::VSET, InstType::V},
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#endif
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{Opcode::EXT1, InstType::R},
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{Opcode::EXT2, InstType::R4},
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{Opcode::R_W, InstType::R},
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@ -373,7 +375,9 @@ static const char* op_string(const Instr &instr) {
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case Opcode::FMSUB: return func2 ? "FMSUB.D" : "FMSUB.S";
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case Opcode::FMNMADD: return func2 ? "FNMADD.D" : "FNMADD.S";
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case Opcode::FMNMSUB: return func2 ? "FNMSUB.D" : "FNMSUB.S";
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#ifdef EXT_V_ENABLE
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case Opcode::VSET: return "VSET";
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#endif
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case Opcode::EXT1:
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switch (func7) {
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case 0:
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@ -405,6 +409,7 @@ static const char* op_string(const Instr &instr) {
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}
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}
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#ifdef EXT_V_ENABLE
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inline void print_vec_attr(std::ostream &os, const Instr &instr) {
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uint32_t mask = instr.getVattrMask();
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if (mask & vattr_vlswidth)
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@ -432,6 +437,7 @@ inline void print_vec_attr(std::ostream &os, const Instr &instr) {
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if (mask & vattr_vediv)
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os << ", ediv:" << instr.getVediv();
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}
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#endif
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namespace vortex {
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std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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@ -453,6 +459,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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os << "0x" << std::hex << instr.getImm() << std::dec;
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}
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#ifdef EXT_V_ENABLE
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if (instr.getOpcode() == Opcode::SYS && instr.getFunc3() >= 5) {
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// CSRs with immediate values
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if (sep++ != 0) { os << ", "; } else { os << " "; }
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@ -462,6 +469,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
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if (instr.getVattrMask() != 0) {
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print_vec_attr(os, instr);
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}
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#endif
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return os;
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}
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}
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@ -473,9 +481,11 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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auto func2 = (code >> shift_func2) & mask_func2;
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auto func3 = (code >> shift_func3) & mask_func3;
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auto func6 = (code >> shift_func6) & mask_func6;
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auto func7 = (code >> shift_func7) & mask_func7;
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#ifdef EXT_V_ENABLE
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auto func6 = (code >> shift_func6) & mask_func6;
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__unused(func6);
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#endif
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auto rd = (code >> shift_rd) & mask_reg;
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auto rs1 = (code >> shift_rs1) & mask_reg;
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@ -489,11 +499,13 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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}
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auto iType = op_it->second;
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#ifdef EXT_V_ENABLE
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if (op == Opcode::FL || op == Opcode::FS) {
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if (func3 != 0x2 && func3 != 0x3) {
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iType = InstType::V;
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}
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}
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#endif
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switch (iType) {
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case InstType::R:
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@ -582,7 +594,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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instr->addSrcReg(rs2, RegType::Integer);
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break;
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}
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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instr->setFunc7(func7);
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break;
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@ -591,7 +605,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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case Opcode::TCU: {
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instr->setDestReg(rs1, RegType::Integer);
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instr->addSrcReg(rs1, RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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instr->setFunc7(func7);
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auto imm = code >> shift_rs2;
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instr->setImm(sext(imm, width_i_imm));
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@ -601,7 +617,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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case Opcode::JALR:
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instr->setDestReg(rd, RegType::Integer);
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instr->addSrcReg(rs1, RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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if (func3 == 0x1 || func3 == 0x5) {
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// Shift instructions
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auto shamt = rs2; // uint5
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@ -622,19 +640,25 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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case Opcode::FL: {
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instr->setDestReg(rd, (op == Opcode::FL) ? RegType::Float : RegType::Integer);
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instr->addSrcReg(rs1, RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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auto imm = code >> shift_rs2;
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instr->setImm(sext(imm, width_i_imm));
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} break;
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case Opcode::FENCE:
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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instr->setImm(code >> shift_rs2);
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break;
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case Opcode::SYS:
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if (func3 != 0) {
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// CSR instructions
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instr->setDestReg(rd, RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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if (func3 < 5) {
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instr->addSrcReg(rs1, RegType::Integer);
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} else {
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@ -655,7 +679,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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case InstType::S: {
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instr->addSrcReg(rs1, RegType::Integer);
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instr->addSrcReg(rs2, (op == Opcode::FS) ? RegType::Float : RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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auto imm = (func7 << width_reg) | rd;
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instr->setImm(sext(imm, width_i_imm));
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} break;
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@ -663,7 +689,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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case InstType::B: {
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instr->addSrcReg(rs1, RegType::Integer);
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instr->addSrcReg(rs2, RegType::Integer);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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auto bit_11 = rd & 0x1;
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auto bits_4_1 = rd >> 1;
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auto bit_10_5 = func7 & 0x3f;
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@ -695,7 +723,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
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instr->addSrcReg(rs2, RegType::Float);
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instr->addSrcReg(rs3, RegType::Float);
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instr->setFunc2(func2);
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#ifdef EXT_V_ENABLE
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instr->setFunc3(func3);
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#endif
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} break;
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#ifdef EXT_V_ENABLE
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@ -33,7 +33,9 @@ using namespace vortex;
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Emulator::warp_t::warp_t(const Arch& arch)
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: ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS))
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, freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS))
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#ifdef EXT_V_ENABLE
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, vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS))
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#endif
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, uuid(0)
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{}
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@ -43,9 +45,11 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
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this->uuid = 0;
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this->fcsr = 0;
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#ifdef EXT_V_ENABLE
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this->vtype = {0, 0, 0, 0, 0};
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this->vl = 0;
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this->vlmax = 0;
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#endif
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for (auto& reg_file : this->ireg_file) {
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for (auto& reg : reg_file) {
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@ -68,6 +72,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
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}
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}
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#ifdef EXT_V_ENABLE
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for (auto& reg_file : this->vreg_file) {
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for (auto& reg : reg_file) {
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#ifndef NDEBUG
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@ -77,6 +82,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
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#endif
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}
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}
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#endif
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}
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///////////////////////////////////////////////////////////////////////////////
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@ -92,13 +98,17 @@ Emulator::Emulator(const Arch &arch, const DCRS &dcrs, Core* core)
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// considered to be big enough to hold input tiles for one output tile.
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// In future versions, scratchpad size should be fixed to an appropriate value.
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, scratchpad(std::vector<Word>(32 * 32 * 32768))
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#ifdef EXT_V_ENABLE
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, csrs_(arch.num_warps())
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#endif
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{
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std::srand(50);
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#ifdef EXT_V_ENABLE
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for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
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csrs_.at(i).resize(arch.num_threads());
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}
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#endif
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this->clear();
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}
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@ -480,6 +490,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
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case VX_CSR_FRM: return (warps_.at(wid).fcsr >> 5);
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case VX_CSR_FCSR: return warps_.at(wid).fcsr;
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#ifdef EXT_V_ENABLE
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// Vector CRSs
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case VX_CSR_VSTART:
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return csrs_.at(wid).at(tid)[VX_CSR_VSTART];
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@ -504,6 +515,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
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return csrs_.at(wid).at(tid)[VX_CSR_VTIME];
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case VX_CSR_VINSTRET:
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return csrs_.at(wid).at(tid)[VX_CSR_VINSTRET];
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#endif
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case VX_CSR_MHARTID: return (core_->id() * arch_.num_warps() + wid) * arch_.num_threads() + tid;
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case VX_CSR_THREAD_ID: return tid;
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@ -621,6 +633,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
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csr_mscratch_ = value;
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break;
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#ifdef EXT_V_ENABLE
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// Vector CRSs
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case VX_CSR_VSTART:
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csrs_.at(wid).at(tid)[VX_CSR_VSTART] = value;
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@ -642,6 +655,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
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csrs_.at(wid).at(tid)[VX_CSR_VTYPE] = value;
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break;
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case VX_CSR_VLENB: // read only, set to VLEN / 8
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#endif
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case VX_CSR_SATP:
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#ifdef VM_ENABLE
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@ -81,6 +81,7 @@ private:
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bool fallthrough;
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};
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#ifdef EXT_V_ENABLE
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struct vtype_t {
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uint32_t vill;
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uint32_t vma;
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@ -88,6 +89,7 @@ private:
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uint32_t vsew;
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uint32_t vlmul;
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};
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#endif
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union reg_data_t {
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Word u;
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@ -109,12 +111,14 @@ private:
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ThreadMask tmask;
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std::vector<std::vector<Word>> ireg_file;
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std::vector<std::vector<uint64_t>>freg_file;
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std::vector<std::vector<Byte>> vreg_file;
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std::stack<ipdom_entry_t> ipdom_stack;
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Byte fcsr;
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#ifdef EXT_V_ENABLE
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std::vector<std::vector<Byte>> vreg_file;
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vtype_t vtype;
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uint32_t vl;
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Word vlmax;
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#endif
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uint32_t uuid;
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};
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@ -173,7 +177,9 @@ private:
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uint32_t mat_size;
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uint32_t tc_size;
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uint32_t tc_num;
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#ifdef EXT_V_ENABLE
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std::vector<std::vector<std::unordered_map<uint32_t, uint32_t>>> csrs_;
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#endif
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};
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}
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@ -25,7 +25,9 @@
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#include "emulator.h"
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#include "instr.h"
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#include "core.h"
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#ifdef EXT_V_ENABLE
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#include "processor_impl.h"
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#endif
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#include "VX_types.h"
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using namespace vortex;
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@ -117,8 +119,10 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
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}
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DPN(2, "}" << std::endl);
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break;
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#ifdef EXT_V_ENABLE
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case RegType::Vector:
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break;
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#endif
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default:
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break;
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}
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@ -707,11 +711,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
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}
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}
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rd_write = true;
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} else {
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#ifdef EXT_V_ENABLE
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this->loadVector(instr, wid, rsdata);
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#endif
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}
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#ifdef EXT_V_ENABLE
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else {
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this->loadVector(instr, wid, rsdata);
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}
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#endif
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break;
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}
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case Opcode::S:
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@ -744,11 +749,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
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std::abort();
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}
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}
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} else {
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#ifdef EXT_V_ENABLE
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this->storeVector(instr, wid, rsdata);
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#endif
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}
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#ifdef EXT_V_ENABLE
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else {
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this->storeVector(instr, wid, rsdata);
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}
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#endif
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break;
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}
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case Opcode::AMO: {
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@ -42,8 +42,10 @@ enum class Opcode {
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// RV64 Standard Extension
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R_W = 0x3b,
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I_W = 0x1b,
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#ifdef EXT_V_ENABLE
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// Vector Extension
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VSET = 0x57,
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#endif
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// Custom Extensions
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EXT1 = 0x0b,
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EXT2 = 0x2b,
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@ -58,7 +60,9 @@ enum class InstType {
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B,
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U,
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J,
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#ifdef EXT_V_ENABLE
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V,
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#endif
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R4
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};
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@ -138,6 +142,7 @@ public:
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, rdest_(0)
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, func2_(0)
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, func3_(0)
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#ifdef EXT_V_ENABLE
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, func6_(0)
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, func7_(0)
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, vmask_(0)
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@ -152,8 +157,9 @@ public:
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, vta_(0)
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, vma_(0)
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, vediv_(0)
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, vattr_mask_(0) {
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for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) {
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, vattr_mask_(0)
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#endif
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{ for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) {
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rsrc_type_[i] = RegType::None;
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rsrc_[i] = 0;
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}
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@ -183,9 +189,11 @@ public:
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void setImm(uint32_t imm) { has_imm_ = true; imm_ = imm; }
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void setFunc2(uint32_t func2) { func2_ = func2; }
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void setFunc7(uint32_t func7) { func7_ = func7; }
|
||||
|
||||
#ifdef EXT_V_ENABLE
|
||||
void setFunc3(uint32_t func3) { func3_ = func3; }
|
||||
void setFunc6(uint32_t func6) { func6_ = func6; }
|
||||
void setFunc7(uint32_t func7) { func7_ = func7; }
|
||||
|
||||
// Attributes for Vector instructions
|
||||
void setVlsWidth(uint32_t width) { vlsWidth_ = width; vattr_mask_ |= vattr_vlswidth; }
|
||||
|
|
@ -200,6 +208,7 @@ public:
|
|||
void setVta(uint32_t vta) { vta_ = vta; vattr_mask_ |= vattr_vta; }
|
||||
void setVma(uint32_t vma) { vma_ = vma; vattr_mask_ |= vattr_vma; }
|
||||
void setVediv(uint32_t ediv) { vediv_ = 1 << ediv; vattr_mask_ |= vattr_vediv; }
|
||||
#endif
|
||||
|
||||
Opcode getOpcode() const { return opcode_; }
|
||||
|
||||
|
|
@ -215,9 +224,11 @@ public:
|
|||
|
||||
uint32_t getFunc2() const { return func2_; }
|
||||
uint32_t getFunc3() const { return func3_; }
|
||||
uint32_t getFunc6() const { return func6_; }
|
||||
uint32_t getFunc7() const { return func7_; }
|
||||
|
||||
#ifdef EXT_V_ENABLE
|
||||
uint32_t getFunc6() const { return func6_; }
|
||||
|
||||
uint32_t getVlsWidth() const { return vlsWidth_; }
|
||||
uint32_t getVmop() const { return vMop_; }
|
||||
uint32_t getVumop() const { return vUmop_; }
|
||||
|
|
@ -231,6 +242,7 @@ public:
|
|||
uint32_t getVma() const { return vma_; }
|
||||
uint32_t getVediv() const { return vediv_; }
|
||||
uint32_t getVattrMask() const { return vattr_mask_; }
|
||||
#endif
|
||||
|
||||
private:
|
||||
|
||||
|
|
@ -248,9 +260,11 @@ private:
|
|||
uint32_t rdest_;
|
||||
uint32_t func2_;
|
||||
uint32_t func3_;
|
||||
uint32_t func6_;
|
||||
uint32_t func7_;
|
||||
|
||||
#ifdef EXT_V_ENABLE
|
||||
uint32_t func6_;
|
||||
|
||||
// Vector
|
||||
uint32_t vmask_;
|
||||
uint32_t vlsWidth_;
|
||||
|
|
@ -265,6 +279,7 @@ private:
|
|||
uint32_t vma_;
|
||||
uint32_t vediv_;
|
||||
uint32_t vattr_mask_;
|
||||
#endif
|
||||
|
||||
friend std::ostream &operator<<(std::ostream &, const Instr&);
|
||||
};
|
||||
|
|
|
|||
|
|
@ -120,7 +120,9 @@ int main(int argc, char **argv) {
|
|||
#endif
|
||||
// run simulation
|
||||
// vector test exitcode is a special case
|
||||
#ifdef EXT_V_ENABLE
|
||||
if (vector_test) return processor.run();
|
||||
#endif
|
||||
// else continue as normal
|
||||
processor.run();
|
||||
|
||||
|
|
|
|||
|
|
@ -127,7 +127,9 @@ int ProcessorImpl::run() {
|
|||
done = false;
|
||||
continue;
|
||||
}
|
||||
#ifdef EXT_V_ENABLE
|
||||
exitcode |= cluster->get_exitcode();
|
||||
#endif
|
||||
}
|
||||
perf_mem_latency_ += perf_mem_pending_reads_;
|
||||
} while (!done);
|
||||
|
|
|
|||
|
|
@ -84,8 +84,10 @@ enum class RegType {
|
|||
None,
|
||||
Integer,
|
||||
Float,
|
||||
Count,
|
||||
Vector
|
||||
#ifdef EXT_V_ENABLE
|
||||
Vector,
|
||||
#endif
|
||||
Count
|
||||
};
|
||||
|
||||
inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
|
||||
|
|
@ -93,7 +95,9 @@ inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
|
|||
case RegType::None: break;
|
||||
case RegType::Integer: os << "x"; break;
|
||||
case RegType::Float: os << "f"; break;
|
||||
#ifdef EXT_V_ENABLE
|
||||
case RegType::Vector: os << "v"; break;
|
||||
#endif
|
||||
default: assert(false);
|
||||
}
|
||||
return os;
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
// The purpose of this fork is to make simx-v2-vector up to date with master
|
||||
// Thanks to Troibe for his amazing work
|
||||
|
||||
#ifdef EXT_V_ENABLE
|
||||
#include "emulator.h"
|
||||
#include "instr.h"
|
||||
#include "processor_impl.h"
|
||||
|
|
@ -2477,3 +2478,4 @@ void Emulator::executeVector(const Instr &instr, uint32_t wid, std::vector<reg_d
|
|||
std::abort();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
#ifdef EXT_V_ENABLE
|
||||
#pragma once
|
||||
|
||||
using namespace vortex;
|
||||
|
|
@ -2389,3 +2390,4 @@ void vector_op_vv_compress(std::vector<std::vector<Byte>> &vreg_file, uint32_t r
|
|||
std::abort();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue