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Added ifndef statements for the vector extension anywhere they didn't exist already

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Added ifndef statements for the vector extension anywhere they didn't exist already

more ifdef statements

more ifdef

Update decode.cpp

Update decode.cpp

Update decode.cpp
This commit is contained in:
MichaelJSr 2025-01-13 17:46:23 -08:00
parent cb491ddb53
commit a2cfeffcfe
11 changed files with 101 additions and 18 deletions
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2
sim/simx/Makefile
View file

@ -17,7 +17,7 @@ CXXFLAGS += $(CONFIGS)
LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a LDFLAGS += $(THIRD_PARTY_DIR)/softfloat/build/Linux-x86_64-GCC/softfloat.a
LDFLAGS += -Wl,-rpath,$(THIRD_PARTY_DIR)/ramulator -L$(THIRD_PARTY_DIR)/ramulator -lramulator LDFLAGS += -Wl,-rpath,$(THIRD_PARTY_DIR)/ramulator -L$(THIRD_PARTY_DIR)/ramulator -lramulator
SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp SRCS = $(COMMON_DIR)/util.cpp $(COMMON_DIR)/mem.cpp $(COMMON_DIR)/softfloat_ext.cpp $(COMMON_DIR)/rvfloats.cpp $(COMMON_DIR)/dram_sim.cpp
SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(SRC_DIR)/core.cpp $(SRC_DIR)/emulator.cpp $(SRC_DIR)/decode.cpp $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(SRC_DIR)/core.cpp $(SRC_DIR)/emulator.cpp $(SRC_DIR)/decode.cpp $(SRC_DIR)/execute.cpp $(SRC_DIR)/func_unit.cpp $(SRC_DIR)/cache_sim.cpp $(SRC_DIR)/mem_sim.cpp $(SRC_DIR)/local_mem.cpp $(SRC_DIR)/mem_coalescer.cpp $(SRC_DIR)/dcrs.cpp $(SRC_DIR)/types.cpp
# Add V extension sources # Add V extension sources

32
sim/simx/decode.cpp
View file

@ -47,7 +47,9 @@ static const std::unordered_map<Opcode, InstType> sc_instTable = {
{Opcode::FMSUB, InstType::R4}, {Opcode::FMSUB, InstType::R4},
{Opcode::FMNMADD, InstType::R4}, {Opcode::FMNMADD, InstType::R4},
{Opcode::FMNMSUB, InstType::R4}, {Opcode::FMNMSUB, InstType::R4},
#ifdef EXT_V_ENABLE
{Opcode::VSET, InstType::V}, {Opcode::VSET, InstType::V},
#endif
{Opcode::EXT1, InstType::R}, {Opcode::EXT1, InstType::R},
{Opcode::EXT2, InstType::R4}, {Opcode::EXT2, InstType::R4},
{Opcode::R_W, InstType::R}, {Opcode::R_W, InstType::R},
@ -373,7 +375,9 @@ static const char* op_string(const Instr &instr) {
case Opcode::FMSUB: return func2 ? "FMSUB.D" : "FMSUB.S"; case Opcode::FMSUB: return func2 ? "FMSUB.D" : "FMSUB.S";
case Opcode::FMNMADD: return func2 ? "FNMADD.D" : "FNMADD.S"; case Opcode::FMNMADD: return func2 ? "FNMADD.D" : "FNMADD.S";
case Opcode::FMNMSUB: return func2 ? "FNMSUB.D" : "FNMSUB.S"; case Opcode::FMNMSUB: return func2 ? "FNMSUB.D" : "FNMSUB.S";
#ifdef EXT_V_ENABLE
case Opcode::VSET: return "VSET"; case Opcode::VSET: return "VSET";
#endif
case Opcode::EXT1: case Opcode::EXT1:
switch (func7) { switch (func7) {
case 0: case 0:
@ -405,6 +409,7 @@ static const char* op_string(const Instr &instr) {
} }
} }
#ifdef EXT_V_ENABLE
inline void print_vec_attr(std::ostream &os, const Instr &instr) { inline void print_vec_attr(std::ostream &os, const Instr &instr) {
uint32_t mask = instr.getVattrMask(); uint32_t mask = instr.getVattrMask();
if (mask & vattr_vlswidth) if (mask & vattr_vlswidth)
@ -432,6 +437,7 @@ inline void print_vec_attr(std::ostream &os, const Instr &instr) {
if (mask & vattr_vediv) if (mask & vattr_vediv)
os << ", ediv:" << instr.getVediv(); os << ", ediv:" << instr.getVediv();
} }
#endif
namespace vortex { namespace vortex {
std::ostream &operator<<(std::ostream &os, const Instr &instr) { std::ostream &operator<<(std::ostream &os, const Instr &instr) {
@ -453,6 +459,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
if (sep++ != 0) { os << ", "; } else { os << " "; } if (sep++ != 0) { os << ", "; } else { os << " "; }
os << "0x" << std::hex << instr.getImm() << std::dec; os << "0x" << std::hex << instr.getImm() << std::dec;
} }
#ifdef EXT_V_ENABLE
if (instr.getOpcode() == Opcode::SYS && instr.getFunc3() >= 5) { if (instr.getOpcode() == Opcode::SYS && instr.getFunc3() >= 5) {
// CSRs with immediate values // CSRs with immediate values
if (sep++ != 0) { os << ", "; } else { os << " "; } if (sep++ != 0) { os << ", "; } else { os << " "; }
@ -462,6 +469,7 @@ std::ostream &operator<<(std::ostream &os, const Instr &instr) {
if (instr.getVattrMask() != 0) { if (instr.getVattrMask() != 0) {
print_vec_attr(os, instr); print_vec_attr(os, instr);
} }
#endif
return os; return os;
} }
} }
@ -473,9 +481,11 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
auto func2 = (code >> shift_func2) & mask_func2; auto func2 = (code >> shift_func2) & mask_func2;
auto func3 = (code >> shift_func3) & mask_func3; auto func3 = (code >> shift_func3) & mask_func3;
auto func6 = (code >> shift_func6) & mask_func6;
auto func7 = (code >> shift_func7) & mask_func7; auto func7 = (code >> shift_func7) & mask_func7;
#ifdef EXT_V_ENABLE
auto func6 = (code >> shift_func6) & mask_func6;
__unused(func6); __unused(func6);
#endif
auto rd = (code >> shift_rd) & mask_reg; auto rd = (code >> shift_rd) & mask_reg;
auto rs1 = (code >> shift_rs1) & mask_reg; auto rs1 = (code >> shift_rs1) & mask_reg;
@ -489,11 +499,13 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
} }
auto iType = op_it->second; auto iType = op_it->second;
#ifdef EXT_V_ENABLE
if (op == Opcode::FL || op == Opcode::FS) { if (op == Opcode::FL || op == Opcode::FS) {
if (func3 != 0x2 && func3 != 0x3) { if (func3 != 0x2 && func3 != 0x3) {
iType = InstType::V; iType = InstType::V;
} }
} }
#endif
switch (iType) { switch (iType) {
case InstType::R: case InstType::R:
@ -582,7 +594,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
instr->addSrcReg(rs2, RegType::Integer); instr->addSrcReg(rs2, RegType::Integer);
break; break;
} }
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
instr->setFunc7(func7); instr->setFunc7(func7);
break; break;
@ -591,7 +605,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
case Opcode::TCU: { case Opcode::TCU: {
instr->setDestReg(rs1, RegType::Integer); instr->setDestReg(rs1, RegType::Integer);
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
instr->setFunc7(func7); instr->setFunc7(func7);
auto imm = code >> shift_rs2; auto imm = code >> shift_rs2;
instr->setImm(sext(imm, width_i_imm)); instr->setImm(sext(imm, width_i_imm));
@ -601,7 +617,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
case Opcode::JALR: case Opcode::JALR:
instr->setDestReg(rd, RegType::Integer); instr->setDestReg(rd, RegType::Integer);
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
if (func3 == 0x1 || func3 == 0x5) { if (func3 == 0x1 || func3 == 0x5) {
// Shift instructions // Shift instructions
auto shamt = rs2; // uint5 auto shamt = rs2; // uint5
@ -622,19 +640,25 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
case Opcode::FL: { case Opcode::FL: {
instr->setDestReg(rd, (op == Opcode::FL) ? RegType::Float : RegType::Integer); instr->setDestReg(rd, (op == Opcode::FL) ? RegType::Float : RegType::Integer);
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
auto imm = code >> shift_rs2; auto imm = code >> shift_rs2;
instr->setImm(sext(imm, width_i_imm)); instr->setImm(sext(imm, width_i_imm));
} break; } break;
case Opcode::FENCE: case Opcode::FENCE:
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
instr->setImm(code >> shift_rs2); instr->setImm(code >> shift_rs2);
break; break;
case Opcode::SYS: case Opcode::SYS:
if (func3 != 0) { if (func3 != 0) {
// CSR instructions // CSR instructions
instr->setDestReg(rd, RegType::Integer); instr->setDestReg(rd, RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
if (func3 < 5) { if (func3 < 5) {
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
} else { } else {
@ -655,7 +679,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
case InstType::S: { case InstType::S: {
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
instr->addSrcReg(rs2, (op == Opcode::FS) ? RegType::Float : RegType::Integer); instr->addSrcReg(rs2, (op == Opcode::FS) ? RegType::Float : RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
auto imm = (func7 << width_reg) | rd; auto imm = (func7 << width_reg) | rd;
instr->setImm(sext(imm, width_i_imm)); instr->setImm(sext(imm, width_i_imm));
} break; } break;
@ -663,7 +689,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
case InstType::B: { case InstType::B: {
instr->addSrcReg(rs1, RegType::Integer); instr->addSrcReg(rs1, RegType::Integer);
instr->addSrcReg(rs2, RegType::Integer); instr->addSrcReg(rs2, RegType::Integer);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
auto bit_11 = rd & 0x1; auto bit_11 = rd & 0x1;
auto bits_4_1 = rd >> 1; auto bits_4_1 = rd >> 1;
auto bit_10_5 = func7 & 0x3f; auto bit_10_5 = func7 & 0x3f;
@ -695,7 +723,9 @@ std::shared_ptr<Instr> Emulator::decode(uint32_t code) const {
instr->addSrcReg(rs2, RegType::Float); instr->addSrcReg(rs2, RegType::Float);
instr->addSrcReg(rs3, RegType::Float); instr->addSrcReg(rs3, RegType::Float);
instr->setFunc2(func2); instr->setFunc2(func2);
#ifdef EXT_V_ENABLE
instr->setFunc3(func3); instr->setFunc3(func3);
#endif
} break; } break;
#ifdef EXT_V_ENABLE #ifdef EXT_V_ENABLE

14
sim/simx/emulator.cpp
View file

@ -33,7 +33,9 @@ using namespace vortex;
Emulator::warp_t::warp_t(const Arch& arch) Emulator::warp_t::warp_t(const Arch& arch)
: ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS)) : ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS))
, freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS)) , freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS))
#ifdef EXT_V_ENABLE
, vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS)) , vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS))
#endif
, uuid(0) , uuid(0)
{} {}
@ -43,9 +45,11 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
this->uuid = 0; this->uuid = 0;
this->fcsr = 0; this->fcsr = 0;
#ifdef EXT_V_ENABLE
this->vtype = {0, 0, 0, 0, 0}; this->vtype = {0, 0, 0, 0, 0};
this->vl = 0; this->vl = 0;
this->vlmax = 0; this->vlmax = 0;
#endif
for (auto& reg_file : this->ireg_file) { for (auto& reg_file : this->ireg_file) {
for (auto& reg : reg_file) { for (auto& reg : reg_file) {
@ -68,6 +72,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
} }
} }
#ifdef EXT_V_ENABLE
for (auto& reg_file : this->vreg_file) { for (auto& reg_file : this->vreg_file) {
for (auto& reg : reg_file) { for (auto& reg : reg_file) {
#ifndef NDEBUG #ifndef NDEBUG
@ -77,6 +82,7 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
#endif #endif
} }
} }
#endif
} }
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
@ -92,13 +98,17 @@ Emulator::Emulator(const Arch &arch, const DCRS &dcrs, Core* core)
// considered to be big enough to hold input tiles for one output tile. // considered to be big enough to hold input tiles for one output tile.
// In future versions, scratchpad size should be fixed to an appropriate value. // In future versions, scratchpad size should be fixed to an appropriate value.
, scratchpad(std::vector<Word>(32 * 32 * 32768)) , scratchpad(std::vector<Word>(32 * 32 * 32768))
#ifdef EXT_V_ENABLE
, csrs_(arch.num_warps()) , csrs_(arch.num_warps())
#endif
{ {
std::srand(50); std::srand(50);
#ifdef EXT_V_ENABLE
for (uint32_t i = 0; i < arch_.num_warps(); ++i) { for (uint32_t i = 0; i < arch_.num_warps(); ++i) {
csrs_.at(i).resize(arch.num_threads()); csrs_.at(i).resize(arch.num_threads());
} }
#endif
this->clear(); this->clear();
} }
@ -480,6 +490,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
case VX_CSR_FRM: return (warps_.at(wid).fcsr >> 5); case VX_CSR_FRM: return (warps_.at(wid).fcsr >> 5);
case VX_CSR_FCSR: return warps_.at(wid).fcsr; case VX_CSR_FCSR: return warps_.at(wid).fcsr;
#ifdef EXT_V_ENABLE
// Vector CRSs // Vector CRSs
case VX_CSR_VSTART: case VX_CSR_VSTART:
return csrs_.at(wid).at(tid)[VX_CSR_VSTART]; return csrs_.at(wid).at(tid)[VX_CSR_VSTART];
@ -504,6 +515,7 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
return csrs_.at(wid).at(tid)[VX_CSR_VTIME]; return csrs_.at(wid).at(tid)[VX_CSR_VTIME];
case VX_CSR_VINSTRET: case VX_CSR_VINSTRET:
return csrs_.at(wid).at(tid)[VX_CSR_VINSTRET]; return csrs_.at(wid).at(tid)[VX_CSR_VINSTRET];
#endif
case VX_CSR_MHARTID: return (core_->id() * arch_.num_warps() + wid) * arch_.num_threads() + tid; case VX_CSR_MHARTID: return (core_->id() * arch_.num_warps() + wid) * arch_.num_threads() + tid;
case VX_CSR_THREAD_ID: return tid; case VX_CSR_THREAD_ID: return tid;
@ -621,6 +633,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
csr_mscratch_ = value; csr_mscratch_ = value;
break; break;
#ifdef EXT_V_ENABLE
// Vector CRSs // Vector CRSs
case VX_CSR_VSTART: case VX_CSR_VSTART:
csrs_.at(wid).at(tid)[VX_CSR_VSTART] = value; csrs_.at(wid).at(tid)[VX_CSR_VSTART] = value;
@ -642,6 +655,7 @@ void Emulator::set_csr(uint32_t addr, Word value, uint32_t tid, uint32_t wid) {
csrs_.at(wid).at(tid)[VX_CSR_VTYPE] = value; csrs_.at(wid).at(tid)[VX_CSR_VTYPE] = value;
break; break;
case VX_CSR_VLENB: // read only, set to VLEN / 8 case VX_CSR_VLENB: // read only, set to VLEN / 8
#endif
case VX_CSR_SATP: case VX_CSR_SATP:
#ifdef VM_ENABLE #ifdef VM_ENABLE

8
sim/simx/emulator.h
View file

@ -81,6 +81,7 @@ private:
bool fallthrough; bool fallthrough;
}; };
#ifdef EXT_V_ENABLE
struct vtype_t { struct vtype_t {
uint32_t vill; uint32_t vill;
uint32_t vma; uint32_t vma;
@ -88,6 +89,7 @@ private:
uint32_t vsew; uint32_t vsew;
uint32_t vlmul; uint32_t vlmul;
}; };
#endif
union reg_data_t { union reg_data_t {
Word u; Word u;
@ -109,12 +111,14 @@ private:
ThreadMask tmask; ThreadMask tmask;
std::vector<std::vector<Word>> ireg_file; std::vector<std::vector<Word>> ireg_file;
std::vector<std::vector<uint64_t>>freg_file; std::vector<std::vector<uint64_t>>freg_file;
std::vector<std::vector<Byte>> vreg_file;
std::stack<ipdom_entry_t> ipdom_stack; std::stack<ipdom_entry_t> ipdom_stack;
Byte fcsr; Byte fcsr;
#ifdef EXT_V_ENABLE
std::vector<std::vector<Byte>> vreg_file;
vtype_t vtype; vtype_t vtype;
uint32_t vl; uint32_t vl;
Word vlmax; Word vlmax;
#endif
uint32_t uuid; uint32_t uuid;
}; };
@ -173,7 +177,9 @@ private:
uint32_t mat_size; uint32_t mat_size;
uint32_t tc_size; uint32_t tc_size;
uint32_t tc_num; uint32_t tc_num;
#ifdef EXT_V_ENABLE
std::vector<std::vector<std::unordered_map<uint32_t, uint32_t>>> csrs_; std::vector<std::vector<std::unordered_map<uint32_t, uint32_t>>> csrs_;
#endif
}; };
} }

22
sim/simx/execute.cpp
View file

@ -25,7 +25,9 @@
#include "emulator.h" #include "emulator.h"
#include "instr.h" #include "instr.h"
#include "core.h" #include "core.h"
#ifdef EXT_V_ENABLE
#include "processor_impl.h" #include "processor_impl.h"
#endif
#include "VX_types.h" #include "VX_types.h"
using namespace vortex; using namespace vortex;
@ -117,8 +119,10 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
} }
DPN(2, "}" << std::endl); DPN(2, "}" << std::endl);
break; break;
#ifdef EXT_V_ENABLE
case RegType::Vector: case RegType::Vector:
break; break;
#endif
default: default:
break; break;
} }
@ -707,11 +711,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
} }
} }
rd_write = true; rd_write = true;
} else {
#ifdef EXT_V_ENABLE
this->loadVector(instr, wid, rsdata);
#endif
} }
#ifdef EXT_V_ENABLE
else {
this->loadVector(instr, wid, rsdata);
}
#endif
break; break;
} }
case Opcode::S: case Opcode::S:
@ -744,11 +749,12 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
std::abort(); std::abort();
} }
} }
} else {
#ifdef EXT_V_ENABLE
this->storeVector(instr, wid, rsdata);
#endif
} }
#ifdef EXT_V_ENABLE
else {
this->storeVector(instr, wid, rsdata);
}
#endif
break; break;
} }
case Opcode::AMO: { case Opcode::AMO: {

25
sim/simx/instr.h
View file

@ -42,8 +42,10 @@ enum class Opcode {
// RV64 Standard Extension // RV64 Standard Extension
R_W = 0x3b, R_W = 0x3b,
I_W = 0x1b, I_W = 0x1b,
#ifdef EXT_V_ENABLE
// Vector Extension // Vector Extension
VSET = 0x57, VSET = 0x57,
#endif
// Custom Extensions // Custom Extensions
EXT1 = 0x0b, EXT1 = 0x0b,
EXT2 = 0x2b, EXT2 = 0x2b,
@ -58,7 +60,9 @@ enum class InstType {
B, B,
U, U,
J, J,
#ifdef EXT_V_ENABLE
V, V,
#endif
R4 R4
}; };
@ -138,6 +142,7 @@ public:
, rdest_(0) , rdest_(0)
, func2_(0) , func2_(0)
, func3_(0) , func3_(0)
#ifdef EXT_V_ENABLE
, func6_(0) , func6_(0)
, func7_(0) , func7_(0)
, vmask_(0) , vmask_(0)
@ -152,8 +157,9 @@ public:
, vta_(0) , vta_(0)
, vma_(0) , vma_(0)
, vediv_(0) , vediv_(0)
, vattr_mask_(0) { , vattr_mask_(0)
for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) { #endif
{ for (uint32_t i = 0; i < MAX_REG_SOURCES; ++i) {
rsrc_type_[i] = RegType::None; rsrc_type_[i] = RegType::None;
rsrc_[i] = 0; rsrc_[i] = 0;
} }
@ -183,9 +189,11 @@ public:
void setImm(uint32_t imm) { has_imm_ = true; imm_ = imm; } void setImm(uint32_t imm) { has_imm_ = true; imm_ = imm; }
void setFunc2(uint32_t func2) { func2_ = func2; } void setFunc2(uint32_t func2) { func2_ = func2; }
void setFunc7(uint32_t func7) { func7_ = func7; }
#ifdef EXT_V_ENABLE
void setFunc3(uint32_t func3) { func3_ = func3; } void setFunc3(uint32_t func3) { func3_ = func3; }
void setFunc6(uint32_t func6) { func6_ = func6; } void setFunc6(uint32_t func6) { func6_ = func6; }
void setFunc7(uint32_t func7) { func7_ = func7; }
// Attributes for Vector instructions // Attributes for Vector instructions
void setVlsWidth(uint32_t width) { vlsWidth_ = width; vattr_mask_ |= vattr_vlswidth; } void setVlsWidth(uint32_t width) { vlsWidth_ = width; vattr_mask_ |= vattr_vlswidth; }
@ -200,6 +208,7 @@ public:
void setVta(uint32_t vta) { vta_ = vta; vattr_mask_ |= vattr_vta; } void setVta(uint32_t vta) { vta_ = vta; vattr_mask_ |= vattr_vta; }
void setVma(uint32_t vma) { vma_ = vma; vattr_mask_ |= vattr_vma; } void setVma(uint32_t vma) { vma_ = vma; vattr_mask_ |= vattr_vma; }
void setVediv(uint32_t ediv) { vediv_ = 1 << ediv; vattr_mask_ |= vattr_vediv; } void setVediv(uint32_t ediv) { vediv_ = 1 << ediv; vattr_mask_ |= vattr_vediv; }
#endif
Opcode getOpcode() const { return opcode_; } Opcode getOpcode() const { return opcode_; }
@ -215,9 +224,11 @@ public:
uint32_t getFunc2() const { return func2_; } uint32_t getFunc2() const { return func2_; }
uint32_t getFunc3() const { return func3_; } uint32_t getFunc3() const { return func3_; }
uint32_t getFunc6() const { return func6_; }
uint32_t getFunc7() const { return func7_; } uint32_t getFunc7() const { return func7_; }
#ifdef EXT_V_ENABLE
uint32_t getFunc6() const { return func6_; }
uint32_t getVlsWidth() const { return vlsWidth_; } uint32_t getVlsWidth() const { return vlsWidth_; }
uint32_t getVmop() const { return vMop_; } uint32_t getVmop() const { return vMop_; }
uint32_t getVumop() const { return vUmop_; } uint32_t getVumop() const { return vUmop_; }
@ -231,6 +242,7 @@ public:
uint32_t getVma() const { return vma_; } uint32_t getVma() const { return vma_; }
uint32_t getVediv() const { return vediv_; } uint32_t getVediv() const { return vediv_; }
uint32_t getVattrMask() const { return vattr_mask_; } uint32_t getVattrMask() const { return vattr_mask_; }
#endif
private: private:
@ -248,9 +260,11 @@ private:
uint32_t rdest_; uint32_t rdest_;
uint32_t func2_; uint32_t func2_;
uint32_t func3_; uint32_t func3_;
uint32_t func6_;
uint32_t func7_; uint32_t func7_;
#ifdef EXT_V_ENABLE
uint32_t func6_;
// Vector // Vector
uint32_t vmask_; uint32_t vmask_;
uint32_t vlsWidth_; uint32_t vlsWidth_;
@ -265,6 +279,7 @@ private:
uint32_t vma_; uint32_t vma_;
uint32_t vediv_; uint32_t vediv_;
uint32_t vattr_mask_; uint32_t vattr_mask_;
#endif
friend std::ostream &operator<<(std::ostream &, const Instr&); friend std::ostream &operator<<(std::ostream &, const Instr&);
}; };

2
sim/simx/main.cpp
View file

@ -120,7 +120,9 @@ int main(int argc, char **argv) {
#endif #endif
// run simulation // run simulation
// vector test exitcode is a special case // vector test exitcode is a special case
#ifdef EXT_V_ENABLE
if (vector_test) return processor.run(); if (vector_test) return processor.run();
#endif
// else continue as normal // else continue as normal
processor.run(); processor.run();

2
sim/simx/processor.cpp
View file

@ -127,7 +127,9 @@ int ProcessorImpl::run() {
done = false; done = false;
continue; continue;
} }
#ifdef EXT_V_ENABLE
exitcode |= cluster->get_exitcode(); exitcode |= cluster->get_exitcode();
#endif
} }
perf_mem_latency_ += perf_mem_pending_reads_; perf_mem_latency_ += perf_mem_pending_reads_;
} while (!done); } while (!done);

8
sim/simx/types.h
View file

@ -84,8 +84,10 @@ enum class RegType {
None, None,
Integer, Integer,
Float, Float,
Count, #ifdef EXT_V_ENABLE
Vector Vector,
#endif
Count
}; };
inline std::ostream &operator<<(std::ostream &os, const RegType& type) { inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
@ -93,7 +95,9 @@ inline std::ostream &operator<<(std::ostream &os, const RegType& type) {
case RegType::None: break; case RegType::None: break;
case RegType::Integer: os << "x"; break; case RegType::Integer: os << "x"; break;
case RegType::Float: os << "f"; break; case RegType::Float: os << "f"; break;
#ifdef EXT_V_ENABLE
case RegType::Vector: os << "v"; break; case RegType::Vector: os << "v"; break;
#endif
default: assert(false); default: assert(false);
} }
return os; return os;

2
sim/simx/vpu.cpp
View file

@ -2,6 +2,7 @@
// The purpose of this fork is to make simx-v2-vector up to date with master // The purpose of this fork is to make simx-v2-vector up to date with master
// Thanks to Troibe for his amazing work // Thanks to Troibe for his amazing work
#ifdef EXT_V_ENABLE
#include "emulator.h" #include "emulator.h"
#include "instr.h" #include "instr.h"
#include "processor_impl.h" #include "processor_impl.h"
@ -2477,3 +2478,4 @@ void Emulator::executeVector(const Instr &instr, uint32_t wid, std::vector<reg_d
std::abort(); std::abort();
} }
} }
#endif

2
sim/simx/vpu.h
View file

@ -1,3 +1,4 @@
#ifdef EXT_V_ENABLE
#pragma once #pragma once
using namespace vortex; using namespace vortex;
@ -2389,3 +2390,4 @@ void vector_op_vv_compress(std::vector<std::vector<Byte>> &vreg_file, uint32_t r
std::abort(); std::abort();
} }
} }
#endif