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Using verilog For-loops + Passing all tests

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This commit is contained in:
felsabbagh3 2019-03-30 22:09:03 -04:00
parent 99a0792a0c
commit a3a3b21de7
17 changed files with 1204 additions and 984 deletions
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7
rtl/VX_alu.v
View file

@ -2,7 +2,8 @@
`include "VX_define.v"
module VX_alu(
input wire[31:0] in_reg_data[1:0],
input wire[31:0] in_1,
input wire[31:0] in_2,
input wire in_rs2_src,
input wire[31:0] in_itype_immed,
input wire[19:0] in_upper_immed,
@ -22,9 +23,9 @@ module VX_alu(
assign which_in2 = in_rs2_src == `RS2_IMMED;
assign ALU_in1 = in_reg_data[0];
assign ALU_in1 = in_1;
assign ALU_in2 = which_in2 ? in_itype_immed : in_reg_data[1];
assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
assign upper_immed = {in_upper_immed, {12{1'b0}}};

26
rtl/VX_d_e_reg.v
View file

@ -7,7 +7,8 @@ module VX_d_e_reg (
input wire[4:0] in_rd,
input wire[4:0] in_rs1,
input wire[4:0] in_rs2,
input wire[31:0] in_reg_data[`NT_T2_M1:0],
input wire[31:0] in_a_reg_data[`NT_M1:0],
input wire[31:0] in_b_reg_data[`NT_M1:0],
input wire[4:0] in_alu_op,
input wire[1:0] in_wb,
input wire in_rs2_src, // NEW
@ -34,7 +35,8 @@ module VX_d_e_reg (
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[`NT_T2_M1:0],
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[4:0] out_alu_op,
output wire[1:0] out_wb,
output wire out_rs2_src, // NEW
@ -54,7 +56,8 @@ module VX_d_e_reg (
reg[4:0] rd;
reg[4:0] rs1;
reg[4:0] rs2;
reg[31:0] reg_data[`NT_T2_M1:0];
reg[31:0] a_reg_data[`NT_M1:0];
reg[31:0] b_reg_data[`NT_M1:0];
reg[4:0] alu_op;
reg[1:0] wb;
reg[31:0] PC_next_out;
@ -72,7 +75,7 @@ module VX_d_e_reg (
reg[31:0] jal_offset;
reg valid[`NT_M1:0];
reg[31:0] reg_data_z[`NT_T2_M1:0];
reg[31:0] reg_data_z[`NT_M1:0];
reg valid_z[`NT_M1:0];
integer ini_reg;
@ -81,10 +84,11 @@ module VX_d_e_reg (
rs1 = 0;
for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
begin
reg_data[ini_reg] = 0;
reg_data_z[ini_reg] = 0;
valid[ini_reg] = 0;
valid_z[ini_reg] = 0;
a_reg_data[ini_reg] = 0;
b_reg_data[ini_reg] = 0;
reg_data_z[ini_reg] = 0;
valid[ini_reg] = 0;
valid_z[ini_reg] = 0;
end
rs2 = 0;
alu_op = 0;
@ -111,7 +115,8 @@ module VX_d_e_reg (
assign out_rd = rd;
assign out_rs1 = rs1;
assign out_rs2 = rs2;
assign out_reg_data = reg_data;
assign out_a_reg_data = a_reg_data;
assign out_b_reg_data = b_reg_data;
assign out_alu_op = alu_op;
assign out_wb = wb;
assign out_PC_next = PC_next_out;
@ -135,7 +140,8 @@ module VX_d_e_reg (
rd <= stalling ? 5'h0 : in_rd;
rs1 <= stalling ? 5'h0 : in_rs1;
rs2 <= stalling ? 5'h0 : in_rs2;
reg_data <= stalling ? reg_data_z : in_reg_data;
a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
alu_op <= stalling ? `NO_ALU : in_alu_op;
wb <= stalling ? `NO_WB : in_wb;
PC_next_out <= stalling ? 32'h0 : in_PC_next;

13
rtl/VX_decode.v
View file

@ -27,7 +27,8 @@ module VX_decode(
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[`NT_T2_M1:0],
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[1:0] out_wb,
output wire[4:0] out_alu_op,
output wire out_rs2_src,
@ -212,13 +213,11 @@ module VX_decode(
// ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction);
genvar index_out_reg;
genvar index_out_reg_2;
generate
for (index_out_reg = 0; index_out_reg <= `NT; index_out_reg = index_out_reg + 2)
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign index_out_reg_2 = index_out_reg / 2;
assign out_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg_2] : rd1_register[index_out_reg_2]));
assign out_reg_data[index_out_reg+1] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg_2] : rd2_register[index_out_reg_2];
assign out_a_reg_data[index_out_reg] = ( (is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
@ -244,7 +243,7 @@ module VX_decode(
// end
assign out_is_csr = is_csr;
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_reg_data[0];
assign out_csr_mask = (is_csr_immed == 1'b1) ? {27'h0, out_rs1} : out_a_reg_data[0];
assign out_wb = (is_jal || is_jalr || is_e_inst) ? `WB_JAL :

22
rtl/VX_e_m_reg.v
View file

@ -10,7 +10,8 @@ module VX_e_m_reg (
input wire[1:0] in_wb,
input wire[4:0] in_rs1,
input wire[4:0] in_rs2,
input wire[31:0] in_reg_data[`NT_T2_M1:0],
input wire[31:0] in_a_reg_data[`NT_M1:0],
input wire[31:0] in_b_reg_data[`NT_M1:0],
input wire[2:0] in_mem_read, // NEW
input wire[2:0] in_mem_write, // NEW
input wire[31:0] in_PC_next,
@ -33,7 +34,8 @@ module VX_e_m_reg (
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[`NT_T2_M1:0],
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output wire[31:0] out_curr_PC,
@ -50,7 +52,8 @@ module VX_e_m_reg (
reg[4:0] rd;
reg[4:0] rs1;
reg[4:0] rs2;
reg[31:0] reg_data[`NT_T2_M1:0];
reg[31:0] a_reg_data[`NT_M1:0];
reg[31:0] b_reg_data[`NT_M1:0];
reg[1:0] wb;
reg[31:0] PC_next;
reg[2:0] mem_read;
@ -87,13 +90,12 @@ module VX_e_m_reg (
branch_type = 0;
jal = `NO_JUMP;
jal_dest = 0;
for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
begin
reg_data[ini_reg] = 0;
// reg_data_z[ini_reg] = 0;
a_reg_data[ini_reg] = 0;
b_reg_data[ini_reg] = 0;
valid[ini_reg] = 0;
// valid_z[ini_reg] = 0;
// alu_result_z[ini_reg] = 0;
alu_result[ini_reg] = 0;
end
end
@ -108,7 +110,8 @@ module VX_e_m_reg (
assign out_PC_next = PC_next;
assign out_mem_read = mem_read;
assign out_mem_write = mem_write;
assign out_reg_data = reg_data;
assign out_a_reg_data = a_reg_data;
assign out_b_reg_data = b_reg_data;
assign out_csr_address = csr_address;
assign out_is_csr = is_csr;
assign out_csr_result = csr_result;
@ -130,7 +133,8 @@ module VX_e_m_reg (
PC_next <= in_PC_next;
mem_read <= in_mem_read;
mem_write <= in_mem_write;
reg_data <= in_reg_data;
a_reg_data <= in_a_reg_data;
b_reg_data <= in_b_reg_data;
csr_address <= in_csr_address;
is_csr <= in_is_csr;
csr_result <= in_csr_result;

46
rtl/VX_execute.v
View file

@ -5,7 +5,8 @@ module VX_execute (
input wire[4:0] in_rd,
input wire[4:0] in_rs1,
input wire[4:0] in_rs2,
input wire[31:0] in_reg_data[`NT_T2_M1:0],
input wire[31:0] in_a_reg_data[`NT_M1:0],
input wire[31:0] in_b_reg_data[`NT_M1:0],
input wire[4:0] in_alu_op,
input wire[1:0] in_wb,
input wire in_rs2_src, // NEW
@ -32,7 +33,8 @@ module VX_execute (
output wire[1:0] out_wb,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_reg_data[`NT_T2_M1:0],
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output wire out_jal,
@ -57,28 +59,46 @@ module VX_execute (
// );
// genvar index;
// genvar index_2;
// reg[5:0] index_2;
// generate
// assign index_2 = 0;
// for (index=0; index <= `NT; index=index+2)
// for (index=0; index < `NT; index=index+1)
// begin: gen_code_label
// assign index_2 = index * 2;
// VX_alu vx_alu(
// .in_reg_data (in_reg_data[index+1:index]),
// .in_reg_data (in_reg_data[(index_2+1):(index_2)]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index_2])
// .out_alu_result(out_alu_result[index])
// );
// index_2 = index_2 + 1;
// end
// endgenerate
// genvar index_out_reg;
// generate
// for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
// begin
// VX_alu vx_alu_0(
// // .in_reg_data (in_reg_data[1:0]),
// .in_1 (in_a_reg_data[index_out_reg]),
// .in_2 (in_b_reg_data[index_out_reg]),
// .in_rs2_src (in_rs2_src),
// .in_itype_immed(in_itype_immed),
// .in_upper_immed(in_upper_immed),
// .in_alu_op (in_alu_op),
// .in_csr_data (in_csr_data),
// .in_curr_PC (in_curr_PC),
// .out_alu_result(out_alu_result[index_out_reg])
// );
// end
// endgenerate
VX_alu vx_alu_0(
.in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[0]),
.in_2 (in_b_reg_data[0]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
@ -89,7 +109,8 @@ module VX_execute (
);
VX_alu vx_alu_1(
.in_reg_data (in_reg_data[3:2]),
.in_1 (in_a_reg_data[1]),
.in_2 (in_b_reg_data[1]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
@ -99,7 +120,7 @@ module VX_execute (
.out_alu_result(out_alu_result[1])
);
assign out_jal_dest = $signed(in_reg_data[0]) + $signed(in_jal_offset);
assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal;
always @(*) begin
@ -125,7 +146,8 @@ module VX_execute (
assign out_mem_read = in_mem_read;
assign out_mem_write = in_mem_write;
assign out_rs1 = in_rs1;
assign out_reg_data = in_reg_data;
assign out_a_reg_data = in_a_reg_data;
assign out_b_reg_data = in_b_reg_data;
assign out_rs2 = in_rs2;
assign out_PC_next = in_PC_next;
assign out_is_csr = in_is_csr;

2
rtl/VX_memory.v
View file

@ -38,7 +38,7 @@ module VX_memory (
always @(in_mem_read, in_cache_driver_out_data) begin
if (in_mem_read == `LW_MEM_READ) begin
// $display("PC: %h ----> Received: %h", in_curr_PC, in_cache_driver_out_data);
$display("PC: %h ----> Received: %h for addr: ", in_curr_PC, in_cache_driver_out_data[0], in_alu_result[0]);
end
end

58
rtl/Vortex.v
View file

@ -5,8 +5,9 @@ module Vortex(
input wire clk,
input wire reset,
input wire[31:0] fe_instruction,
input wire[31:0] in_cache_driver_out_data_0,
input wire[31:0] in_cache_driver_out_data_1,
// input wire[31:0] in_cache_driver_out_data_0,
// input wire[31:0] in_cache_driver_out_data_1,
input wire[31:0] in_cache_driver_out_data[`NT_M1:0],
output wire[31:0] curr_PC,
output wire[31:0] out_cache_driver_in_address[`NT_M1:0],
output wire[2:0] out_cache_driver_in_mem_read,
@ -15,10 +16,10 @@ module Vortex(
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
);
wire[31:0] in_cache_driver_out_data[`NT_M1:0];
// wire[31:0] in_cache_driver_out_data[`NT_M1:0];
assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
// assign in_cache_driver_out_data[0] = in_cache_driver_out_data_0;
// assign in_cache_driver_out_data[1] = in_cache_driver_out_data_1;
assign curr_PC = fetch_curr_PC;
@ -42,7 +43,8 @@ wire[31:0] decode_csr_mask;
wire[4:0] decode_rd;
wire[4:0] decode_rs1;
wire[4:0] decode_rs2;
wire[31:0] decode_reg_data[`NT_T2_M1:0];
wire[31:0] decode_a_reg_data[`NT_M1:0];
wire[31:0] decode_b_reg_data[`NT_M1:0];
wire[1:0] decode_wb;
wire[4:0] decode_alu_op;
wire decode_rs2_src;
@ -63,7 +65,8 @@ wire[31:0] d_e_csr_mask;
wire[4:0] d_e_rd;
wire[4:0] d_e_rs1;
wire[4:0] d_e_rs2;
wire[31:0] d_e_reg_data[`NT_T2_M1:0];
wire[31:0] d_e_a_reg_data[`NT_M1:0];
wire[31:0] d_e_b_reg_data[`NT_M1:0];
wire[4:0] d_e_alu_op;
wire[1:0] d_e_wb;
wire d_e_rs2_src;
@ -89,14 +92,15 @@ wire[4:0] execute_rd;
wire[1:0] execute_wb;
wire[4:0] execute_rs1;
wire[4:0] execute_rs2;
wire[31:0] execute_reg_data[`NT_T2_M1:0];
wire[31:0] execute_a_reg_data[`NT_M1:0];
wire[31:0] execute_b_reg_data[`NT_M1:0];
wire[2:0] execute_mem_read;
wire[2:0] execute_mem_write;
wire execute_jal;
wire[31:0] execute_jal_dest;
wire[31:0] execute_branch_offset;
wire[31:0] execute_PC_next;
wire execute_valid[`NT_M1:0];
wire execute_valid[`NT_M1:0];
// From e_m_register
@ -110,8 +114,9 @@ wire[4:0] e_m_rd;
wire[1:0] e_m_wb;
wire[4:0] e_m_rs1;
/* verilator lint_off UNUSED */
wire[31:0] e_m_reg_data[`NT_T2_M1:0];
wire[31:0] e_m_a_reg_data[`NT_M1:0];
/* verilator lint_on UNUSED */
wire[31:0] e_m_b_reg_data[`NT_M1:0];
wire[4:0] e_m_rs2;
wire[2:0] e_m_mem_read;
wire[2:0] e_m_mem_write;
@ -119,7 +124,7 @@ wire[31:0] e_m_curr_PC;
wire[31:0] e_m_branch_offset;
wire[2:0] e_m_branch_type;
wire[31:0] e_m_PC_next;
wire e_m_valid[`NT_M1:0];
wire e_m_valid[`NT_M1:0];
// From memory
@ -133,7 +138,7 @@ wire[1:0] memory_wb;
wire[4:0] memory_rs1;
wire[4:0] memory_rs2;
wire[31:0] memory_PC_next;
wire memory_valid[`NT_M1:0];
wire memory_valid[`NT_M1:0];
// From m_w_register
wire[31:0] m_w_alu_result[`NT_M1:0];
@ -235,7 +240,8 @@ VX_decode vx_decode(
.out_rd (decode_rd),
.out_rs1 (decode_rs1),
.out_rs2 (decode_rs2),
.out_reg_data (decode_reg_data),
.out_a_reg_data (decode_a_reg_data),
.out_b_reg_data (decode_b_reg_data),
.out_wb (decode_wb),
.out_alu_op (decode_alu_op),
.out_rs2_src (decode_rs2_src),
@ -257,7 +263,8 @@ VX_d_e_reg vx_d_e_reg(
.in_rd (decode_rd),
.in_rs1 (decode_rs1),
.in_rs2 (decode_rs2),
.in_reg_data (decode_reg_data),
.in_a_reg_data (decode_a_reg_data),
.in_b_reg_data (decode_b_reg_data),
.in_alu_op (decode_alu_op),
.in_wb (decode_wb),
.in_rs2_src (decode_rs2_src),
@ -284,7 +291,8 @@ VX_d_e_reg vx_d_e_reg(
.out_rd (d_e_rd),
.out_rs1 (d_e_rs1),
.out_rs2 (d_e_rs2),
.out_reg_data (d_e_reg_data),
.out_a_reg_data (d_e_a_reg_data),
.out_b_reg_data (d_e_b_reg_data),
.out_alu_op (d_e_alu_op),
.out_wb (d_e_wb),
.out_rs2_src (d_e_rs2_src),
@ -304,7 +312,8 @@ VX_execute vx_execute(
.in_rd (d_e_rd),
.in_rs1 (d_e_rs1),
.in_rs2 (d_e_rs2),
.in_reg_data (d_e_reg_data),
.in_a_reg_data (d_e_a_reg_data),
.in_b_reg_data (d_e_b_reg_data),
.in_alu_op (d_e_alu_op),
.in_wb (d_e_wb),
.in_rs2_src (d_e_rs2_src),
@ -331,7 +340,8 @@ VX_execute vx_execute(
.out_wb (execute_wb),
.out_rs1 (execute_rs1),
.out_rs2 (execute_rs2),
.out_reg_data (execute_reg_data),
.out_a_reg_data (execute_a_reg_data),
.out_b_reg_data (execute_b_reg_data),
.out_mem_read (execute_mem_read),
.out_mem_write (execute_mem_write),
.out_jal (execute_jal),
@ -349,7 +359,8 @@ VX_e_m_reg vx_e_m_reg(
.in_wb (execute_wb),
.in_rs1 (execute_rs1),
.in_rs2 (execute_rs2),
.in_reg_data (execute_reg_data),
.in_a_reg_data (execute_a_reg_data),
.in_b_reg_data (execute_b_reg_data),
.in_mem_read (execute_mem_read),
.in_mem_write (execute_mem_write),
.in_PC_next (execute_PC_next),
@ -372,7 +383,8 @@ VX_e_m_reg vx_e_m_reg(
.out_wb (e_m_wb),
.out_rs1 (e_m_rs1),
.out_rs2 (e_m_rs2),
.out_reg_data (e_m_reg_data),
.out_a_reg_data (e_m_a_reg_data),
.out_b_reg_data (e_m_b_reg_data),
.out_mem_read (e_m_mem_read),
.out_mem_write (e_m_mem_write),
.out_curr_PC (e_m_curr_PC),
@ -384,10 +396,10 @@ VX_e_m_reg vx_e_m_reg(
.out_valid (e_m_valid)
);
wire[31:0] use_rd2[`NT_M1:0];
// wire[31:0] use_rd2[`NT_M1:0];
assign use_rd2[0] = e_m_reg_data[1];
assign use_rd2[1] = e_m_reg_data[3];
// assign use_rd2[0] = e_m_reg_data[1];
// assign use_rd2[1] = e_m_reg_data[3];
VX_memory vx_memory(
.in_alu_result (e_m_alu_result),
@ -397,7 +409,7 @@ VX_memory vx_memory(
.in_wb (e_m_wb),
.in_rs1 (e_m_rs1),
.in_rs2 (e_m_rs2),
.in_rd2 (use_rd2),
.in_rd2 (e_m_b_reg_data),
.in_PC_next (e_m_PC_next),
.in_curr_PC (e_m_curr_PC),
.in_branch_offset (e_m_branch_offset),

BIN
rtl/obj_dir/VVortex
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1281
rtl/obj_dir/VVortex.cpp
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164
rtl/obj_dir/VVortex.h
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@ -26,9 +26,8 @@ VL_MODULE(VVortex) {
VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_IN(fe_instruction,31,0);
VL_IN(in_cache_driver_out_data_0,31,0);
VL_IN(in_cache_driver_out_data_1,31,0);
VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[2],31,0);
VL_OUT(out_cache_driver_in_address[2],31,0);
VL_OUT8(out_cache_driver_in_valid[2],0,0);
VL_OUT(out_cache_driver_in_data[2],31,0);
@ -115,18 +114,19 @@ VL_MODULE(VVortex) {
VL_SIG64(Vortex__DOT__vx_execute__DOT__vx_alu_1__DOT__mult_signed_result,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__cycle,63,0);
VL_SIG64(Vortex__DOT__vx_csr_handler__DOT__instret,63,0);
VL_SIG(Vortex__DOT__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT__fetch_valid[2],0,0);
VL_SIG8(Vortex__DOT__f_d_valid[2],0,0);
VL_SIG(Vortex__DOT__decode_reg_data[4],31,0);
VL_SIG(Vortex__DOT__decode_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__decode_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__decode_valid[2],0,0);
VL_SIG(Vortex__DOT__d_e_reg_data[4],31,0);
VL_SIG(Vortex__DOT__d_e_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__d_e_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__d_e_valid[2],0,0);
VL_SIG(Vortex__DOT__execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__execute_reg_data[4],31,0);
VL_SIG(Vortex__DOT__execute_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__execute_valid[2],0,0);
VL_SIG(Vortex__DOT__e_m_alu_result[2],31,0);
VL_SIG(Vortex__DOT__e_m_reg_data[4],31,0);
VL_SIG(Vortex__DOT__e_m_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__e_m_valid[2],0,0);
VL_SIG(Vortex__DOT__memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT__memory_mem_result[2],31,0);
@ -137,18 +137,19 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__use_rd2[2],31,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_0__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__vx_register_file_1__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data[4],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[4],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__reg_data_z[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid_z[2],0,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__reg_data[4],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_e_m_reg__DOT__b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_e_m_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_m_w_reg__DOT__mem_result[2],31,0);
@ -162,70 +163,77 @@ VL_MODULE(VVortex) {
// LOCAL VARIABLES
// Internals; generally not touched by application code
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_reg_data[4],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_reg_data[4],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_0__in_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellinp__vx_alu_1__in_reg_data[2],31,0);
// Anonymous structures to workaround compiler member-count bugs
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_0__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__vx_register_file_1__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_0__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__vx_alu_1__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_f_d_reg__out_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_f_d_reg__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_decode__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_decode__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_wb_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_decode__in_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_decode__in_valid[2],0,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_d_e_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_d_e_reg__out_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_d_e_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_d_e_reg__in_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_execute__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_execute__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_execute__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_execute__in_a_reg_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_e_m_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_e_m_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_e_m_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_e_m_reg__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_cache_driver_in_address[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_memory__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_memory__out_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_cache_driver_out_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_memory__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_rd2[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_memory__in_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_m_w_reg__out_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_m_w_reg__out_alu_result[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_m_w_reg__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_m_w_reg__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_writeback__out_write_data[2],31,0);
VL_SIG8(Vortex__DOT____Vcellinp__vx_writeback__in_valid[2],0,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);
// INTERNAL VARIABLES
@ -260,7 +268,7 @@ VL_MODULE(VVortex) {
private:
static QData _change_request(VVortex__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _combo__TOP__9(VVortex__Syms* __restrict vlSymsp);
private:
void _ctor_var_reset();
@ -276,9 +284,9 @@ VL_MODULE(VVortex) {
static void _initial__TOP__6(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _sequent__TOP__7(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp);
static void _settle__TOP__8(VVortex__Syms* __restrict vlSymsp);
} VL_ATTR_ALIGNED(128);

BIN
rtl/obj_dir/VVortex__ALL.a
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BIN
rtl/obj_dir/VVortex__ALLcls.o
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30
rtl/obj_dir/VVortex__verFiles.dat
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@ -1,26 +1,26 @@
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "-Wall -cc Vortex.v VX_alu.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_d_e_reg.v VX_execute.v VX_e_m_reg.v VX_memory.v VX_m_w_reg.v VX_writeback.v VX_csr_handler.v VX_forwarding.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2869 12889318286 1553929158 0 1553929158 0 "VX_alu.v"
S 2862 12889318286 1553966962 0 1553966962 0 "VX_alu.v"
S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v"
S 4780 12889318287 1553672988 0 1553672988 0 "VX_d_e_reg.v"
S 11922 12889419225 1553929867 0 1553929867 0 "VX_decode.v"
S 5040 12889318287 1553995422 0 1553995422 0 "VX_d_e_reg.v"
S 11888 12889419225 1553995767 0 1553995767 0 "VX_decode.v"
S 1551 12889419227 1553898607 0 1553898607 0 "VX_define.v"
S 3941 12889318289 1553673060 0 1553673060 0 "VX_e_m_reg.v"
S 4044 12889318290 1553932436 0 1553932436 0 "VX_execute.v"
S 4077 12889318289 1553997299 0 1553997299 0 "VX_e_m_reg.v"
S 4908 12889318290 1553997136 0 1553997136 0 "VX_execute.v"
S 1382 12889050060 1553673124 0 1553673124 0 "VX_f_d_reg.v"
S 4048 12889419228 1553932280 0 1553932280 0 "VX_fetch.v"
S 5632 12889086478 1553672336 0 1553672336 0 "VX_forwarding.v"
S 1677 12889085814 1553673165 0 1553673165 0 "VX_m_w_reg.v"
S 2973 12889084513 1553931546 0 1553931546 0 "VX_memory.v"
S 3002 12889084513 1553997670 0 1553997670 0 "VX_memory.v"
S 1003 12889419229 1553930745 0 1553930745 0 "VX_register_file.v"
S 1173 12889419230 1553930874 0 1553930874 0 "VX_writeback.v"
S 15887 12889419231 1553932044 0 1553932044 0 "Vortex.v"
T 187461 12889423037 1553932439 0 1553932439 0 "obj_dir/VVortex.cpp"
T 14542 12889423036 1553932439 0 1553932439 0 "obj_dir/VVortex.h"
T 1800 12889423039 1553932439 0 1553932439 0 "obj_dir/VVortex.mk"
T 530 12889423035 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889423034 1553932439 0 1553932439 0 "obj_dir/VVortex__Syms.h"
T 464 12889423040 1553932439 0 1553932439 0 "obj_dir/VVortex__ver.d"
T 0 0 1553932439 0 1553932439 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889423038 1553932439 0 1553932439 0 "obj_dir/VVortex_classes.mk"
S 16452 12889419231 1553997933 0 1553997933 0 "Vortex.v"
T 183333 12889432530 1553998021 0 1553998021 0 "obj_dir/VVortex.cpp"
T 14673 12889432529 1553998021 0 1553998021 0 "obj_dir/VVortex.h"
T 1800 12889432532 1553998021 0 1553998021 0 "obj_dir/VVortex.mk"
T 530 12889432528 1553998021 0 1553998021 0 "obj_dir/VVortex__Syms.cpp"
T 717 12889432527 1553998021 0 1553998021 0 "obj_dir/VVortex__Syms.h"
T 464 12889432533 1553998021 0 1553998021 0 "obj_dir/VVortex__ver.d"
T 0 0 1553998021 0 1553998021 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12889432531 1553998021 0 1553998021 0 "obj_dir/VVortex_classes.mk"

506
rtl/obj_dir/debug.txt
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rtl/obj_dir/test_bench.o
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2
rtl/test_bench.cpp
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@ -78,7 +78,7 @@ int main(int argc, char **argv)
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-lw.hex";
// char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
// bool curr = v.simulate(testing);
// if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;

31
rtl/test_bench.h
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@ -206,52 +206,50 @@ bool Vortex::dbus_driver()
printf("----\n");
for (unsigned curr_th = 0; curr_th < NT; curr_th++)
{
unsigned & in_data_use = (curr_th == 0) ? vortex->in_cache_driver_out_data_0 : vortex->in_cache_driver_out_data_1;
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[0])
if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
{
addr = (uint32_t) vortex->out_cache_driver_in_address[1];
addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
ram.getWord(addr, &data_read);
if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
{
in_data_use = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
{
in_data_use = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
} else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
{
// printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
std::cout << std::dec;
in_data_use = data_read;
vortex->in_cache_driver_out_data[curr_th] = data_read;
} else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
{
in_data_use = (data_read & 0xFF);
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
} else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
{
in_data_use = (data_read & 0xFFFF);
vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
}
else
{
in_data_use = 0xbabebabe;
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
}
else
{
in_data_use = 0xbabebabe;
vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
}
}
@ -321,13 +319,16 @@ bool Vortex::simulate(std::string file_to_simulate)
// cycle++;
// }
bool istop;
bool dstop;
// for (int i = 0; i < 500; i++)
while (this->stop && (!(stop && (counter > 5))))
{
// std::cout << "************* Cycle: " << cycle << "\n";
bool istop = ibus_driver();
bool dstop = !dbus_driver();
istop = ibus_driver();
dstop = !dbus_driver();
vortex->clk = 1;
vortex->eval();