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critical path optimizations
This commit is contained in:
Blaise Tine
parent
b8fd2308e1
commit
a3a7239b4d
4 changed files with 287 additions and 60 deletions
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@ -97,6 +97,7 @@ module VX_ibuffer #(
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reg [DATAW-1:0] deq_instr, deq_instr_n;
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reg [NWARPSW-1:0] num_warps;
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// calculate valid table
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always @(*) begin
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valid_table_n = valid_table;
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if (deq_fire) begin
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@ -113,11 +114,10 @@ module VX_ibuffer #(
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deq_valid_n = 1;
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deq_wid_n = 'x;
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deq_instr_n = 'x;
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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for (integer i = `NUM_WARPS-1; i >= 0; --i) begin
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if (schedule_table[i]) begin
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deq_wid_n = `NW_BITS'(i);
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deq_wid_n = `NW_BITS'(i);
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deq_instr_n = q_data_out[i];
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break;
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end
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end
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end else if (1 == num_warps && !(deq_fire && q_alm_empty[deq_wid])) begin
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@ -130,16 +130,16 @@ module VX_ibuffer #(
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deq_instr_n = q_data_in;
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end
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end
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// do round-robin with multiple active warps
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// do round-robin scheduling with multiple active warps
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always @(*) begin
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schedule_table_n = schedule_table;
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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if (schedule_table[i]) begin
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schedule_table_n[i] = 0;
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break;
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end
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if (1 == $countones(schedule_table)
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|| (num_warps < 2)) begin
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schedule_table_n = valid_table_n;
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end else begin
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schedule_table_n = schedule_table;
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end
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schedule_table_n[deq_wid_n] = 0;
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end
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wire warp_added = enq_fire && q_empty[ibuf_enq_if.wid];
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@ -148,21 +148,12 @@ module VX_ibuffer #(
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always @(posedge clk) begin
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if (reset) begin
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valid_table <= 0;
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schedule_table <= 0;
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deq_valid <= 0;
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num_warps <= 0;
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end else begin
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valid_table <= valid_table_n;
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if (0 == (| schedule_table_n)
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|| (num_warps < 2)) begin
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schedule_table <= valid_table_n;
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schedule_table[deq_wid_n] <= 0;
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end else begin
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schedule_table <= schedule_table_n;
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end
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deq_valid <= deq_valid_n;
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valid_table <= valid_table_n;
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deq_valid <= deq_valid_n;
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schedule_table <= schedule_table_n;
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if (warp_added && !warp_removed) begin
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num_warps <= num_warps + NWARPSW'(1);
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@ -12,18 +12,11 @@ module VX_scoreboard #(
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);
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reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs;
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reg is_reg_busy;
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always @(*) begin
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is_reg_busy = 'x;
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for (integer i = 0; i < `NUM_WARPS; ++i) begin
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if (ibuf_deq_if.wid == `NW_BITS'(i)) begin
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is_reg_busy = | (inuse_regs[i] & ibuf_deq_if.used_regs);
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end
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end
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end
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assign delay = is_reg_busy;
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wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && (ibuf_deq_if.wb != 0);
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wire [`NUM_REGS-1:0] deq_inuse_regs = inuse_regs[ibuf_deq_if.wid];
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assign delay = | (deq_inuse_regs & ibuf_deq_if.used_regs);
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wire reserve_reg = ibuf_deq_if.valid && ibuf_deq_if.ready && ibuf_deq_if.wb;
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wire release_reg = writeback_if.valid && writeback_if.ready && writeback_if.eop;
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@ -43,8 +36,6 @@ module VX_scoreboard #(
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end
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end
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wire [`NUM_REGS-1:0] deq_inuse_regs = inuse_regs[ibuf_deq_if.wid];
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
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@ -4,8 +4,10 @@
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// Adapter from BaseJump STL: http://bjump.org/data_out.html
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module VX_onehot_encoder #(
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parameter N = 1,
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parameter LN = `LOG2UP(N)
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parameter N = 1,
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parameter REVERSE = 0,
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parameter FAST = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [LN-1:0] data_out,
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@ -18,14 +20,24 @@ module VX_onehot_encoder #(
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end else if (N == 2) begin
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assign data_out = data_in[1];
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assign data_out = data_in[!REVERSE];
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assign valid = (| data_in);
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end else begin
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end else if (N == 4) begin
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reg [LN-1:0] index_r;
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if (N == 4) begin
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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4'b1000: index_r = LN'(0);
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4'b?100: index_r = LN'(1);
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4'b??10: index_r = LN'(2);
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4'b???1: index_r = LN'(3);
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default: index_r = 'x;
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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4'b0001: index_r = LN'(0);
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@ -35,7 +47,30 @@ module VX_onehot_encoder #(
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default: index_r = 'x;
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endcase
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end
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end else if (N == 8) begin
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end
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assign data_out = index_r;
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assign valid = (| data_in);
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end else if (N == 8) begin
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reg [LN-1:0] index_r;
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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8'b10000000: index_r = LN'(0);
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8'b?1000000: index_r = LN'(1);
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8'b??100000: index_r = LN'(2);
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8'b???10000: index_r = LN'(3);
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8'b????1000: index_r = LN'(4);
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8'b?????100: index_r = LN'(5);
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8'b??????10: index_r = LN'(6);
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8'b???????1: index_r = LN'(7);
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default: index_r = 'x;
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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8'b00000001: index_r = LN'(0);
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@ -49,7 +84,38 @@ module VX_onehot_encoder #(
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default: index_r = 'x;
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endcase
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end
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end else if (N == 16) begin
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end
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assign data_out = index_r;
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assign valid = (| data_in);
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end else if (N == 16) begin
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reg [LN-1:0] index_r;
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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16'b1000000000000000: index_r = LN'(0);
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16'b?100000000000000: index_r = LN'(1);
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16'b??10000000000000: index_r = LN'(2);
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16'b???1000000000000: index_r = LN'(3);
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16'b????100000000000: index_r = LN'(4);
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16'b?????10000000000: index_r = LN'(5);
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16'b??????1000000000: index_r = LN'(6);
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16'b???????100000000: index_r = LN'(7);
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16'b????????10000000: index_r = LN'(8);
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16'b?????????1000000: index_r = LN'(9);
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16'b??????????100000: index_r = LN'(10);
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16'b???????????10000: index_r = LN'(11);
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16'b????????????1000: index_r = LN'(12);
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16'b?????????????100: index_r = LN'(13);
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16'b??????????????10: index_r = LN'(14);
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16'b???????????????1: index_r = LN'(15);
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default: index_r = 'x;
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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16'b0000000000000001: index_r = LN'(0);
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@ -71,7 +137,66 @@ module VX_onehot_encoder #(
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default: index_r = 'x;
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endcase
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end
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end else begin
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end
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assign data_out = index_r;
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assign valid = (| data_in);
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end if (FAST) begin
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`IGNORE_WARNINGS_BEGIN
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localparam levels_lp = $clog2(N);
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localparam aligned_width_lp = 1 << $clog2(N);
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wire [levels_lp:0][aligned_width_lp-1:0] addr;
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wire [levels_lp:0][aligned_width_lp-1:0] v;
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// base case, also handle padding for non-power of two inputs
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assign v[0] = REVERSE ? (data_in << (aligned_width_lp - N)) : ((aligned_width_lp)'(data_in));
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assign addr[0] = 'x;
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for (genvar level = 1; level < levels_lp+1; level=level+1) begin
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localparam segments_lp = 2**(levels_lp-level);
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localparam segment_slot_lp = aligned_width_lp/segments_lp;
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localparam segment_width_lp = level; // how many bits are needed at each level
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for (genvar segment = 0; segment < segments_lp; segment=segment+1) begin
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wire [1:0] vs = {
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v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)],
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v[level-1][segment*segment_slot_lp]
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};
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assign v[level][segment*segment_slot_lp] = (| vs);
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if (level == 1) begin
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assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = vs[!REVERSE];
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end else begin
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assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = {
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vs[!REVERSE],
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addr[level-1][segment*segment_slot_lp+:segment_width_lp-1] | addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1]
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};
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end
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end
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end
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assign data_out = addr[levels_lp][`LOG2UP(N)-1:0];
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assign valid = v[levels_lp][0];
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`IGNORE_WARNINGS_END
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end else begin
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reg [LN-1:0] index_r;
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if (REVERSE) begin
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always @(*) begin
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index_r = 'x;
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for (integer i = N-1; i >= 0; --i) begin
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if (data_in[i]) begin
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index_r = `LOG2UP(N)'(i);
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end
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end
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end
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end else begin
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always @(*) begin
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index_r = 'x;
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for (integer i = 0; i < N; i++) begin
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@ -84,7 +209,6 @@ module VX_onehot_encoder #(
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assign data_out = index_r;
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assign valid = (| data_in);
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end
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endmodule
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@ -1,9 +1,10 @@
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`include "VX_platform.vh"
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module VX_priority_encoder #(
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parameter N = 1,
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parameter FAST = 1,
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parameter LN = `LOG2UP(N)
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parameter N = 1,
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parameter REVERSE = 0,
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parameter FAST = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [N-1:0] onehot,
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@ -19,16 +20,26 @@ module VX_priority_encoder #(
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end else if (N == 2) begin
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assign onehot = {~data_in[0], data_in[0]};
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assign index = ~data_in[0];
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assign onehot = {~data_in[REVERSE], data_in[REVERSE]};
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assign index = ~data_in[REVERSE];
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assign valid_out = (| data_in);
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end else begin
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end else if (N == 4) begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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if (N == 4) begin
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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4'b1???: begin onehot_r = 4'b0001; index_r = LN'(0); end
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4'b01??: begin onehot_r = 4'b0010; index_r = LN'(1); end
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4'b001?: begin onehot_r = 4'b0100; index_r = LN'(2); end
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4'b0001: begin onehot_r = 4'b1000; index_r = LN'(3); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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4'b???1: begin onehot_r = 4'b0001; index_r = LN'(0); end
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@ -38,7 +49,31 @@ module VX_priority_encoder #(
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else if (N == 8) begin
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end
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assign index = index_r;
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assign onehot = onehot_r;
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end else if (N == 8) begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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8'b1???????: begin onehot_r = 8'b00000001; index_r = LN'(0); end
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8'b01??????: begin onehot_r = 8'b00000010; index_r = LN'(1); end
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8'b001?????: begin onehot_r = 8'b00000100; index_r = LN'(2); end
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8'b0001????: begin onehot_r = 8'b00001000; index_r = LN'(3); end
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8'b00001???: begin onehot_r = 8'b00010000; index_r = LN'(4); end
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8'b000001??: begin onehot_r = 8'b00100000; index_r = LN'(5); end
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8'b0000001?: begin onehot_r = 8'b01000000; index_r = LN'(6); end
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8'b00000001: begin onehot_r = 8'b10000000; index_r = LN'(7); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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8'b???????1: begin onehot_r = 8'b00000001; index_r = LN'(0); end
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@ -52,7 +87,39 @@ module VX_priority_encoder #(
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else if (N == 16) begin
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end
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assign index = index_r;
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assign onehot = onehot_r;
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end else if (N == 16) begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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if (REVERSE) begin
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always @(*) begin
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casez (data_in)
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16'b1???????????????: begin onehot_r = 16'b0000000000000001; index_r = LN'(0); end
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16'b01??????????????: begin onehot_r = 16'b0000000000000010; index_r = LN'(1); end
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16'b001?????????????: begin onehot_r = 16'b0000000000000100; index_r = LN'(2); end
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16'b0001????????????: begin onehot_r = 16'b0000000000001000; index_r = LN'(3); end
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16'b00001???????????: begin onehot_r = 16'b0000000000010000; index_r = LN'(4); end
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16'b000001??????????: begin onehot_r = 16'b0000000000100000; index_r = LN'(5); end
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16'b0000001?????????: begin onehot_r = 16'b0000000001000000; index_r = LN'(6); end
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16'b00000001????????: begin onehot_r = 16'b0000000010000000; index_r = LN'(7); end
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16'b000000001???????: begin onehot_r = 16'b0000000100000000; index_r = LN'(8); end
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16'b0000000001??????: begin onehot_r = 16'b0000001000000000; index_r = LN'(9); end
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16'b00000000001?????: begin onehot_r = 16'b0000010000000000; index_r = LN'(10); end
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16'b000000000001????: begin onehot_r = 16'b0000100000000000; index_r = LN'(11); end
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16'b0000000000001???: begin onehot_r = 16'b0001000000000000; index_r = LN'(12); end
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16'b00000000000001??: begin onehot_r = 16'b0010000000000000; index_r = LN'(13); end
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16'b000000000000001?: begin onehot_r = 16'b0100000000000000; index_r = LN'(14); end
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16'b0000000000000001: begin onehot_r = 16'b1000000000000000; index_r = LN'(15); end
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end else begin
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always @(*) begin
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casez (data_in)
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16'b???????????????1: begin onehot_r = 16'b0000000000000001; index_r = LN'(0); end
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@ -74,6 +141,58 @@ module VX_priority_encoder #(
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default: begin onehot_r = 'x; index_r = 'x; end
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endcase
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end
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end
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assign index = index_r;
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assign onehot = onehot_r;
|
||||
|
||||
end else if (FAST) begin
|
||||
|
||||
wire [N-1:0] scan_lo;
|
||||
|
||||
VX_scan #(
|
||||
.N (N),
|
||||
.OP (2),
|
||||
.REVERSE (REVERSE)
|
||||
) scan (
|
||||
.data_in (data_in),
|
||||
.data_out (scan_lo)
|
||||
);
|
||||
|
||||
if (REVERSE) begin
|
||||
assign onehot = scan_lo & {1'b1, (~scan_lo[N-1:1])};
|
||||
assign valid_out = scan_lo[0];
|
||||
end else begin
|
||||
assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
|
||||
assign valid_out = scan_lo[N-1];
|
||||
end
|
||||
|
||||
VX_onehot_encoder #(
|
||||
.N (N),
|
||||
.REVERSE (REVERSE)
|
||||
) onehot_encoder (
|
||||
.data_in (onehot),
|
||||
.data_out (index),
|
||||
`UNUSED_PIN (valid)
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
reg [LN-1:0] index_r;
|
||||
reg [N-1:0] onehot_r;
|
||||
|
||||
if (REVERSE) begin
|
||||
always @(*) begin
|
||||
index_r = 'x;
|
||||
onehot_r = 'x;
|
||||
for (integer i = 0; i < N; ++i) begin
|
||||
if (data_in[i]) begin
|
||||
index_r = LN'(i);
|
||||
onehot_r = 0;
|
||||
onehot_r[i] = 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
always @(*) begin
|
||||
index_r = 'x;
|
||||
|
|
@ -86,11 +205,13 @@ module VX_priority_encoder #(
|
|||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign index = index_r;
|
||||
assign onehot = onehot_r;
|
||||
assign valid_out = (| data_in);
|
||||
assign onehot = onehot_r;
|
||||
|
||||
end
|
||||
|
||||
assign valid_out = (| data_in);
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue