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interfaces refactoring

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This commit is contained in:
Blaise Tine 2020-07-02 19:44:32 -07:00
parent c5a64a0eed
commit a5f4eb3d13
9 changed files with 27 additions and 27 deletions
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2
driver/rtlsim/Makefile
View file

@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1
AFU=1
#AFU=1
CFLAGS += -fPIC

2
driver/tests/basic/Makefile
View file

@ -38,7 +38,7 @@ $(PROJECT): $(SRCS)
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@
run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 4096
LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256
run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256

2
driver/tests/demo/Makefile
View file

@ -36,7 +36,7 @@ $(PROJECT): $(SRCS)
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@
run-fpga: $(PROJECT)
LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 128
LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16
run-ase: $(PROJECT)
ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16

20
hw/rtl/VX_exec_unit.v
View file

@ -115,15 +115,15 @@ module VX_exec_unit (
assign inst_exec_wb_if.curr_PC = in_curr_PC;
// Jal rsp
assign jal_rsp_temp_if.jal = in_jal;
assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
assign jal_rsp_temp_if.valid = in_jal;
assign jal_rsp_temp_if.dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num;
// Branch rsp
assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid);
assign branch_rsp_temp_if.branch_dir = temp_branch_dir;
assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num;
assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset
assign branch_rsp_temp_if.valid = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid);
assign branch_rsp_temp_if.dir = temp_branch_dir;
assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num;
assign branch_rsp_temp_if.dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset
VX_generic_register #(
.N(33 + `NW_BITS-1 + 1)
@ -132,8 +132,8 @@ module VX_exec_unit (
.reset (reset),
.stall (1'b0),
.flush (1'b0),
.in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.warp_num}),
.out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.warp_num})
.in ({jal_rsp_temp_if.valid, jal_rsp_temp_if.dest, jal_rsp_temp_if.warp_num}),
.out ({jal_rsp_if.valid , jal_rsp_if.dest , jal_rsp_if.warp_num})
);
VX_generic_register #(
@ -143,8 +143,8 @@ module VX_exec_unit (
.reset (reset),
.stall (1'b0),
.flush (1'b0),
.in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.branch_dest}),
.out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.warp_num , branch_rsp_if.branch_dest })
.in ({branch_rsp_temp_if.valid, branch_rsp_temp_if.dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.dest}),
.out ({branch_rsp_if.valid , branch_rsp_if.dir , branch_rsp_if.warp_num , branch_rsp_if.dest })
);
endmodule : VX_exec_unit

10
hw/rtl/VX_fetch.v
View file

@ -68,14 +68,14 @@ module VX_fetch (
.split_warp_num (warp_ctl_if.warp_num),
// JAL
.jal (jal_rsp_if.jal),
.jal_dest (jal_rsp_if.jal_dest),
.jal (jal_rsp_if.valid),
.dest (jal_rsp_if.dest),
.jal_warp_num (jal_rsp_if.warp_num),
// Branch
.branch_valid (branch_rsp_if.valid_branch),
.branch_dir (branch_rsp_if.branch_dir),
.branch_dest (branch_rsp_if.branch_dest),
.branch_valid (branch_rsp_if.valid),
.branch_dir (branch_rsp_if.dir),
.branch_dest (branch_rsp_if.dest),
.branch_warp_num (branch_rsp_if.warp_num),
// Outputs

4
hw/rtl/VX_warp.v
View file

@ -9,7 +9,7 @@ module VX_warp (
input wire[`NUM_THREADS-1:0] thread_mask,
input wire change_mask,
input wire jal,
input wire[31:0] jal_dest,
input wire[31:0] dest,
input wire branch_dir,
input wire[31:0] branch_dest,
input wire wspawn,
@ -43,7 +43,7 @@ module VX_warp (
always @(*) begin
if (jal == 1'b1) begin
temp_PC = jal_dest;
temp_PC = dest;
end else if (branch_dir) begin
temp_PC = branch_dest;
end else begin

4
hw/rtl/VX_warp_sched.v
View file

@ -44,7 +44,7 @@ module VX_warp_sched (
// JAL
input wire jal,
input wire[31:0] jal_dest,
input wire[31:0] dest,
input wire[`NW_BITS-1:0] jal_warp_num,
// Branch
@ -203,7 +203,7 @@ module VX_warp_sched (
// Jal
if (jal) begin
warp_pcs[jal_warp_num] <= jal_dest;
warp_pcs[jal_warp_num] <= dest;
warp_stalled[jal_warp_num] <= 0;
end

6
hw/rtl/interfaces/VX_branch_rsp_if.v
View file

@ -5,9 +5,9 @@
interface VX_branch_rsp_if ();
wire valid_branch;
wire branch_dir;
wire [31:0] branch_dest;
wire valid;
wire dir;
wire [31:0] dest;
wire [`NW_BITS-1:0] warp_num;
endinterface

4
hw/rtl/interfaces/VX_jal_rsp_if.v
View file

@ -6,8 +6,8 @@
interface VX_jal_rsp_if ();
wire jal;
wire [31:0] jal_dest;
wire valid;
wire [31:0] dest;
wire [`NW_BITS-1:0] warp_num;
endinterface