github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 13:27:29 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

set target synthesis freq=200 MHz, set 4-cores as default config, MULT.latency=1, DIV.latency=18

Browse source
This commit is contained in:
Blaise Tine 2020-06-29 08:03:19 -07:00
parent d33916f1e0
commit a70562d386
8 changed files with 40 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

4
driver/rtlsim/Makefile
View file

@ -16,8 +16,8 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE
#DBG_FLAGS += $(DBG_PRINT_FLAGS)
DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1

27
hw/opae/Makefile
View file

@ -2,7 +2,7 @@ ASE_BUILD_DIR=build_ase
FPGA_BUILD_DIR=build_fpga
all: ase-2c
all: ase-1c
ase-1c: setup-ase-1c
make -C $(ASE_BUILD_DIR)_1c
@ -10,47 +10,72 @@ ase-1c: setup-ase-1c
ase-2c: setup-ase-2c
make -C $(ASE_BUILD_DIR)_2c
ase-4c: setup-ase-4c
make -C $(ASE_BUILD_DIR)_4c
setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile
setup-ase-4c: $(ASE_BUILD_DIR)_4c/Makefile
$(ASE_BUILD_DIR)_1c/Makefile:
afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
$(ASE_BUILD_DIR)_2c/Makefile:
afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c
$(ASE_BUILD_DIR)_4c/Makefile:
afu_sim_setup -s sources_4c.txt $(ASE_BUILD_DIR)_4c
fpga-1c: setup-fpga-1c
cd $(FPGA_BUILD_DIR)_1c && qsub-synth
fpga-2c: setup-fpga-2c
cd $(FPGA_BUILD_DIR)_2c && qsub-synth
fpga-4c: setup-fpga-4c
cd $(FPGA_BUILD_DIR)_4c && qsub-synth
setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf
setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf
setup-fpga-4c: $(FPGA_BUILD_DIR)_4c/build/dcp.qpf
$(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c
$(FPGA_BUILD_DIR)_2c/build/dcp.qpf:
afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c
$(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s sources_4c.txt $(FPGA_BUILD_DIR)_4c
run-ase-1c:
cd $(ASE_BUILD_DIR)_1c && make sim
run-ase-2c:
cd $(ASE_BUILD_DIR)_2c && make sim
run-ase-4c:
cd $(ASE_BUILD_DIR)_4c && make sim
clean-ase-1c:
rm -rf $(ASE_BUILD_DIR)_1c
clean-ase-2c:
rm -rf $(ASE_BUILD_DIR)_2c
clean-ase-4c:
rm -rf $(ASE_BUILD_DIR)_4c
clean-fpga-1c:
rm -rf $(FPGA_BUILD_DIR)_1c
clean-fpga-2c:
rm -rf $(FPGA_BUILD_DIR)_2c
clean-fpga-4c:
rm -rf $(FPGA_BUILD_DIR)_4c

4
hw/opae/sources_4c.txt Normal file
View file

@ -0,0 +1,4 @@
+define+NUM_CORES=4
+define+L2_ENABLE=0
C:sources.txt

4
hw/rtl/VX_alu_unit.v
View file

@ -13,8 +13,8 @@ module VX_alu_unit (
output reg [31:0] alu_result,
output reg alu_stall
);
localparam DIV_PIPELINE_LEN = 20;
localparam MUL_PIPELINE_LEN = 8;
localparam DIV_PIPELINE_LEN = 18;
localparam MUL_PIPELINE_LEN = 1;
wire[31:0] div_result_unsigned;
wire[31:0] div_result_signed;

4
hw/rtl/VX_config.vh
View file

@ -8,7 +8,7 @@
`endif
`ifndef NUM_CORES
`define NUM_CORES 1
`define NUM_CORES 4
`endif
`ifndef NUM_WARPS
@ -52,7 +52,7 @@
`endif
`ifndef L2_ENABLE
`define L2_ENABLE (`NUM_CORES > 2)
`define L2_ENABLE 0
`endif
`ifndef L3_ENABLE

2
hw/rtl/libs/VX_generic_queue.v
View file

@ -3,7 +3,7 @@
module VX_generic_queue #(
parameter DATAW,
parameter SIZE = 16,
parameter BUFFERED_OUTPUT = (SIZE > 8)
parameter BUFFERED_OUTPUT = 1
) (
input wire clk,
input wire reset,

4
hw/simulate/Makefile
View file

@ -1,5 +1,5 @@
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4
#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
# control RTL debug print states

2
hw/syn/quartus/project.sdc
View file

@ -1,6 +1,6 @@
set_time_format -unit ns -decimal_places 3
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
create_clock -name {clk} -period "200 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty