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minor update

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This commit is contained in:
Blaise Tine 2024-05-23 22:33:12 -07:00
parent f6663d6618
commit a72c68acf4
23 changed files with 171 additions and 174 deletions
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4
hw/rtl/VX_define.vh
View file

@ -126,7 +126,7 @@
///////////////////////////////////////////////////////////////////////////////
`define INST_OP_BITS 4
`define INST_MOD_BITS $bits(op_mod_t)
`define INST_ARGS_BITS $bits(op_args_t)
`define INST_FMT_BITS 2
///////////////////////////////////////////////////////////////////////////////
@ -432,7 +432,7 @@
data.tmask, \
data.PC, \
data.op_type, \
data.op_mod, \
data.op_args, \
data.wb, \
data.rd, \
tid, \

2
hw/rtl/VX_gpu_pkg.sv
View file

@ -116,7 +116,7 @@ package VX_gpu_pkg;
lsu_mod_t lsu;
csr_mod_t csr;
wctl_mod_t wctl;
} op_mod_t;
} op_args_t;
/* verilator lint_off UNUSED */

12
hw/rtl/core/VX_alu_int.sv
View file

@ -52,16 +52,14 @@ module VX_alu_int #(
wire [NUM_LANES-1:0][`XLEN-1:0] alu_result_r;
`ifdef XLEN_64
wire is_alu_w = execute_if.data.op_mod.alu.is_w;
wire is_alu_w = execute_if.data.op_args.alu.is_w;
`else
wire is_alu_w = 0;
`endif
`UNUSED_VAR (execute_if.data.op_mod)
wire [`INST_ALU_BITS-1:0] alu_op = `INST_ALU_BITS'(execute_if.data.op_type);
wire [`INST_BR_BITS-1:0] br_op = `INST_BR_BITS'(execute_if.data.op_type);
wire is_br_op = (execute_if.data.op_mod.alu.xtype == `ALU_TYPE_BRANCH);
wire is_br_op = (execute_if.data.op_args.alu.xtype == `ALU_TYPE_BRANCH);
wire is_sub_op = `INST_ALU_IS_SUB(alu_op);
wire is_signed = `INST_ALU_SIGNED(alu_op);
wire [1:0] op_class = is_br_op ? `INST_BR_CLASS(alu_op) : `INST_ALU_CLASS(alu_op);
@ -69,9 +67,9 @@ module VX_alu_int #(
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1 = execute_if.data.rs1_data;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2 = execute_if.data.rs2_data;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1_PC = execute_if.data.op_mod.alu.use_PC ? {NUM_LANES{execute_if.data.PC, 1'd0}} : alu_in1;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.op_mod.alu.use_imm ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_mod.alu.imm)}} : alu_in2;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br = (execute_if.data.op_mod.alu.use_imm && ~is_br_op) ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_mod.alu.imm)}} : alu_in2;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1_PC = execute_if.data.op_args.alu.use_PC ? {NUM_LANES{execute_if.data.PC, 1'd0}} : alu_in1;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.op_args.alu.use_imm ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2;
wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br = (execute_if.data.op_args.alu.use_imm && ~is_br_op) ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i];

2
hw/rtl/core/VX_alu_muldiv.sv
View file

@ -38,7 +38,7 @@ module VX_alu_muldiv #(
wire is_mulx_op = `INST_M_IS_MULX(muldiv_op);
wire is_signed_op = `INST_M_SIGNED(muldiv_op);
`ifdef XLEN_64
wire is_alu_w = execute_if.data.op_mod.alu.is_w;
wire is_alu_w = execute_if.data.op_args.alu.is_w;
`else
wire is_alu_w = 0;
`endif

2
hw/rtl/core/VX_alu_unit.sv
View file

@ -59,7 +59,7 @@ module VX_alu_unit #(
`RESET_RELAY (block_reset, reset);
wire is_muldiv_op = `EXT_M_ENABLED && (per_block_execute_if[block_idx].data.op_mod.alu.xtype == `ALU_TYPE_MULDIV);
wire is_muldiv_op = `EXT_M_ENABLED && (per_block_execute_if[block_idx].data.op_args.alu.xtype == `ALU_TYPE_MULDIV);
VX_execute_if #(
.NUM_LANES (NUM_LANES)

6
hw/rtl/core/VX_csr_unit.sv
View file

@ -51,8 +51,8 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
wire csr_wr_enable;
wire csr_req_ready;
wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.op_mod.csr.addr;
wire [`NRI_BITS-1:0] csr_imm = execute_if.data.op_mod.csr.imm;
wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.op_args.csr.addr;
wire [`NRI_BITS-1:0] csr_imm = execute_if.data.op_args.csr.imm;
wire is_fpu_csr = (csr_addr <= `VX_CSR_FCSR);
@ -134,7 +134,7 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
// CSR write
assign csr_req_data = execute_if.data.op_mod.csr.use_imm ? `XLEN'(csr_imm) : rs1_data[0];
assign csr_req_data = execute_if.data.op_args.csr.use_imm ? `XLEN'(csr_imm) : rs1_data[0];
assign csr_wr_enable = (csr_write_enable || (| csr_req_data));
always @(*) begin

164
hw/rtl/core/VX_decode.sv
View file

@ -42,7 +42,7 @@ module VX_decode import VX_gpu_pkg::*; #(
VX_decode_sched_if.master decode_sched_if
);
localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `PC_BITS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + (`NR_BITS * 4);
localparam DATAW = `UUID_WIDTH + `NW_WIDTH + `NUM_THREADS + `PC_BITS + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + 1 + (`NR_BITS * 4);
`UNUSED_PARAM (CORE_ID)
`UNUSED_VAR (clk)
@ -50,7 +50,7 @@ module VX_decode import VX_gpu_pkg::*; #(
reg [`EX_BITS-1:0] ex_type;
reg [`INST_OP_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r;
reg use_rd, use_rs1, use_rs2, use_rs3;
reg is_wstall;
@ -149,7 +149,7 @@ module VX_decode import VX_gpu_pkg::*; #(
ex_type = '0;
op_type = 'x;
op_mod = 'x;
op_args = 'x;
rd_r = '0;
rs1_r = '0;
rs2_r = '0;
@ -164,20 +164,20 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_I: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(r_type);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = `SEXT(`IMM_BITS, i_imm);
op_args.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, i_imm);
use_rd = 1;
`USED_IREG (rd);
`USED_IREG (rs1);
end
`INST_R: begin
ex_type = `EX_ALU;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 0;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 0;
use_rd = 1;
`USED_IREG (rd);
`USED_IREG (rs1);
@ -187,19 +187,19 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_R_F7_MUL: begin
// MUL, MULH, MULHSU, MULHU
op_type = `INST_OP_BITS'(m_type);
op_mod.alu.xtype = `ALU_TYPE_MULDIV;
op_args.alu.xtype = `ALU_TYPE_MULDIV;
end
`endif
`ifdef EXT_ZICOND_ENABLE
`INST_R_F7_ZICOND: begin
// CZERO-EQZ, CZERO-NEZ
op_type = func3[1] ? `INST_OP_BITS'(`INST_ALU_CZNE) : `INST_OP_BITS'(`INST_ALU_CZEQ);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.xtype = `ALU_TYPE_ARITH;
end
`endif
default: begin
op_type = `INST_OP_BITS'(r_type);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.xtype = `ALU_TYPE_ARITH;
end
endcase
end
@ -208,20 +208,20 @@ module VX_decode import VX_gpu_pkg::*; #(
// ADDIW, SLLIW, SRLIW, SRAIW
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(r_type);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_mod.alu.is_w = 1;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = `SEXT(`IMM_BITS, iw_imm);
op_args.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.is_w = 1;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, iw_imm);
use_rd = 1;
`USED_IREG (rd);
`USED_IREG (rs1);
end
`INST_R_W: begin
ex_type = `EX_ALU;
op_mod.alu.is_w = 1;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 0;
op_args.alu.is_w = 1;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 0;
use_rd = 1;
`USED_IREG (rd);
`USED_IREG (rs1);
@ -231,13 +231,13 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_R_F7_MUL: begin
// MULW, DIVW, DIVUW, REMW, REMUW
op_type = `INST_OP_BITS'(m_type);
op_mod.alu.xtype = `ALU_TYPE_MULDIV;
op_args.alu.xtype = `ALU_TYPE_MULDIV;
end
`endif
default: begin
// ADDW, SUBW, SLLW, SRLW, SRAW
op_type = `INST_OP_BITS'(r_type);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.xtype = `ALU_TYPE_ARITH;
end
endcase
end
@ -245,33 +245,33 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_LUI: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(`INST_ALU_LUI);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = {{`IMM_BITS-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
op_args.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 1;
op_args.alu.imm = {{`IMM_BITS-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
use_rd = 1;
`USED_IREG (rd);
end
`INST_AUIPC: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(`INST_ALU_AUIPC);
op_mod.alu.xtype = `ALU_TYPE_ARITH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 1;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = {{`IMM_BITS-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
op_args.alu.xtype = `ALU_TYPE_ARITH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 1;
op_args.alu.use_imm = 1;
op_args.alu.imm = {{`IMM_BITS-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)};
use_rd = 1;
`USED_IREG (rd);
end
`INST_JAL: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(`INST_BR_JAL);
op_mod.alu.xtype = `ALU_TYPE_BRANCH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 1;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = `SEXT(`IMM_BITS, jal_imm);
op_args.alu.xtype = `ALU_TYPE_BRANCH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 1;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, jal_imm);
use_rd = 1;
is_wstall = 1;
`USED_IREG (rd);
@ -279,11 +279,11 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_JALR: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(`INST_BR_JALR);
op_mod.alu.xtype = `ALU_TYPE_BRANCH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 0;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = `SEXT(`IMM_BITS, u_12);
op_args.alu.xtype = `ALU_TYPE_BRANCH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 0;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, u_12);
use_rd = 1;
is_wstall = 1;
`USED_IREG (rd);
@ -292,11 +292,11 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_B: begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(b_type);
op_mod.alu.xtype = `ALU_TYPE_BRANCH;
op_mod.alu.is_w = 0;
op_mod.alu.use_PC = 1;
op_mod.alu.use_imm = 1;
op_mod.alu.imm = `SEXT(`IMM_BITS, b_imm);
op_args.alu.xtype = `ALU_TYPE_BRANCH;
op_args.alu.is_w = 0;
op_args.alu.use_PC = 1;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, b_imm);
is_wstall = 1;
`USED_IREG (rs1);
`USED_IREG (rs2);
@ -304,32 +304,32 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_FENCE: begin
ex_type = `EX_LSU;
op_type = `INST_LSU_FENCE;
op_mod.lsu.is_store = 0;
op_mod.lsu.is_float = 0;
op_mod.lsu.offset = 0;
op_args.lsu.is_store = 0;
op_args.lsu.is_float = 0;
op_args.lsu.offset = 0;
end
`INST_SYS : begin
if (func3[1:0] != 0) begin
ex_type = `EX_SFU;
op_type = `INST_OP_BITS'(`INST_SFU_CSR(func3[1:0]));
op_mod.csr.addr = u_12;
op_mod.csr.use_imm = func3[2];
op_args.csr.addr = u_12;
op_args.csr.use_imm = func3[2];
use_rd = 1;
is_wstall = is_fpu_csr; // only stall for FPU CSRs
`USED_IREG (rd);
if (func3[2]) begin
op_mod.csr.imm = rs1;
op_args.csr.imm = rs1;
end else begin
`USED_IREG (rs1);
end
end else begin
ex_type = `EX_ALU;
op_type = `INST_OP_BITS'(s_type);
op_mod.alu.xtype = `ALU_TYPE_BRANCH;
op_mod.alu.is_w = 0;
op_mod.alu.use_imm = 1;
op_mod.alu.use_PC = 1;
op_mod.alu.imm = `IMM_BITS'd4;
op_args.alu.xtype = `ALU_TYPE_BRANCH;
op_args.alu.is_w = 0;
op_args.alu.use_imm = 1;
op_args.alu.use_PC = 1;
op_args.alu.imm = `IMM_BITS'd4;
use_rd = 1;
is_wstall = 1;
`USED_IREG (rd);
@ -341,9 +341,9 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_L: begin
ex_type = `EX_LSU;
op_type = `INST_OP_BITS'({1'b0, func3});
op_mod.lsu.is_store = 0;
op_mod.lsu.is_float = opcode[2];
op_mod.lsu.offset = u_12;
op_args.lsu.is_store = 0;
op_args.lsu.is_float = opcode[2];
op_args.lsu.offset = u_12;
use_rd = 1;
`ifdef EXT_F_ENABLE
if (opcode[2]) begin
@ -359,9 +359,9 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_S: begin
ex_type = `EX_LSU;
op_type = `INST_OP_BITS'({1'b1, func3});
op_mod.lsu.is_store = 1;
op_mod.lsu.is_float = opcode[2];
op_mod.lsu.offset = s_imm;
op_args.lsu.is_store = 1;
op_args.lsu.is_float = opcode[2];
op_args.lsu.offset = s_imm;
`USED_IREG (rs1);
`ifdef EXT_F_ENABLE
if (opcode[2]) begin
@ -377,8 +377,8 @@ module VX_decode import VX_gpu_pkg::*; #(
`INST_FNMADD: begin
ex_type = `EX_FPU;
op_type = `INST_OP_BITS'({2'b11, opcode[3:2]});
op_mod.fpu.frm = func3;
op_mod.fpu.fmt[0] = func2[0]; // float / double
op_args.fpu.frm = func3;
op_args.fpu.fmt[0] = func2[0]; // float / double
use_rd = 1;
`USED_FREG (rd);
`USED_FREG (rs1);
@ -387,9 +387,9 @@ module VX_decode import VX_gpu_pkg::*; #(
end
`INST_FCI: begin
ex_type = `EX_FPU;
op_mod.fpu.frm = func3;
op_mod.fpu.fmt[0] = func2[0]; // float / double
op_mod.fpu.fmt[1] = rs2[1]; // int32 / int64
op_args.fpu.frm = func3;
op_args.fpu.fmt[0] = func2[0]; // float / double
op_args.fpu.fmt[1] = rs2[1]; // int32 / int64
use_rd = 1;
case (func5)
5'b00000, // FADD
@ -404,7 +404,7 @@ module VX_decode import VX_gpu_pkg::*; #(
5'b00100: begin
// NCP: FSGNJ=0, FSGNJN=1, FSGNJX=2
op_type = `INST_OP_BITS'(`INST_FPU_MISC);
op_mod.fpu.frm = `INST_FRM_BITS'(func3[1:0]);
op_args.fpu.frm = `INST_FRM_BITS'(func3[1:0]);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
@ -412,7 +412,7 @@ module VX_decode import VX_gpu_pkg::*; #(
5'b00101: begin
// NCP: FMIN=6, FMAX=7
op_type = `INST_OP_BITS'(`INST_FPU_MISC);
op_mod.fpu.frm = `INST_FRM_BITS'(func3[0] ? 7 : 6);
op_args.fpu.frm = `INST_FRM_BITS'(func3[0] ? 7 : 6);
`USED_FREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2);
@ -454,11 +454,11 @@ module VX_decode import VX_gpu_pkg::*; #(
if (func3[0]) begin
// NCP: FCLASS=3
op_type = `INST_OP_BITS'(`INST_FPU_MISC);
op_mod.fpu.frm = `INST_FRM_BITS'(3);
op_args.fpu.frm = `INST_FRM_BITS'(3);
end else begin
// NCP: FMV.X.W=4
op_type = `INST_OP_BITS'(`INST_FPU_MISC);
op_mod.fpu.frm = `INST_FRM_BITS'(4);
op_args.fpu.frm = `INST_FRM_BITS'(4);
end
`USED_IREG (rd);
`USED_FREG (rs1);
@ -466,7 +466,7 @@ module VX_decode import VX_gpu_pkg::*; #(
5'b11110: begin
// NCP: FMV.W.X=5
op_type = `INST_OP_BITS'(`INST_FPU_MISC);
op_mod.fpu.frm = `INST_FRM_BITS'(5);
op_args.fpu.frm = `INST_FRM_BITS'(5);
`USED_FREG (rd);
`USED_IREG (rs1);
end
@ -492,7 +492,7 @@ module VX_decode import VX_gpu_pkg::*; #(
3'h2: begin // SPLIT
op_type = `INST_OP_BITS'(`INST_SFU_SPLIT);
use_rd = 1;
op_mod.wctl.is_neg = rs2[0];
op_args.wctl.is_neg = rs2[0];
`USED_IREG (rs1);
`USED_IREG (rd);
end
@ -507,7 +507,7 @@ module VX_decode import VX_gpu_pkg::*; #(
end
3'h5: begin // PRED
op_type = `INST_OP_BITS'(`INST_SFU_PRED);
op_mod.wctl.is_neg = rd[0];
op_args.wctl.is_neg = rd[0];
`USED_IREG (rs1);
`USED_IREG (rs2);
end
@ -532,8 +532,8 @@ module VX_decode import VX_gpu_pkg::*; #(
.reset (reset),
.valid_in (fetch_if.valid),
.ready_in (fetch_if.ready),
.data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_mod, wb, rd_r, rs1_r, rs2_r, rs3_r}),
.data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}),
.data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_args, wb, rd_r, rs1_r, rs2_r, rs3_r}),
.data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_args, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}),
.valid_out (decode_if.valid),
.ready_out (decode_if.ready)
);
@ -555,10 +555,10 @@ module VX_decode import VX_gpu_pkg::*; #(
`TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, {decode_if.data.PC, 1'd0}, instr));
trace_ex_type(1, decode_if.data.ex_type);
`TRACE(1, (", op="));
trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod);
trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_args);
`TRACE(1, (", tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, opds=%b%b%b%b",
decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, use_rd, use_rs1, use_rs2, use_rs3));
trace_op_mod(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod);
trace_op_args(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_args);
`TRACE(1, (" (#%0d)\n", decode_if.data.uuid));
end
end

6
hw/rtl/core/VX_dispatch.sv
View file

@ -31,7 +31,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + `INST_OP_BITS + `INST_MOD_BITS + 1 + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + `INST_OP_BITS + `INST_ARGS_BITS + 1 + `NR_BITS + (3 * `NUM_THREADS * `XLEN) + `NT_WIDTH;
wire [`NUM_THREADS-1:0][`NT_WIDTH-1:0] tids;
for (genvar i = 0; i < `NUM_THREADS; ++i) begin
@ -124,14 +124,14 @@ module VX_dispatch import VX_gpu_pkg::*; #(
`TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), {operands_if[i].data.PC, 1'b0}));
trace_ex_type(1, operands_if[i].data.ex_type);
`TRACE(1, (", op="));
trace_ex_op(1, operands_if[i].data.ex_type, operands_if[i].data.op_type, operands_if[i].data.op_mod);
trace_ex_op(1, operands_if[i].data.ex_type, operands_if[i].data.op_type, operands_if[i].data.op_args);
`TRACE(1, (", tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
`TRACE_ARRAY1D(1, "0x%0h", operands_if[i].data.rs1_data, `NUM_THREADS);
`TRACE(1, (", rs2_data="));
`TRACE_ARRAY1D(1, "0x%0h", operands_if[i].data.rs2_data, `NUM_THREADS);
`TRACE(1, (", rs3_data="));
`TRACE_ARRAY1D(1, "0x%0h", operands_if[i].data.rs3_data, `NUM_THREADS);
trace_op_mod(1, operands_if[i].data.ex_type, operands_if[i].data.op_type, operands_if[i].data.op_mod);
trace_op_args(1, operands_if[i].data.ex_type, operands_if[i].data.op_type, operands_if[i].data.op_args);
`TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
end
end

4
hw/rtl/core/VX_dispatch_unit.sv
View file

@ -38,8 +38,8 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
localparam BATCH_COUNT = `ISSUE_WIDTH / BLOCK_SIZE;
localparam BATCH_COUNT_W= `LOG2UP(BATCH_COUNT);
localparam ISSUE_W = `LOG2UP(`ISSUE_WIDTH);
localparam IN_DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_MOD_BITS + 1 + `PC_BITS + `NR_BITS + `NT_WIDTH + (3 * `NUM_THREADS * `XLEN);
localparam OUT_DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `INST_OP_BITS + `INST_MOD_BITS + 1 + `PC_BITS + `NR_BITS + `NT_WIDTH + (3 * NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1;
localparam IN_DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `INST_OP_BITS + `INST_ARGS_BITS + 1 + `PC_BITS + `NR_BITS + `NT_WIDTH + (3 * `NUM_THREADS * `XLEN);
localparam OUT_DATAW = `UUID_WIDTH + `NW_WIDTH + NUM_LANES + `INST_OP_BITS + `INST_ARGS_BITS + 1 + `PC_BITS + `NR_BITS + `NT_WIDTH + (3 * NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1;
localparam FANOUT_ENABLE= (`NUM_THREADS > MAX_FANOUT);
localparam DATA_TMASK_OFF = IN_DATAW - (`UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS);

2
hw/rtl/core/VX_execute.sv
View file

@ -117,7 +117,7 @@ module VX_execute import VX_gpu_pkg::*; #(
// simulation helper signal to get RISC-V tests Pass/Fail status
assign sim_ebreak = dispatch_if[0].valid && dispatch_if[0].ready
&& dispatch_if[0].data.wis == 0
&& (dispatch_if[0].data.op_mod.alu.xtype == `ALU_TYPE_BRANCH)
&& (dispatch_if[0].data.op_args.alu.xtype == `ALU_TYPE_BRANCH)
&& (`INST_BR_BITS'(dispatch_if[0].data.op_type) == `INST_BR_EBREAK
|| `INST_BR_BITS'(dispatch_if[0].data.op_type) == `INST_BR_ECALL);

4
hw/rtl/core/VX_fpu_unit.sv
View file

@ -78,8 +78,8 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
wire [TAG_WIDTH-1:0] fpu_req_tag, fpu_rsp_tag;
wire mdata_full;
wire [`INST_FMT_BITS-1:0] fpu_fmt = per_block_execute_if[block_idx].data.op_mod.fpu.fmt;
wire [`INST_FRM_BITS-1:0] fpu_frm = per_block_execute_if[block_idx].data.op_mod.fpu.frm;
wire [`INST_FMT_BITS-1:0] fpu_fmt = per_block_execute_if[block_idx].data.op_args.fpu.fmt;
wire [`INST_FRM_BITS-1:0] fpu_frm = per_block_execute_if[block_idx].data.op_args.fpu.frm;
wire execute_fire = per_block_execute_if[block_idx].valid && per_block_execute_if[block_idx].ready;
wire fpu_rsp_fire = fpu_rsp_valid && fpu_rsp_ready;

6
hw/rtl/core/VX_gpr_slice.sv
View file

@ -25,7 +25,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
VX_operands_if.master operands_if
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + `NR_BITS;
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + `NR_BITS;
localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * ISSUE_RATIO);
localparam STATE_IDLE = 2'd0;
@ -210,7 +210,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
scoreboard_if.data.wb,
scoreboard_if.data.ex_type,
scoreboard_if.data.op_type,
scoreboard_if.data.op_mod,
scoreboard_if.data.op_args,
scoreboard_if.data.rd
}),
.ready_in (stg_ready_in),
@ -223,7 +223,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
operands_if.data.wb,
operands_if.data.ex_type,
operands_if.data.op_type,
operands_if.data.op_mod,
operands_if.data.op_args,
operands_if.data.rd
}),
.ready_out (operands_if.ready)

4
hw/rtl/core/VX_ibuffer.sv
View file

@ -26,7 +26,7 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
VX_ibuffer_if.master ibuffer_if [`NUM_WARPS]
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `UUID_WIDTH + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + (`NR_BITS * 4);
localparam DATAW = `UUID_WIDTH + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + (`NR_BITS * 4);
wire [`NUM_WARPS-1:0] ibuf_ready_in;
@ -47,7 +47,7 @@ module VX_ibuffer import VX_gpu_pkg::*; #(
decode_if.data.PC,
decode_if.data.ex_type,
decode_if.data.op_type,
decode_if.data.op_mod,
decode_if.data.op_args,
decode_if.data.wb,
decode_if.data.rd,
decode_if.data.rs1,

13
hw/rtl/core/VX_lsu_slice.sv
View file

@ -52,7 +52,6 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
.NUM_LANES (NUM_LANES)
) commit_no_rsp_if();
`UNUSED_VAR (execute_if.data.op_mod)
`UNUSED_VAR (execute_if.data.rs3_data)
`UNUSED_VAR (execute_if.data.tid)
@ -62,7 +61,7 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
wire [NUM_LANES-1:0][`XLEN-1:0] full_addr;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign full_addr[i] = execute_if.data.rs1_data[i] + `SEXT(`XLEN, execute_if.data.op_mod.lsu.offset);
assign full_addr[i] = execute_if.data.rs1_data[i] + `SEXT(`XLEN, execute_if.data.op_args.lsu.offset);
end
// address type calculation
@ -129,24 +128,24 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
end
wire req_skip = req_is_fence && ~execute_if.data.eop;
wire no_rsp_buf_use = (mem_req_rw && ~execute_if.data.wb) || req_skip;
wire no_rsp_buf_enable = (mem_req_rw && ~execute_if.data.wb) || req_skip;
assign mem_req_valid = execute_if.valid
&& ~req_skip
&& ~(no_rsp_buf_use && ~no_rsp_buf_ready)
&& ~(no_rsp_buf_enable && ~no_rsp_buf_ready)
&& ~fence_lock;
assign no_rsp_buf_valid = execute_if.valid
&& no_rsp_buf_use
&& no_rsp_buf_enable
&& (req_skip || mem_req_ready)
&& ~fence_lock;
assign execute_if.ready = (mem_req_ready || req_skip)
&& ~(no_rsp_buf_use && ~no_rsp_buf_ready)
&& ~(no_rsp_buf_enable && ~no_rsp_buf_ready)
&& ~fence_lock;
assign mem_req_mask = execute_if.data.tmask;
assign mem_req_rw = execute_if.data.op_mod.lsu.is_store;
assign mem_req_rw = execute_if.data.op_args.lsu.is_store;
// address formatting

4
hw/rtl/core/VX_scoreboard.sv
View file

@ -30,7 +30,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
VX_scoreboard_if.master scoreboard_if [`ISSUE_WIDTH]
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `UUID_WIDTH + `NUM_THREADS + `PC_BITS + `EX_BITS + `INST_OP_BITS + `INST_MOD_BITS + (`NR_BITS * 4) + 1;
localparam DATAW = `UUID_WIDTH + `NUM_THREADS + `PC_BITS + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + (`NR_BITS * 4) + 1;
`ifdef PERF_ENABLE
reg [`NUM_WARPS-1:0][`NUM_EX_UNITS-1:0] perf_inuse_units_per_cycle;
@ -319,7 +319,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
scoreboard_if[i].data.PC,
scoreboard_if[i].data.ex_type,
scoreboard_if[i].data.op_type,
scoreboard_if[i].data.op_mod,
scoreboard_if[i].data.op_args,
scoreboard_if[i].data.wb,
scoreboard_if[i].data.rd,
scoreboard_if[i].data.rs1,

96
hw/rtl/core/VX_trace.vh
View file

@ -29,14 +29,14 @@
task trace_ex_op(input int level,
input [`EX_BITS-1:0] ex_type,
input [`INST_OP_BITS-1:0] op_type,
input VX_gpu_pkg::op_mod_t op_mod
input VX_gpu_pkg::op_args_t op_args
);
case (ex_type)
`EX_ALU: begin
case (op_mod.alu.xtype)
case (op_args.alu.xtype)
`ALU_TYPE_ARITH: begin
if (op_mod.alu.is_w) begin
if (op_mod.alu.use_imm) begin
if (op_args.alu.is_w) begin
if (op_args.alu.use_imm) begin
case (`INST_ALU_BITS'(op_type))
`INST_ALU_ADD: `TRACE(level, ("ADDIW"));
`INST_ALU_SLL: `TRACE(level, ("SLLIW"));
@ -55,7 +55,7 @@
endcase
end
end else begin
if (op_mod.alu.use_imm) begin
if (op_args.alu.use_imm) begin
case (`INST_ALU_BITS'(op_type))
`INST_ALU_ADD: `TRACE(level, ("ADDI"));
`INST_ALU_SLL: `TRACE(level, ("SLLI"));
@ -108,7 +108,7 @@
endcase
end
`ALU_TYPE_MULDIV: begin
if (op_mod.alu.is_w) begin
if (op_args.alu.is_w) begin
case (`INST_M_BITS'(op_type))
`INST_M_MUL: `TRACE(level, ("MULW"));
`INST_M_DIV: `TRACE(level, ("DIVW"));
@ -135,7 +135,7 @@
endcase
end
`EX_LSU: begin
if (op_mod.lsu.is_float) begin
if (op_args.lsu.is_float) begin
case (`INST_LSU_BITS'(op_type))
`INST_LSU_LW: `TRACE(level, ("FLW"));
`INST_LSU_LD: `TRACE(level, ("FLD"));
@ -164,69 +164,69 @@
`EX_FPU: begin
case (`INST_FPU_BITS'(op_type))
`INST_FPU_ADD: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FADD.D"));
else
`TRACE(level, ("FADD.S"));
end
`INST_FPU_SUB: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FSUB.D"));
else
`TRACE(level, ("FSUB.S"));
end
`INST_FPU_MUL: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FMUL.D"));
else
`TRACE(level, ("FMUL.S"));
end
`INST_FPU_DIV: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FDIV.D"));
else
`TRACE(level, ("FDIV.S"));
end
`INST_FPU_SQRT: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FSQRT.D"));
else
`TRACE(level, ("FSQRT.S"));
end
`INST_FPU_MADD: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FMADD.D"));
else
`TRACE(level, ("FMADD.S"));
end
`INST_FPU_MSUB: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FMSUB.D"));
else
`TRACE(level, ("FMSUB.S"));
end
`INST_FPU_NMADD: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FNMADD.D"));
else
`TRACE(level, ("FNMADD.S"));
end
`INST_FPU_NMSUB: begin
if (op_mod.fpu.fmt[0])
if (op_args.fpu.fmt[0])
`TRACE(level, ("FNMSUB.D"));
else
`TRACE(level, ("FNMSUB.S"));
end
`INST_FPU_CMP: begin
if (op_mod.fpu.fmt[0]) begin
case (op_mod.fpu.frm[1:0])
if (op_args.fpu.fmt[0]) begin
case (op_args.fpu.frm[1:0])
0: `TRACE(level, ("FLE.D"));
1: `TRACE(level, ("FLT.D"));
2: `TRACE(level, ("FEQ.D"));
default: `TRACE(level, ("?"));
endcase
end else begin
case (op_mod.fpu.frm[1:0])
case (op_args.fpu.frm[1:0])
0: `TRACE(level, ("FLE.S"));
1: `TRACE(level, ("FLT.S"));
2: `TRACE(level, ("FEQ.S"));
@ -235,21 +235,21 @@
end
end
`INST_FPU_F2F: begin
if (op_mod.fpu.fmt[0]) begin
if (op_args.fpu.fmt[0]) begin
`TRACE(level, ("FCVT.D.S"));
end else begin
`TRACE(level, ("FCVT.S.D"));
end
end
`INST_FPU_F2I: begin
if (op_mod.fpu.fmt[0]) begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.L.D"));
end else begin
`TRACE(level, ("FCVT.W.D"));
end
end else begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.L.S"));
end else begin
`TRACE(level, ("FCVT.W.S"));
@ -257,14 +257,14 @@
end
end
`INST_FPU_F2U: begin
if (op_mod.fpu.fmt[0]) begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.LU.D"));
end else begin
`TRACE(level, ("FCVT.WU.D"));
end
end else begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.LU.S"));
end else begin
`TRACE(level, ("FCVT.WU.S"));
@ -272,14 +272,14 @@
end
end
`INST_FPU_I2F: begin
if (op_mod.fpu.fmt[0]) begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.D.L"));
end else begin
`TRACE(level, ("FCVT.D.W"));
end
end else begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.S.L"));
end else begin
`TRACE(level, ("FCVT.S.W"));
@ -287,14 +287,14 @@
end
end
`INST_FPU_U2F: begin
if (op_mod.fpu.fmt[0]) begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[0]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.D.LU"));
end else begin
`TRACE(level, ("FCVT.D.WU"));
end
end else begin
if (op_mod.fpu.fmt[1]) begin
if (op_args.fpu.fmt[1]) begin
`TRACE(level, ("FCVT.S.LU"));
end else begin
`TRACE(level, ("FCVT.S.WU"));
@ -302,8 +302,8 @@
end
end
`INST_FPU_MISC: begin
if (op_mod.fpu.fmt[0]) begin
case (op_mod)
if (op_args.fpu.fmt[0]) begin
case (op_args)
0: `TRACE(level, ("FSGNJ.D"));
1: `TRACE(level, ("FSGNJN.D"));
2: `TRACE(level, ("FSGNJX.D"));
@ -314,7 +314,7 @@
7: `TRACE(level, ("FMAX.D"));
endcase
end else begin
case (op_mod)
case (op_args)
0: `TRACE(level, ("FSGNJ.S"));
1: `TRACE(level, ("FSGNJN.S"));
2: `TRACE(level, ("FSGNJX.S"));
@ -333,13 +333,13 @@
case (`INST_SFU_BITS'(op_type))
`INST_SFU_TMC: `TRACE(level, ("TMC"));
`INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN"));
`INST_SFU_SPLIT: begin if (op_mod.wctl.is_neg) `TRACE(level, ("SPLIT.N")); else `TRACE(level, ("SPLIT")); end
`INST_SFU_SPLIT: begin if (op_args.wctl.is_neg) `TRACE(level, ("SPLIT.N")); else `TRACE(level, ("SPLIT")); end
`INST_SFU_JOIN: `TRACE(level, ("JOIN"));
`INST_SFU_BAR: `TRACE(level, ("BAR"));
`INST_SFU_PRED: begin if (op_mod.wctl.is_neg) `TRACE(level, ("PRED.N")); else `TRACE(level, ("PRED")); end
`INST_SFU_CSRRW: begin if (op_mod.csr.use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end
`INST_SFU_CSRRS: begin if (op_mod.csr.use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end
`INST_SFU_CSRRC: begin if (op_mod.csr.use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end
`INST_SFU_PRED: begin if (op_args.wctl.is_neg) `TRACE(level, ("PRED.N")); else `TRACE(level, ("PRED")); end
`INST_SFU_CSRRW: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRWI")); else `TRACE(level, ("CSRRW")); end
`INST_SFU_CSRRS: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRSI")); else `TRACE(level, ("CSRRS")); end
`INST_SFU_CSRRC: begin if (op_args.csr.use_imm) `TRACE(level, ("CSRRCI")); else `TRACE(level, ("CSRRC")); end
default: `TRACE(level, ("?"));
endcase
end
@ -347,24 +347,24 @@
endcase
endtask
task trace_op_mod(input int level,
input [`EX_BITS-1:0] ex_type,
input [`INST_OP_BITS-1:0] op_type,
input VX_gpu_pkg::op_mod_t op_mod
task trace_op_args(input int level,
input [`EX_BITS-1:0] ex_type,
input [`INST_OP_BITS-1:0] op_type,
input VX_gpu_pkg::op_args_t op_args
);
case (ex_type)
`EX_ALU: begin
`TRACE(level, (", use_PC=%b, use_imm=%b, imm=0x%0h", op_mod.alu.use_PC, op_mod.alu.use_imm, op_mod.alu.imm));
`TRACE(level, (", use_PC=%b, use_imm=%b, imm=0x%0h", op_args.alu.use_PC, op_args.alu.use_imm, op_args.alu.imm));
end
`EX_LSU: begin
`TRACE(level, (", offset=0x%0h", op_mod.lsu.offset));
`TRACE(level, (", offset=0x%0h", op_args.lsu.offset));
end
`EX_FPU: begin
`TRACE(level, (", fmt=0x%0h, frm=0x%0h", op_mod.fpu.fmt, op_mod.fpu.frm));
`TRACE(level, (", fmt=0x%0h, frm=0x%0h", op_args.fpu.fmt, op_args.fpu.frm));
end
`EX_SFU: begin
if (`INST_SFU_IS_CSR(op_type)) begin
`TRACE(level, (", addr=0x%0h, use_imm=%b, imm=0x%0h", op_mod.csr.addr, op_mod.csr.use_imm, op_mod.csr.imm));
`TRACE(level, (", addr=0x%0h, use_imm=%b, imm=0x%0h", op_args.csr.addr, op_args.csr.use_imm, op_args.csr.imm));
end
end
default:;

2
hw/rtl/core/VX_wctl_unit.sv
View file

@ -60,7 +60,7 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
wire [`XLEN-1:0] rs2_data = execute_if.data.rs2_data[tid];
`UNUSED_VAR (rs1_data)
wire not_pred = execute_if.data.op_mod.wctl.is_neg;
wire not_pred = execute_if.data.op_args.wctl.is_neg;
wire [NUM_LANES-1:0] taken;
for (genvar i = 0; i < NUM_LANES; ++i) begin

2
hw/rtl/interfaces/VX_decode_if.sv
View file

@ -22,7 +22,7 @@ interface VX_decode_if import VX_gpu_pkg::*; ();
logic [`PC_BITS-1:0] PC;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NR_BITS-1:0] rs1;

2
hw/rtl/interfaces/VX_dispatch_if.sv
View file

@ -21,7 +21,7 @@ interface VX_dispatch_if import VX_gpu_pkg::*; ();
logic [`NUM_THREADS-1:0] tmask;
logic [`PC_BITS-1:0] PC;
logic [`INST_ALU_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NT_WIDTH-1:0] tid;

2
hw/rtl/interfaces/VX_execute_if.sv
View file

@ -23,7 +23,7 @@ interface VX_execute_if import VX_gpu_pkg::*; #(
logic [NUM_LANES-1:0] tmask;
logic [`PC_BITS-1:0] PC;
logic [`INST_ALU_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NT_WIDTH-1:0] tid;

2
hw/rtl/interfaces/VX_ibuffer_if.sv
View file

@ -21,7 +21,7 @@ interface VX_ibuffer_if import VX_gpu_pkg::*; ();
logic [`PC_BITS-1:0] PC;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NR_BITS-1:0] rs1;

2
hw/rtl/interfaces/VX_operands_if.sv
View file

@ -22,7 +22,7 @@ interface VX_operands_if import VX_gpu_pkg::*; ();
logic [`PC_BITS-1:0] PC;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data;

2
hw/rtl/interfaces/VX_scoreboard_if.sv
View file

@ -22,7 +22,7 @@ interface VX_scoreboard_if import VX_gpu_pkg::*; ();
logic [`PC_BITS-1:0] PC;
logic [`EX_BITS-1:0] ex_type;
logic [`INST_OP_BITS-1:0] op_type;
op_mod_t op_mod;
op_args_t op_args;
logic wb;
logic [`NR_BITS-1:0] rd;
logic [`NR_BITS-1:0] rs1;