mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-22 21:09:15 -04:00
minor updates
This commit is contained in:
Blaise Tine
parent
310a8642b3
commit
a82ae7df59
8 changed files with 248 additions and 262 deletions
|
|
@ -40,15 +40,17 @@ ifeq ($(DEVICE_FAMILY), arria10)
|
|||
CONFIGS += -DALTERA_A10
|
||||
endif
|
||||
|
||||
CONFIGS_1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 $(CONFIGS)
|
||||
CONFIGS_2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 $(CONFIGS)
|
||||
CONFIGS_4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_16 := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_32 := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_64 := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_SEL := $(CONFIGS_$(NUM_CORES))
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
|
||||
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
|
||||
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
|
||||
|
|
@ -56,11 +58,11 @@ ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
|
|||
RTL_INCLUDE = -I$(RTL_DIR) -I$(DPI_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(IP_CACHE_DIR)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
|
||||
|
||||
# compilation flags
|
||||
CFLAGS += -DSYNTHESIS -DQUARTUS -DNOGLOBALS
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
CFLAGS += -DSYNTHESIS
|
||||
CFLAGS += -DQUARTUS
|
||||
|
||||
ifeq ($(TARGET), ase)
|
||||
CFLAGS += -DSIMULATION
|
||||
endif
|
||||
|
|
@ -94,7 +96,7 @@ vortex_afu.h: vortex_afu.json
|
|||
|
||||
setup:
|
||||
mkdir -p $(BUILD_DIR)/src
|
||||
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) $(CONFIGS_SEL) -DNOGLOBALS -F$(BUILD_DIR)/src -P -Osources.txt
|
||||
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -F$(BUILD_DIR)/src -P -Osources.txt
|
||||
ifeq ($(TARGET), ase)
|
||||
afu_sim_setup -f -s setup.cfg $(BUILD_DIR)
|
||||
else
|
||||
|
|
|
|||
|
|
@ -1,14 +1,42 @@
|
|||
|
||||
VIVADO = $(XILINX_VIVADO)/bin/vivado
|
||||
|
||||
all: create_project
|
||||
RTL_DIR = ../../../rtl
|
||||
AFU_DIR = $(RTL_DIR)/afu/xrt
|
||||
SCRIPT_DIR = ../../../scripts
|
||||
|
||||
create_project: project_1
|
||||
project_1: project_1.tcl
|
||||
$(VIVADO) -mode batch -source project_1.tcl
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
|
||||
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
|
||||
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
|
||||
ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
|
||||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache
|
||||
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
|
||||
RTL_INCLUDE += -Iproject_1_files
|
||||
|
||||
run:
|
||||
$(VIVADO) project_1/project_1.xpr &
|
||||
# compilation flags
|
||||
CFLAGS += -DSYNTHESIS -DVIVADO -DNOGLOBALS
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
COE_FILE := $(realpath project_1_files)/kernel.bin.coe
|
||||
ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')
|
||||
|
||||
all: build
|
||||
|
||||
gen-sources: project_1/sources.txt
|
||||
project_1/sources.txt:
|
||||
mkdir -p project_1
|
||||
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -EVX_fpu_fpnew.sv -Fproject_1/src -Oproject_1/sources.txt
|
||||
|
||||
project.tcl: project.tcl.in
|
||||
sed -e 's/%COE_FILE%/$(ESCAPED_COE_FILE)/g' < $< > $@
|
||||
|
||||
build: project_1/vortex.xpr
|
||||
project_1/vortex.xpr: project_1/sources.txt project.tcl
|
||||
$(VIVADO) -mode batch -source project.tcl -tclargs project_1/sources.txt project_1_files $(SCRIPT_DIR)
|
||||
|
||||
run: project_1/vortex.xpr
|
||||
$(VIVADO) project_1/vortex.xpr &
|
||||
|
||||
clean:
|
||||
rm -rf project_1
|
||||
rm -rf project_1 project.tcl
|
||||
|
|
|
|||
|
|
@ -1,26 +1,18 @@
|
|||
#*****************************************************************************************
|
||||
# Vivado (TM) v2020.2.2 (64-bit)
|
||||
#
|
||||
# project_1.tcl: Tcl script for re-creating project 'project_1'
|
||||
#
|
||||
# Generated by Vivado on Thu Sep 30 07:21:21 EDT 2021
|
||||
# IP Build 3115676 on Tue Feb 9 10:48:11 MST 2021
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
if { $::argc != 3 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 3 arguments!\n"
|
||||
puts "Usage: $::argv0 <vcs_file> <files_dir> <tool_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
set vcs_file [lindex $::argv 0]
|
||||
set files_dir [lindex $::argv 1]
|
||||
set tool_dir [lindex $::argv 2]
|
||||
|
||||
#puts $vcs_file
|
||||
#puts $files_dir
|
||||
#puts $tool_dir
|
||||
|
||||
set origin_dir [file normalize "."]
|
||||
set vortex_dir "/nethome/btine3/dev/vortex-gfx"
|
||||
|
||||
set path_to_hdl_vx "$vortex_dir/hw/rtl"
|
||||
set path_to_hdl_ip "$vortex_dir/hw/ip/xilinx"
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
|
|
@ -28,66 +20,26 @@ if { [info exists ::origin_dir_loc] } {
|
|||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "project_1"
|
||||
set project_name "project_1"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
set project_name $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "project_1.tcl"
|
||||
source "${tool_dir}/parse_vcs_list.tcl"
|
||||
set vlist [parse_vcs_list "${vcs_file}"]
|
||||
|
||||
# Help information for this script
|
||||
proc print_help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
set vsources_list [lindex $vlist 0]
|
||||
set vincludes_list [lindex $vlist 1]
|
||||
set vdefines_list [lindex $vlist 2]
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--help" { print_help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
set orig_proj_dir "[file normalize "$origin_dir/project_1"]"
|
||||
#puts ${vsources_list}
|
||||
#puts ${vincludes_list}
|
||||
#puts ${vdefines_list}
|
||||
|
||||
# Create project
|
||||
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xcu280-fsvh2892-2L-e
|
||||
create_project ${project_name} ./${project_name} -force -part xcu280-fsvh2892-2L-e
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
|
@ -95,15 +47,15 @@ set proj_dir [get_property directory [current_project]]
|
|||
# Set project properties
|
||||
set obj [current_project]
|
||||
set_property -name "board_part" -value "xilinx.com:au280:part0:1.1" -objects $obj
|
||||
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/activehdl" -objects $obj
|
||||
set_property -name "compxlib.activehdl_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/activehdl" -objects $obj
|
||||
set_property -name "compxlib.funcsim" -value "1" -objects $obj
|
||||
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/ies" -objects $obj
|
||||
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/modelsim" -objects $obj
|
||||
set_property -name "compxlib.ies_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/ies" -objects $obj
|
||||
set_property -name "compxlib.modelsim_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/modelsim" -objects $obj
|
||||
set_property -name "compxlib.overwrite_libs" -value "0" -objects $obj
|
||||
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/questa" -objects $obj
|
||||
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/riviera" -objects $obj
|
||||
set_property -name "compxlib.questa_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/questa" -objects $obj
|
||||
set_property -name "compxlib.riviera_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/riviera" -objects $obj
|
||||
set_property -name "compxlib.timesim" -value "1" -objects $obj
|
||||
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${_xil_proj_name_}.cache/compile_simlib/vcs" -objects $obj
|
||||
set_property -name "compxlib.vcs_compiled_library_dir" -value "$proj_dir/${project_name}.cache/compile_simlib/vcs" -objects $obj
|
||||
set_property -name "compxlib.xsim_compiled_library_dir" -value "" -objects $obj
|
||||
set_property -name "corecontainer.enable" -value "0" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
|
|
@ -112,7 +64,7 @@ set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
|||
set_property -name "generate_ip_upgrade_log" -value "1" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_interface_inference_priority" -value "" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
|
||||
set_property -name "legacy_ip_repo_paths" -value "" -objects $obj
|
||||
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
||||
set_property -name "platform.board_id" -value "au280" -objects $obj
|
||||
|
|
@ -127,7 +79,7 @@ set_property -name "platform.slrconstraintmode" -value "0" -objects $obj
|
|||
set_property -name "preferred_sim_model" -value "rtl" -objects $obj
|
||||
set_property -name "project_type" -value "Default" -objects $obj
|
||||
set_property -name "pr_flow" -value "0" -objects $obj
|
||||
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
||||
set_property -name "sim.central_dir" -value "$proj_dir/${project_name}.ip_user_files" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "sim.use_ip_compiled_libs" -value "1" -objects $obj
|
||||
set_property -name "simulator.activehdl_gcc_install_dir" -value "" -objects $obj
|
||||
|
|
@ -170,7 +122,13 @@ if {[string equal [get_filesets -quiet sources_1] ""]} {
|
|||
|
||||
# add source files
|
||||
set obj [get_filesets sources_1]
|
||||
add_files -verbose -fileset $obj [ glob $path_to_hdl_vx $path_to_hdl_ip $origin_dir/project_1_files ]
|
||||
add_files -norecurse -verbose -fileset $obj ${vsources_list}
|
||||
|
||||
# process defines
|
||||
set obj [get_filesets sources_1]
|
||||
foreach def $vdefines_list {
|
||||
set_property -name "verilog_define" -value $def -objects $obj
|
||||
}
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
|
|
@ -215,7 +173,7 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
|
|||
set obj [get_filesets sim_1]
|
||||
# Import local files from the original project
|
||||
set files [list \
|
||||
[file normalize "$origin_dir/project_1_files/testbench.v" ]\
|
||||
[file normalize "$files_dir/testbench.v" ]\
|
||||
]
|
||||
set imported_files [import_files -fileset sim_1 $files]
|
||||
|
||||
|
|
@ -304,7 +262,7 @@ set_property -name "name" -value "utils_1" -objects $obj
|
|||
proc cr_bd_design_1 { parentCell } {
|
||||
# The design that will be created by this Tcl proc contains the following
|
||||
# module references:
|
||||
# Vortex_axi_wrapper
|
||||
# Vortex_top
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
set design_name design_1
|
||||
|
|
@ -347,7 +305,7 @@ if { $bCheckIPs == 1 } {
|
|||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
Vortex_axi_wrapper\
|
||||
Vortex_top\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
|
|
@ -366,125 +324,126 @@ if { $bCheckIPs == 1 } {
|
|||
}
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
variable script_folder
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
# Create interface ports
|
||||
|
||||
# Create ports
|
||||
set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ]
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
set vx_busy [ create_bd_port -dir O vx_busy ]
|
||||
set vx_reset [ create_bd_port -dir I -type rst vx_reset ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_HIGH} \
|
||||
] $vx_reset
|
||||
# Create ports
|
||||
set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ]
|
||||
set resetn [ create_bd_port -dir I -type rst resetn ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $resetn
|
||||
set vx_busy [ create_bd_port -dir O vx_busy ]
|
||||
set vx_reset [ create_bd_port -dir I -type rst vx_reset ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_HIGH} \
|
||||
] $vx_reset
|
||||
|
||||
set dcr_wr_valid [ create_bd_port -dir I dcr_wr_valid ]
|
||||
set dcr_wr_addr [ create_bd_port -dir I -from 11 -to 0 dcr_wr_addr ]
|
||||
set dcr_wr_data [ create_bd_port -dir I -from 31 -to 0 dcr_wr_data ]
|
||||
set dcr_wr_valid [ create_bd_port -dir I dcr_wr_valid ]
|
||||
set dcr_wr_addr [ create_bd_port -dir I -from 11 -to 0 dcr_wr_addr ]
|
||||
set dcr_wr_data [ create_bd_port -dir I -from 31 -to 0 dcr_wr_data ]
|
||||
|
||||
# Create instance: Vortex_axi_wrapper_0, and set properties
|
||||
set block_name Vortex_axi_wrapper
|
||||
set block_cell_name Vortex_axi_wrapper_0
|
||||
if { [catch {set Vortex_axi_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $Vortex_axi_wrapper_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
# Create instance: Vortex_top_0, and set properties
|
||||
set block_name Vortex_top
|
||||
set block_cell_name Vortex_top_0
|
||||
if { [catch {set Vortex_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $Vortex_top_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: axi_bram_ctrl_0, and set properties
|
||||
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.ECC_TYPE {0} \
|
||||
] $axi_bram_ctrl_0
|
||||
# Create instance: axi_bram_ctrl_0, and set properties
|
||||
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.DATA_WIDTH {512} \
|
||||
CONFIG.ECC_TYPE {0} \
|
||||
] $axi_bram_ctrl_0
|
||||
|
||||
# Create instance: axi_bram_ctrl_0_bram, and set properties
|
||||
set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Assume_Synchronous_Clk {true} \
|
||||
CONFIG.Byte_Size {8} \
|
||||
CONFIG.Load_Init_File {true} \
|
||||
CONFIG.Coe_File {/nethome/btine3/dev/vortex-gfx/hw/syn/xilinx/test1/project_1_files/kernel.bin.coe} \
|
||||
CONFIG.EN_SAFETY_CKT {true} \
|
||||
CONFIG.Enable_32bit_Address {true} \
|
||||
CONFIG.Fill_Remaining_Memory_Locations {false} \
|
||||
CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
|
||||
CONFIG.Operating_Mode_A {NO_CHANGE} \
|
||||
CONFIG.Operating_Mode_B {READ_FIRST} \
|
||||
CONFIG.Port_B_Write_Rate {0} \
|
||||
CONFIG.Read_Width_A {512} \
|
||||
CONFIG.Read_Width_B {512} \
|
||||
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
|
||||
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
|
||||
CONFIG.Remaining_Memory_Locations {0} \
|
||||
CONFIG.Use_Byte_Write_Enable {true} \
|
||||
CONFIG.Use_RSTA_Pin {false} \
|
||||
CONFIG.Use_RSTB_Pin {true} \
|
||||
CONFIG.Write_Width_A {512} \
|
||||
CONFIG.Write_Depth_A {16384} \
|
||||
CONFIG.use_bram_block {Stand_Alone} \
|
||||
] $axi_bram_ctrl_0_bram
|
||||
# Create instance: axi_bram_ctrl_0_bram, and set properties
|
||||
set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Vortex_axi_wrapper_0_m_axi_mem [get_bd_intf_pins Vortex_axi_wrapper_0/m_axi_mem] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Assume_Synchronous_Clk {true} \
|
||||
CONFIG.Byte_Size {8} \
|
||||
CONFIG.Load_Init_File {true} \
|
||||
CONFIG.Coe_File {%COE_FILE%} \
|
||||
CONFIG.EN_SAFETY_CKT {true} \
|
||||
CONFIG.Enable_32bit_Address {true} \
|
||||
CONFIG.Fill_Remaining_Memory_Locations {false} \
|
||||
CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
|
||||
CONFIG.Operating_Mode_A {NO_CHANGE} \
|
||||
CONFIG.Operating_Mode_B {READ_FIRST} \
|
||||
CONFIG.Port_B_Write_Rate {0} \
|
||||
CONFIG.Read_Width_A {512} \
|
||||
CONFIG.Read_Width_B {512} \
|
||||
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
|
||||
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
|
||||
CONFIG.Remaining_Memory_Locations {0} \
|
||||
CONFIG.Use_Byte_Write_Enable {true} \
|
||||
CONFIG.Use_RSTA_Pin {false} \
|
||||
CONFIG.Use_RSTB_Pin {true} \
|
||||
CONFIG.Write_Width_A {512} \
|
||||
CONFIG.Write_Depth_A {16384} \
|
||||
CONFIG.use_bram_block {Stand_Alone} \
|
||||
] $axi_bram_ctrl_0_bram
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net Vortex_axi_wrapper_0_busy [get_bd_ports vx_busy] [get_bd_pins Vortex_axi_wrapper_0/busy]
|
||||
connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins Vortex_axi_wrapper_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
|
||||
connect_bd_net -net vx_reset_1 [get_bd_ports vx_reset] [get_bd_pins Vortex_axi_wrapper_0/reset]
|
||||
connect_bd_net -net dcr_wr_valid_1 [get_bd_ports dcr_wr_valid] [get_bd_pins Vortex_axi_wrapper_0/dcr_wr_valid]
|
||||
connect_bd_net -net dcr_wr_addr_1 [get_bd_ports dcr_wr_addr] [get_bd_pins Vortex_axi_wrapper_0/dcr_wr_addr]
|
||||
connect_bd_net -net dcr_wr_data_1 [get_bd_ports dcr_wr_data] [get_bd_pins Vortex_axi_wrapper_0/dcr_wr_data]
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Vortex_top_0_m_axi_mem [get_bd_intf_pins Vortex_top_0/m_axi_mem] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB]
|
||||
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces Vortex_axi_wrapper_0/m_axi_mem] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
# Create port connections
|
||||
connect_bd_net -net Vortex_top_0_busy [get_bd_ports vx_busy] [get_bd_pins Vortex_top_0/busy]
|
||||
connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins Vortex_top_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk]
|
||||
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
|
||||
connect_bd_net -net vx_reset_1 [get_bd_ports vx_reset] [get_bd_pins Vortex_top_0/reset]
|
||||
connect_bd_net -net dcr_wr_valid_1 [get_bd_ports dcr_wr_valid] [get_bd_pins Vortex_top_0/dcr_wr_valid]
|
||||
connect_bd_net -net dcr_wr_addr_1 [get_bd_ports dcr_wr_addr] [get_bd_pins Vortex_top_0/dcr_wr_addr]
|
||||
connect_bd_net -net dcr_wr_data_1 [get_bd_ports dcr_wr_data] [get_bd_pins Vortex_top_0/dcr_wr_data]
|
||||
|
||||
# Perform GUI Layout
|
||||
regenerate_bd_layout -layout_string {
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-195,-165",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
|
||||
# Create address segments
|
||||
assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces Vortex_top_0/m_axi_mem] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
|
||||
|
||||
# Perform GUI Layout
|
||||
regenerate_bd_layout -layout_string {
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-195,-165",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port clk_100MHz -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD
|
||||
preplace port resetn -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD
|
||||
|
|
@ -493,10 +452,10 @@ preplace port vx_reset -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
|
|||
preplace port dcr_wr_valid -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD
|
||||
preplace portBus dcr_wr_addr -pg 1 -lvl 0 -x 0 -y 150 -defaultsOSRD
|
||||
preplace portBus dcr_wr_data -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD
|
||||
preplace inst Vortex_axi_wrapper_0 -pg 1 -lvl 1 -x 190 -y 130 -defaultsOSRD
|
||||
preplace inst Vortex_top_0 -pg 1 -lvl 1 -x 190 -y 130 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 2 -x 520 -y 140 -defaultsOSRD
|
||||
preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 3 -x 800 -y 140 -defaultsOSRD
|
||||
preplace netloc Vortex_axi_wrapper_0_busy 1 1 3 360J 220 NJ 220 NJ
|
||||
preplace netloc Vortex_top_0_busy 1 1 3 360J 220 NJ 220 NJ
|
||||
preplace netloc clk_wiz_clk_out1 1 0 2 20 30 370
|
||||
preplace netloc resetn_1 1 0 2 NJ 20 380J
|
||||
preplace netloc vx_reset_1 1 0 1 NJ 110
|
||||
|
|
@ -505,7 +464,7 @@ preplace netloc dcr_wr_addr_1 1 0 1 NJ 150
|
|||
preplace netloc dcr_wr_data_1 1 0 1 NJ 170
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 1 N 150
|
||||
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 1 N 130
|
||||
preplace netloc Vortex_axi_wrapper_0_m_axi_mem 1 1 1 N 120
|
||||
preplace netloc Vortex_top_0_m_axi_mem 1 1 1 N 120
|
||||
levelinfo -pg 1 0 190 520 800 950
|
||||
pagesize -pg 1 -db -bbox -sgen -180 0 1060 240
|
||||
"
|
||||
|
|
@ -536,13 +495,8 @@ set_property USED_IN_SIMULATION "1" [get_files design_1.bd ]
|
|||
set_property USED_IN_SYNTHESIS "1" [get_files design_1.bd ]
|
||||
|
||||
#call make_wrapper to create wrapper files
|
||||
if { [get_property IS_LOCKED [ get_files -norecurse design_1.bd] ] == 1 } {
|
||||
import_files -fileset sources_1 [file normalize "$origin_dir/project_1_files/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" ]
|
||||
} else {
|
||||
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
|
||||
add_files -norecurse -fileset sources_1 $wrapper_path
|
||||
}
|
||||
|
||||
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
|
||||
add_files -norecurse -fileset sources_1 $wrapper_path
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
|
|
@ -2116,7 +2070,7 @@ set_property -name "steps.write_bitstream.args.more options" -value "" -objects
|
|||
# set the current impl run
|
||||
current_run -implementation [get_runs impl_1]
|
||||
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
puts "INFO: Project created:${project_name}"
|
||||
# Create 'drc_1' gadget (if not found)
|
||||
if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} {
|
||||
create_dashboard_gadget -name {drc_1} -type drc
|
||||
|
|
@ -21,6 +21,15 @@ RTL_DIR = ../../../../rtl
|
|||
AFU_DIR = $(RTL_DIR)/afu/xrt
|
||||
SCRIPT_DIR = ../../../../scripts
|
||||
|
||||
VIVADO = $(XILINX_VIVADO)/bin/vivado
|
||||
VPP = $(XILINX_VITIS)/bin/v++
|
||||
CP = cp -rf
|
||||
RMDIR = rm -rf
|
||||
ECHO = @echo
|
||||
|
||||
NCPUS := $(shell grep -c ^processor /proc/cpuinfo)
|
||||
JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) )))
|
||||
|
||||
PLATFORM_TO_XSA = $(strip $(patsubst %.xpfm, % , $(shell basename $(PLATFORM))))
|
||||
XSA := $(call PLATFORM_TO_XSA, $(PLATFORM))
|
||||
|
||||
|
|
@ -30,6 +39,9 @@ CPU_TYPE := $(shell platforminfo -p $(PLATFORM) | grep 'CPU Type' | sed 's/.*://
|
|||
BUILD_DIR = $(PREFIX)_$(XSA)_$(TARGET)
|
||||
BIN_DIR = $(BUILD_DIR)/bin
|
||||
|
||||
XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
|
||||
XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
|
||||
|
||||
# Control RTL debug tracing states
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_PIPELINE
|
||||
DBG_TRACE_FLAGS += -DDBG_TRACE_CORE_ICACHE
|
||||
|
|
@ -52,6 +64,17 @@ CHIPSCOPE_FLAGS += -DCHIPSCOPE_LSU
|
|||
CHIPSCOPE_FLAGS += -DCHIPSCOPE_RASTER
|
||||
CHIPSCOPE_FLAGS += -DCHIPSCOPE_MSCHED
|
||||
|
||||
# cluster configuration
|
||||
CONFIGS_1c := -DNUM_CLUSTERS=1 -DNUM_CORES=1
|
||||
CONFIGS_2c := -DNUM_CLUSTERS=1 -DNUM_CORES=2
|
||||
CONFIGS_4c := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE
|
||||
CONFIGS_8c := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE
|
||||
CONFIGS_16c := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_32c := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
|
||||
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
|
||||
|
||||
# include paths
|
||||
FPU_INCLUDE = -I$(RTL_DIR)/fpu_unit
|
||||
TEX_INCLUDE = -I$(RTL_DIR)/tex_unit
|
||||
RASTER_INCLUDE = -I$(RTL_DIR)/raster_unit
|
||||
|
|
@ -59,23 +82,10 @@ ROP_INCLUDE = -I$(RTL_DIR)/rop_unit
|
|||
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR)
|
||||
RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
|
||||
|
||||
CONFIGS += -DSYNTHESIS -DVIVADO
|
||||
|
||||
VIVADO = $(XILINX_VIVADO)/bin/vivado
|
||||
|
||||
VPP = $(XILINX_VITIS)/bin/v++
|
||||
|
||||
CP = cp -rf
|
||||
RMDIR = rm -rf
|
||||
|
||||
ECHO = @echo
|
||||
|
||||
XO_CONTAINER = $(BIN_DIR)/vortex_afu.xo
|
||||
|
||||
XCLBIN_CONTAINER = $(BIN_DIR)/vortex_afu.xclbin
|
||||
|
||||
NCPUS := $(shell grep -c ^processor /proc/cpuinfo)
|
||||
JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) )))
|
||||
# compilation flags
|
||||
CFLAGS += -DSYNTHESIS -DVIVADO -DNOGLOBALS
|
||||
CFLAGS += $(CONFIGS)
|
||||
CFLAGS += $(RTL_INCLUDE)
|
||||
|
||||
# Kernel compiler global settings
|
||||
VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
|
||||
|
|
@ -95,7 +105,7 @@ VPP_FLAGS += --config ../vitis.ini
|
|||
|
||||
# Enable perf counters
|
||||
ifdef PERF
|
||||
CONFIGS += -DPERF_ENABLE
|
||||
CFLAGS += -DPERF_ENABLE
|
||||
endif
|
||||
|
||||
# Generates profile summary report
|
||||
|
|
@ -109,14 +119,14 @@ ifdef DEBUG
|
|||
VPP_FLAGS += -g --optimize 0 --debug.protocol all
|
||||
ifeq ($(TARGET), hw)
|
||||
VPP_FLAGS += --debug.chipscope vortex_afu_1
|
||||
CONFIGS += -DCHIPSCOPE $(CHIPSCOPE_FLAGS)
|
||||
CFLAGS += -DCHIPSCOPE $(CHIPSCOPE_FLAGS)
|
||||
else
|
||||
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
|
||||
CONFIGS += -DSIMULATION $(DBG_TRACE_FLAGS)
|
||||
CFLAGS += -DSIMULATION $(DBG_TRACE_FLAGS)
|
||||
endif
|
||||
else
|
||||
CONFIGS += -DNDEBUG
|
||||
VPP_FLAGS += --optimize 3
|
||||
VPP_FLAGS += --optimize 3
|
||||
CFLAGS += -DNDEBUG
|
||||
endif
|
||||
|
||||
# RTL Kernel only supports Hardware and Hardware Emulation.
|
||||
|
|
@ -124,25 +134,16 @@ ifneq ($(TARGET),$(findstring $(TARGET), hw hw_emu))
|
|||
$(warning WARNING:Application supports only hw hw_emu TARGET. Please use the target for running the application)
|
||||
endif
|
||||
|
||||
CONFIGS_1 := -DNUM_CLUSTERS=1 -DNUM_CORES=1 $(CONFIGS)
|
||||
CONFIGS_2 := -DNUM_CLUSTERS=1 -DNUM_CORES=2 $(CONFIGS)
|
||||
CONFIGS_4 := -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_8 := -DNUM_CLUSTERS=1 -DNUM_CORES=8 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_16 := -DNUM_CLUSTERS=1 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_32 := -DNUM_CLUSTERS=2 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_64 := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE $(CONFIGS)
|
||||
CONFIGS_SEL := $(CONFIGS_$(NUM_CORES))
|
||||
|
||||
.PHONY: all clean gen-sources emconfig check-devices
|
||||
|
||||
all: check-devices emconfig $(XCLBIN_CONTAINER)
|
||||
|
||||
gen-sources: $(BUILD_DIR)/sources.txt
|
||||
$(BUILD_DIR)/sources.txt:
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(RTL_INCLUDE) $(CONFIGS_SEL) -DNOGLOBALS -EVX_fpu_fpnew.sv -Fsrc -P -Osources.txt
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -EVX_fpu_fpnew.sv -Fsrc -P -Osources.txt
|
||||
|
||||
$(XO_CONTAINER): $(BUILD_DIR)/sources.txt ./kernel.xml
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source ../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt ../kernel.xml ../$(BUILD_DIR)
|
||||
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source ../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt ../kernel.xml $(SCRIPT_DIR) ../$(BUILD_DIR)
|
||||
|
||||
$(XCLBIN_CONTAINER): $(XO_CONTAINER)
|
||||
mkdir -p $(BIN_DIR); cd $(BUILD_DIR); $(VPP) $(VPP_FLAGS) -o ../$(XCLBIN_CONTAINER) ../$(XO_CONTAINER)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
if { $::argc != 5 } {
|
||||
if { $::argc != 6 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n"
|
||||
puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <kernel_xml> <build_dir>\n"
|
||||
puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <kernel_xml> <tool_dir> <build_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
|
|
@ -8,7 +8,8 @@ set xoname [lindex $::argv 0]
|
|||
set krnl_name [lindex $::argv 1]
|
||||
set vcs_file [lindex $::argv 2]
|
||||
set krnl_xml [lindex $::argv 3]
|
||||
set build_dir [lindex $::argv 4]
|
||||
set tool_dir [lindex $::argv 4]
|
||||
set build_dir [lindex $::argv 5]
|
||||
|
||||
set script_path [ file dirname [ file normalize [ info script ] ] ]
|
||||
|
||||
|
|
@ -20,8 +21,8 @@ set argv [list ${build_dir}/ip]
|
|||
set argc 1
|
||||
source ${script_path}/gen_ip.tcl
|
||||
|
||||
set argv [list ${krnl_name} ${build_dir}]
|
||||
set argc 2
|
||||
set argv [list ${krnl_name} ${vcs_file} ${tool_dir} ${build_dir}]
|
||||
set argc 4
|
||||
source ${script_path}/package_kernel.tcl
|
||||
|
||||
package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory "${build_dir}/xo/packaged_kernel" -kernel_xml ${krnl_xml}
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
if { $::argc != 2 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 2 arguments!\n"
|
||||
puts "Usage: $::argv0 <krnl_name> <build_dir>\n"
|
||||
if { $::argc != 4 } {
|
||||
puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
|
||||
puts "Usage: $::argv0 <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
|
||||
exit
|
||||
}
|
||||
|
||||
set krnl_name [lindex $::argv 0]
|
||||
set build_dir [lindex $::argv 1]
|
||||
|
||||
set script_path [ file dirname [ file normalize [ info script ] ] ]
|
||||
set vcs_file [lindex $::argv 1]
|
||||
set tool_dir [lindex $::argv 2]
|
||||
set build_dir [lindex $::argv 3]
|
||||
|
||||
set path_to_packaged "${build_dir}/xo/packaged_kernel"
|
||||
set path_to_tmp_project "${build_dir}/xo/project"
|
||||
|
||||
source "${script_path}/parse_vcs_list.tcl"
|
||||
source "${tool_dir}/parse_vcs_list.tcl"
|
||||
set vlist [parse_vcs_list "${vcs_file}"]
|
||||
|
||||
set vsources_list [lindex $vlist 0]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue