Synthesis Cleanup 1

rtl/VX_define.v

@@ -115,6 +115,7 @@
 
 `define ZERO_REG 5'h0
 
+// `define PARAM
 
 // Offset
 `define CACHE_OFFSET_NB ($clog2(NUM_WORDS_PER_BLOCK))

rtl/VX_gpr_wrapper.v

@@ -17,7 +17,9 @@ module VX_gpr_wrapper (
 
 	wire[`NT_M1:0][31:0] jal_data;
 	genvar index;
-	for (index = 0; index <= `NT_M1; index = index + 1) assign jal_data[index] = VX_gpr_jal.curr_PC;
+	for (index = 0; index <= `NT_M1; index = index + 1) begin
+		assign jal_data[index] = VX_gpr_jal.curr_PC;
+	end
 
 
 	assign out_a_reg_data = (VX_gpr_jal.is_jal   ? jal_data :  (temp_a_reg_data[VX_gpr_read.warp_num]));

rtl/VX_warp_scheduler.v

@@ -122,7 +122,7 @@ module VX_warp_scheduler (
 			visible_active[0]     <= 1; // Activating first warp
 			thread_masks[0]       <= 1; // Activating first thread in first warp
 			warp_stalled          <= 0;
-			total_barrier_stall    = 0;
+			// total_barrier_stall    = 0;
 			for (curr_w_help = 1; curr_w_help < `NW; curr_w_help=curr_w_help+1) begin
 				warp_pcs[curr_w_help]        <= 0;
 				warp_active[curr_w_help]     <= 0; // Activating first warp
@@ -217,14 +217,15 @@ module VX_warp_scheduler (
 
 	assign wstall_this_cycle = wstall && (wstall_warp_num == warp_to_schedule); // Maybe bug
 
-	integer curr_b;
-	always @(*) begin
-		total_barrier_stall = 0;
-		for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1)
-		begin
-			total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b[($clog2(`NUM_BARRIERS)-1):0]][`NW-1:0];
-		end
-	end
+	assign total_barrier_stall = barrier_stall_mask[0] | barrier_stall_mask[1] | barrier_stall_mask[2] | barrier_stall_mask[3];
+	// integer curr_b;
+	// always @(*) begin
+	// 	total_barrier_stall = 0;
+	// 	for (curr_b = 0; curr_b < `NUM_BARRIERS; curr_b=curr_b+1)
+	// 	begin
+	// 		total_barrier_stall[`NW-1:0] = total_barrier_stall[`NW-1:0] | barrier_stall_mask[curr_b];
+	// 	end
+	// end
 
 
 	assign update_visible_active = (count_visible_active < 1) && !(stall || wstall_this_cycle || hazard || is_join);

rtl/Vortex.v

@@ -8,8 +8,7 @@ module Vortex
       parameter CACHE_WAYS     = 1,
       parameter CACHE_BLOCK    = 128, // Bytes
       parameter CACHE_BANKS    = 8,
-	localparam NUMBER_BANKS        = 8,
-	localparam NUM_WORDS_PER_BLOCK = 4
+      parameter NUM_WORDS_PER_BLOCK = 4
     )
 	(
 	input  wire           clk,
@@ -23,15 +22,17 @@ module Vortex
     output reg [31:0]  o_m_read_addr,
     output reg [31:0]  o_m_evict_addr,
     output reg         o_m_valid,
-    output reg [31:0]  o_m_writedata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
+    output reg [31:0]  o_m_writedata[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
     output reg         o_m_read_or_write,
 
     // Rsp
-    input  wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
+    input  wire [31:0] i_m_readdata[CACHE_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
     input  wire        i_m_ready,
 	output wire        out_ebreak
 	);
 
+
+
 wire memory_delay;
 wire gpr_stage_delay;
 wire schedule_delay;
@@ -58,7 +59,7 @@ assign VX_dram_req_rsp.i_m_ready = i_m_ready;
 
 genvar curr_bank;
 genvar curr_word;
-for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin
+for (curr_bank = 0; curr_bank < CACHE_BANKS; curr_bank = curr_bank + 1) begin
 
 	for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
 		assign o_m_writedata[curr_bank][curr_word]                = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];

rtl/byte_enabled_simple_dual_port_ram.v

@@ -25,7 +25,7 @@ module byte_enabled_simple_dual_port_ram
 	integer ini;
 	always@(posedge clk, posedge reset) begin
 		if (reset) begin
-			for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] = 0;
+			for (ini = 0; ini < 32; ini = ini + 1) GPR[ini] <= 0;
 		end else if(we) begin
 			integer thread_ind;
 			for (thread_ind = 0; thread_ind <= `NT_M1; thread_ind = thread_ind + 1) begin

rtl/cache/VX_cache_data.v

@@ -13,20 +13,37 @@ module VX_cache_data
     (
 	input wire clk, rst,    // Clock
 
-	// Addr
-	input wire[`CACHE_IND_SIZE_RNG] addr,
-	// WE
-	input wire[NUM_WORDS_PER_BLOCK-1:0][3:0]   we,
-	input wire                             evict,
-	// Data
-	input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write, // Update Data
-	input wire[`CACHE_TAG_SIZE_RNG]                           tag_write,
+    `ifdef PARAM
+    	// Addr
+    	input wire[`CACHE_IND_SIZE_RNG]          addr,
+    	// WE
+    	input wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we,
+    	input wire                               evict,
+    	// Data
+    	input wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write,
+    	input wire[`CACHE_TAG_SIZE_RNG]                           tag_write,
 
 
-	output wire[`CACHE_TAG_SIZE_RNG]           tag_use,
-	output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
-	output wire                                 valid_use,
-	output wire                                 dirty_use
+    	output wire[`CACHE_TAG_SIZE_RNG]            tag_use,
+    	output wire[NUM_WORDS_PER_BLOCK-1:0][31:0]  data_use,
+    	output wire                                 valid_use,
+    	output wire                                 dirty_use
+    `else 
+        // Addr
+        input wire[7:0]                            addr,
+        // WE
+        input wire[NUM_WORDS_PER_BLOCK-1:0][3:0]   we,
+        input wire                                 evict,
+        // Data
+        input wire[NUM_WORDS_PER_BLOCK-1:0][31:0]  data_write, // Update Data
+        input wire[16:0]                           tag_write,
+
+
+        output wire[16:0]                          tag_use,
+        output wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_use,
+        output wire                                valid_use,
+        output wire                                dirty_use
+    `endif
 	
 );
 
@@ -61,10 +78,10 @@ module VX_cache_data
         always @(posedge clk, posedge rst) begin : update_all
           if (rst) begin
             for (ini_ind = 0; ini_ind < NUMBER_INDEXES; ini_ind=ini_ind+1) begin
-                data[ini_ind]  = 0;
-                tag[ini_ind]   = 0;
-                valid[ini_ind] = 0;
-                dirty[ini_ind] = 0;
+                data[ini_ind]  <= 0;
+                tag[ini_ind]   <= 0;
+                valid[ini_ind] <= 0;
+                dirty[ini_ind] <= 0;
             end
           end else begin
               if (update_dirty) dirty[addr] <= dirt_new; // WRite Port

rtl/cache/VX_d_cache.v

@@ -146,14 +146,21 @@ module VX_d_cache
           .found (valid_per_bank[bid])
           );
 
-        always @(*) begin
-          if (use_write_final_data) new_final_data_read[use_thread_index] = use_data_final_data;
-        end
-        // assign new_final_data_read[use_thread_index] = use_write_final_data ? use_data_final_data : 0;
         assign debug_hit_per_bank_mask[bid]   = {NUM_REQ{hit_per_bank[bid]}};
         assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
     end
 
+    integer test_bid;
+    always @(*) begin
+      new_final_data_read = 0;
+      for (test_bid=0; test_bid < NUMBER_BANKS; test_bid=test_bid+1)
+      begin
+          if (hit_per_bank[test_bid]) begin
+            new_final_data_read[index_per_bank[test_bid]] = readdata_per_bank[test_bid];
+          end
+      end
+    end
+
 
     wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
     assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
@@ -212,7 +219,7 @@ module VX_d_cache
   always @(posedge clk, posedge rst) begin
     if (rst) begin
       final_data_read         <= 0;
-      new_final_data_read      = 0;
+      // new_final_data_read      = 0;
       state                   <= 0;
       stored_valid            <= 0;
       // eviction_addr_per_bank  <= 0;

rtl/shared_memory/VX_priority_encoder_sm.v

@@ -104,7 +104,7 @@ module VX_priority_encoder_sm
 	always @(posedge clk, posedge reset) begin
 		if (reset) begin
 			left_requests <= 0;
-			serviced       = 0;
+			// serviced       = 0;
 		end else begin
 			if (!stall)    left_requests <= 0;
 			else           left_requests <= new_left_requests;

rtl/shared_memory/VX_shared_memory_block.v

@@ -21,7 +21,7 @@ module VX_shared_memory_block (
 			if (reset) begin
 				for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
 				begin
-					shared_memory[curr_ind] = 0;
+					shared_memory[curr_ind] <= 0;
 				end
 			end else if(shm_write) begin
 				if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0]; 

syn/Makefile

@@ -4,4 +4,4 @@ all: syn
 
 
 syn:
-	dc_shell-t -f fsyn.tcl
+	dc_shell-t -f fsyn.tcl 2>&1 | tee vortex_syn.log

syn/fsyn.tcl

@@ -4,6 +4,8 @@ set symbol_library		{}
 set target_library		[concat NanGate_15nm_OCL.db]
 set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
 					]
+# set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
+# 					]
 
 set top_level Vortex
 analyze -format sverilog $verilog_files