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minor tweaks to appease quartus

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re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
This commit is contained in:
wgulian3 2020-03-10 04:05:01 -04:00
parent ca62e57a0d
commit a931b588c2
5 changed files with 23 additions and 20 deletions
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2
rtl/Makefile
View file

@ -19,7 +19,7 @@ LIGHTW=-Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
CF=-CFLAGS '-std=c++11 -O3'
CF=-CFLAGS '-std=c++11 -fms-extensions'
DEB=--trace --prof-cfuncs -DVL_DEBUG=1

16
rtl/VX_cache/VX_bank.v
View file

@ -296,17 +296,19 @@ module VX_bank
);
wire stall_bank_pipe;
reg is_fill_in_pipe;
reg is_fill_in_pipe;
genvar p_stage;
reg[16:0] p_stage;
always @(*) begin
assign is_fill_in_pipe = 0;
is_fill_in_pipe = 0;
for (p_stage = 0; p_stage < STAGE_1_CYCLES; p_stage=p_stage+1) begin
if (is_fill_st1[p_stage]) assign is_fill_in_pipe = 1;
if (is_fill_st1[p_stage]) is_fill_in_pipe = 1;
end
if (is_fill_st2) assign is_fill_in_pipe = 1;
if (is_fill_st2) is_fill_in_pipe = 1;
end
// assign is_fill_in_pipe = (|is_fill_st1) || is_fill_st2;
assign dfpq_pop = !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
@ -630,7 +632,7 @@ module VX_bank
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
endmodule
endmodule : VX_bank

8
rtl/VX_define.v
View file

@ -146,7 +146,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define DNUMBER_REQUESTS `NT
// Number of cycles to complete stage 1 (read from memory)
`define DSTAGE_1_CYCLES 2
`define DSTAGE_1_CYCLES 4
// Function ID
`define DFUNC_ID 0
@ -199,7 +199,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define INUMBER_REQUESTS 1
// Number of cycles to complete stage 1 (read from memory)
`define ISTAGE_1_CYCLES 2
`define ISTAGE_1_CYCLES 4
// Function ID
`define IFUNC_ID 1
@ -251,7 +251,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define SNUMBER_REQUESTS `NT
// Number of cycles to complete stage 1 (read from memory)
`define SSTAGE_1_CYCLES 2
`define SSTAGE_1_CYCLES 4
// Function ID
`define SFUNC_ID 2
@ -305,7 +305,7 @@
// Number of Word requests per cycle {1, 2, 4, 8, ...}
`define LLNUMBER_REQUESTS (2*`NUMBER_CORES_PER_CLUSTER)
// Number of cycles to complete stage 1 (read from memory)
`define LLSTAGE_1_CYCLES 2
`define LLSTAGE_1_CYCLES 4
// Function ID
`define LLFUNC_ID 3

15
rtl/quartus/Makefile
View file

@ -32,26 +32,27 @@ smart: smart.log
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
$(QUARTUS_ROOT)/quartus/bin/quartus_sta -t VX_timing.tcl
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
$(QUARTUS_ROOT)/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat"
$(QUARTUS_ROOT)/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc vortex.sdc -inc "..;../interfaces;../pipe_regs;../cache;../VX_cache;../shared_memory;../compat"
syn.chg:
$(STAMP) syn.chg
@ -66,7 +67,7 @@ asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
$(QUARTUS_ROOT)/quartus/bin/quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

2
rtl/quartus/VX_timing.tcl
View file

@ -10,7 +10,7 @@ update_timing_netlist
foreach_in_collection op [get_available_operating_conditions] {
set_operating_conditions $op
report_timing -setup -npaths 20 -detail full_path -multi_corner \
report_timing -setup -npaths 150 -detail full_path -multi_corner -pairs_only -nworst 8 \
-file "bin/timing_paths_$op.html" \
-panel_name "Critical paths for $op"