minor updates

hw/rtl/VX_config.vh

@@ -824,4 +824,4 @@
 `define L3_NUM_WAYS 4
 `endif
 
-`endif
+`endif // VX_CONFIG_VH

hw/rtl/VX_define.vh

@@ -33,10 +33,12 @@
 
 `define PERF_CTR_BITS   44
 
-`ifdef SIMULATION
+`ifndef NDEBUG
+`ifdef VIVADO
+`define UUID_BITS       19
+`else
 `define UUID_BITS       44
-`elsif CHIPSCOPE 
-`define UUID_BITS       12
+`endif
 `else
 `define UUID_BITS       0
 `endif
@@ -472,4 +474,4 @@
     `REDUCE_ADD (dst, src, mem_stalls, `PERF_CTR_BITS, count); \
     `REDUCE_ADD (dst, src, crsp_stalls, `PERF_CTR_BITS, count)
 
-`endif
+`endif // VX_DEFINE_VH

hw/rtl/VX_gpu_types.vh

@@ -269,4 +269,4 @@ endpackage
 `define GPU_SPLIT_BITS      $bits(VX_gpu_types::gpu_split_t)
 `define GPU_BARRIER_BITS    $bits(VX_gpu_types::gpu_barrier_t)
 
-`endif
+`endif // VX_GPU_TYPES_VH

hw/rtl/VX_platform.vh

@@ -244,4 +244,4 @@
 `define REPEAT_COMMA ,
 `define REPEAT_SEMICOLON ;
 
-`endif
+`endif // VX_PLATFORM_VH

hw/rtl/VX_scope.vh

@@ -96,4 +96,5 @@
 `define SCOPE_ASSIGN(d,s)
 
 `endif
-`endif
+
+`endif // VX_SCOPE_VH

hw/rtl/VX_trace_info.vh

@@ -161,4 +161,4 @@ task trace_base_dcr (
     endcase  
 endtask
 
-`endif
+`endif // VX_TRACE_INFO_VH

hw/rtl/VX_types.vh

@@ -425,4 +425,4 @@
 `define DCR_ROP_STATE(addr)         ((addr) - `DCR_ROP_STATE_BEGIN)
 `define DCR_ROP_STATE_COUNT         (`DCR_ROP_STATE_END-`DCR_ROP_STATE_BEGIN)
 
-`endif
+`endif // VX_TYPES_VH

hw/rtl/afu/opae/vortex_afu.sv

@@ -1,12 +1,8 @@
-`include "VX_platform.vh"
-`ifdef NOPAE
-`IGNORE_WARNINGS_BEGIN
-`include "vortex_afu.vh"
-`IGNORE_WARNINGS_END
-`else
+`ifndef NOPAE
 `include "afu_json_info.vh"
+`else
+`include "vortex_afu.vh"
 `endif
-
 `include "VX_define.vh"
 `include "VX_gpu_types.vh"
 

hw/rtl/afu/opae/vortex_afu.vh

@@ -45,4 +45,4 @@
 `define AFU_IMAGE_POWER 0
 `define AFU_TOP_IFC "ccip_std_afu_avalon_mm"
 
-`endif
+`endif // VORTEX_AFU_VH

hw/rtl/afu/xrt/vortex_afu.vh

@@ -94,4 +94,4 @@
 	assign m_axi_mem_bresp_a[i] = m``i``_axi_mem_bresp; \
 	assign m_axi_mem_bid_a[i] = m``i``_axi_mem_bid
 
-`endif
+`endif // VORTEX_AFU_VH

hw/rtl/cache/VX_cache_define.vh

@@ -66,4 +66,4 @@
 
 `define TO_FULL_ADDR(x)         {x, (32-$bits(x))'(0)}
 
-`endif
+`endif // VX_CACHE_DEFINE_VH

hw/rtl/core/VX_warp_sched.sv

@@ -251,10 +251,10 @@ module VX_warp_sched #(
 
     assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid];    
 
-`ifdef SIMULATION
+`ifndef NDEBUG
     assign instr_uuid = (issued_instrs[schedule_wid] * `NUM_WARPS * `NUM_CORES * `NUM_CLUSTERS)
-                      + (`NUM_WARPS * CORE_ID)
-                      + `UUID_BITS'(schedule_wid);
+                      + UUID_WIDTH'(`NUM_WARPS * CORE_ID)
+                      + UUID_WIDTH'(schedule_wid);
 `else
     assign instr_uuid = '0;
 `endif

hw/rtl/fpu_unit/VX_fpu_define.vh

@@ -13,4 +13,4 @@
 import VX_fpu_types::*;
 `IGNORE_WARNINGS_END
 
-`endif
+`endif // VX_FPU_DEFINE_VH

hw/rtl/fpu_unit/VX_fpu_types.vh

@@ -28,4 +28,4 @@ endpackage
 `define FP_CLASS_BITS   $bits(VX_fpu_types::fclass_t)
 `define FP_FLAGS_BITS   $bits(VX_fpu_types::fflags_t)
 
-`endif
+`endif // VX_FPU_TYPES_VH

hw/rtl/raster_unit/VX_raster_define.vh

@@ -63,4 +63,4 @@ endtask
     `REDUCE_ADD (dst, src, mem_latency, `PERF_CTR_BITS, count); \
     `REDUCE_ADD (dst, src, stall_cycles, `PERF_CTR_BITS, count)
 
-`endif
+`endif // VX_RASTER_DEFINE_VH

hw/rtl/raster_unit/VX_raster_types.vh

@@ -35,4 +35,4 @@ typedef struct packed {
 
 endpackage
 
-`endif
+`endif // VX_RASTER_TYPES_VH

hw/rtl/rop_unit/VX_rop_define.vh

@@ -54,4 +54,4 @@ endtask
     `REDUCE_ADD (dst, src, mem_latency, `PERF_CTR_BITS, count); \
     `REDUCE_ADD (dst, src, stall_cycles, `PERF_CTR_BITS, count)
 
-`endif
+`endif // VX_ROP_DEFINE_VH

hw/rtl/rop_unit/VX_rop_types.vh

@@ -56,4 +56,4 @@ typedef struct packed {
 
 endpackage
 
-`endif
+`endif // VX_ROP_TYPES_VH

hw/rtl/tex_unit/VX_tex_define.vh

@@ -39,4 +39,4 @@ endtask
     `REDUCE_ADD (dst, src, mem_latency, `PERF_CTR_BITS, count); \
     `REDUCE_ADD (dst, src, stall_cycles, `PERF_CTR_BITS, count)
 
-`endif
+`endif // VX_TEX_DEFINE_VH

hw/rtl/tex_unit/VX_tex_types.vh

@@ -37,4 +37,4 @@ typedef struct packed {
 
 endpackage
 
-`endif
+`endif // VX_TEX_TYPES_VH

hw/syn/xilinx/test/project_1_files/globals.vh

@@ -14,5 +14,5 @@
 `define IO_ADDR_SIZE    (32'hFFFFF - `IO_BASE_ADDR + 1)
 `define IO_COUT_ADDR    (32'hFFFFF - `MEM_BLOCK_SIZE + 1)
 
-`endif
+`endif // GLOBALS_VH