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Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile

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This commit is contained in:
Santosh Srivatsan 2022-01-22 13:47:44 -05:00
parent 91c22a2592
commit ad92c09f5b
10 changed files with 77 additions and 60 deletions
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7
sim/simx/Makefile
View file

@ -31,6 +31,13 @@ else
CXXFLAGS += -O2 -DNDEBUG
endif
# XLEN parameterization
ifdef XLEN
CXXFLAGS += -DXLEN=$(XLEN)
else
CXXFLAGS += -DXLEN=32
endif
PROJECT = simx
all: $(DESTDIR)/$(PROJECT)

6
sim/simx/core.cpp
View file

@ -406,8 +406,8 @@ Word Core::icache_read(Addr addr, Size size) {
return data;
}
DWord Core::dcache_read(Addr addr, Size size) {
DWord data;
XWord Core::dcache_read(Addr addr, Size size) {
XWord data;
auto type = get_addr_type(addr, size);
if (type == AddrType::Shared) {
smem_.read(&data, addr & (SMEM_SIZE-1), size);
@ -417,7 +417,7 @@ DWord Core::dcache_read(Addr addr, Size size) {
return data;
}
void Core::dcache_write(Addr addr, DWord data, Size size) {
void Core::dcache_write(Addr addr, XWord data, Size size) {
if (addr >= IO_COUT_ADDR
&& addr <= (IO_COUT_ADDR + IO_COUT_SIZE - 1)) {
this->writeToStdOut(addr, data);

4
sim/simx/core.h
View file

@ -109,9 +109,9 @@ public:
Word icache_read(Addr, Size);
DWord dcache_read(Addr, Size);
XWord dcache_read(Addr, Size);
void dcache_write(Addr, DWord, Size);
void dcache_write(Addr, XWord, Size);
Word tex_read(uint32_t unit, Word lod, Word u, Word v, std::vector<mem_addr_size_t>* mem_addrs);

8
sim/simx/decode.cpp
View file

@ -52,7 +52,7 @@ static const char* op_string(const Instr &instr) {
Word func3 = instr.getFunc3();
Word func7 = instr.getFunc7();
Word rs2 = instr.getRSrc(1);
DWord imm = instr.getImm();
XWord imm = instr.getImm();
switch (opcode) {
case Opcode::NOP: return "NOP";
@ -517,7 +517,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
instr->setSrcReg(rs2);
}
instr->setFunc3(func3);
DWord imm = (func7 << reg_s_) | rd;
XWord imm = (func7 << reg_s_) | rd;
instr->setImm(sext64(imm, 12));
} break;
@ -529,7 +529,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
Word bits_4_1 = rd >> 1;
Word bit_10_5 = func7 & 0x3f;
Word bit_12 = func7 >> 6;
DWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
XWord imm = (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
instr->setImm(sext64(imm, 13));
} break;
@ -545,7 +545,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code) const {
Word bit_11 = (unordered >> 8) & 0x1;
Word bits_10_1 = (unordered >> 9) & 0x3ff;
Word bit_20 = (unordered >> 19) & 0x1;
DWord imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
XWord imm = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
if (bit_20) {
imm |= ~j_imm_mask_;
}

72
sim/simx/execute.cpp
View file

@ -16,7 +16,7 @@
using namespace vortex;
static bool HasDivergentThreads(const ThreadMask &thread_mask,
const std::vector<std::vector<DWord>> &reg_file,
const std::vector<std::vector<XWord>> &reg_file,
unsigned reg) {
bool cond;
size_t thread_idx = 0;
@ -52,7 +52,7 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
assert(tmask_.any());
DWord nextPC = PC_ + core_->arch().wsize();
XWord nextPC = PC_ + core_->arch().wsize();
Word func2 = instr.getFunc2();
Word func3 = instr.getFunc3();
@ -64,13 +64,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
int rsrc0 = instr.getRSrc(0);
int rsrc1 = instr.getRSrc(1);
int rsrc2 = instr.getRSrc(2);
DWord immsrc = instr.getImm();
XWord immsrc = instr.getImm();
Word vmask = instr.getVmask();
int num_threads = core_->arch().num_threads();
std::vector<DWord[3]> rsdata(num_threads);
std::vector<DWord> rddata(num_threads);
std::vector<XWord[3]> rsdata(num_threads);
std::vector<XWord> rddata(num_threads);
int num_rsrcs = instr.getNRSrc();
if (num_rsrcs) {
@ -149,7 +149,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
switch (func3) {
case 0:
// RV32M: MUL
rddata[t] = ((DWordI)rsdata[t][0]) * ((DWordI)rsdata[t][1]);
rddata[t] = ((XWordI)rsdata[t][0]) * ((XWordI)rsdata[t][1]);
trace->alu.type = AluType::IMUL;
break;
case 1: {
@ -175,11 +175,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 4: {
// RV32M: DIV
DWordI dividen = rsdata[t][0];
DWordI divisor = rsdata[t][1];
XWordI dividen = rsdata[t][0];
XWordI divisor = rsdata[t][1];
if (divisor == 0) {
rddata[t] = -1;
} else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
} else if (dividen == XWordI(0x8000000000000000) && divisor == XWordI(0xffffffffffffffff)) {
rddata[t] = dividen;
} else {
rddata[t] = dividen / divisor;
@ -188,8 +188,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 5: {
// RV32M: DIVU
DWord dividen = rsdata[t][0];
DWord divisor = rsdata[t][1];
XWord dividen = rsdata[t][0];
XWord divisor = rsdata[t][1];
if (divisor == 0) {
rddata[t] = -1;
} else {
@ -199,11 +199,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 6: {
// RV32M: REM
DWordI dividen = rsdata[t][0];
DWordI divisor = rsdata[t][1];
XWordI dividen = rsdata[t][0];
XWordI divisor = rsdata[t][1];
if (rsdata[t][1] == 0) {
rddata[t] = dividen;
} else if (dividen == DWordI(0x8000000000000000) && divisor == DWordI(0xffffffffffffffff)) {
} else if (dividen == XWordI(0x8000000000000000) && divisor == XWordI(0xffffffffffffffff)) {
rddata[t] = 0;
} else {
rddata[t] = dividen % divisor;
@ -212,8 +212,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
} break;
case 7: {
// RV32M: REMU
DWord dividen = rsdata[t][0];
DWord divisor = rsdata[t][1];
XWord dividen = rsdata[t][0];
XWord divisor = rsdata[t][1];
if (rsdata[t][1] == 0) {
rddata[t] = dividen;
} else {
@ -241,11 +241,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 2:
// RV32I: LT
rddata[t] = (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1]));
rddata[t] = (XWordI(rsdata[t][0]) < XWordI(rsdata[t][1]));
break;
case 3:
// RV32I: LTU
rddata[t] = (DWord(rsdata[t][0]) < DWord(rsdata[t][1]));
rddata[t] = (XWord(rsdata[t][0]) < XWord(rsdata[t][1]));
break;
case 4:
// RV32I: XOR
@ -254,10 +254,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV32I: SRA
rddata[t] = DWordI(rsdata[t][0]) >> DWordI(rsdata[t][1]);
rddata[t] = XWordI(rsdata[t][0]) >> XWordI(rsdata[t][1]);
} else {
// RV32I: SHR
rddata[t] = DWord(rsdata[t][0]) >> DWord(rsdata[t][1]);
rddata[t] = XWord(rsdata[t][0]) >> XWord(rsdata[t][1]);
}
break;
case 6:
@ -293,7 +293,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 2:
// RV32I: SLTI
rddata[t] = (DWordI(rsdata[t][0]) < DWordI(immsrc));
rddata[t] = (XWordI(rsdata[t][0]) < XWordI(immsrc));
break;
case 3: {
// RV32I: SLTIU
@ -306,11 +306,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV32I: SRAI
DWord result = DWordI(rsdata[t][0]) >> immsrc;
XWord result = XWordI(rsdata[t][0]) >> immsrc;
rddata[t] = result;
} else {
// RV32I: SRLI
DWord result = rsdata[t][0] >> immsrc;
XWord result = rsdata[t][0] >> immsrc;
rddata[t] = result;
}
break;
@ -439,11 +439,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
case 5:
if (func7) {
// RV64I: SRAIW
DWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
XWord result = sext64((WordI)rsdata[t][0] >> (WordI)immsrc, 32);
rddata[t] = result;
} else {
// RV64I: SRLIW
DWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
XWord result = sext64((Word)rsdata[t][0] >> (Word)immsrc, 32);
rddata[t] = result;
}
break;
@ -476,25 +476,25 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 4:
// RV32I: BLT
if (DWordI(rsdata[t][0]) < DWordI(rsdata[t][1])) {
if (XWordI(rsdata[t][0]) < XWordI(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 5:
// RV32I: BGE
if (DWordI(rsdata[t][0]) >= DWordI(rsdata[t][1])) {
if (XWordI(rsdata[t][0]) >= XWordI(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 6:
// RV32I: BLTU
if (DWord(rsdata[t][0]) < DWord(rsdata[t][1])) {
if (XWord(rsdata[t][0]) < XWord(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
case 7:
// RV32I: BGEU
if (DWord(rsdata[t][0]) >= DWord(rsdata[t][1])) {
if (XWord(rsdata[t][0]) >= XWord(rsdata[t][1])) {
nextPC = PC_ + immsrc;
}
break;
@ -543,9 +543,9 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
for (int t = 0; t < num_threads; ++t) {
if (!tmask_.test(t))
continue;
DWord mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFFC); // double word aligned
DWord shift_by = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
DWord data_read = core_->dcache_read(mem_addr, 8);
XWord mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFFC); // double word aligned
XWord shift_by = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
XWord data_read = core_->dcache_read(mem_addr, 8);
trace->mem_addrs.at(t).push_back({mem_addr, 8});
DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << data_read);
switch (func3) {
@ -567,15 +567,15 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
break;
case 4:
// RV32I: LBU
rddata[t] = DWord((data_read >> shift_by) & 0xFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFF);
break;
case 5:
// RV32I: LHU
rddata[t] = DWord((data_read >> shift_by) & 0xFFFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFFFF);
break;
case 6:
// RV64I: LWU
rddata[t] = DWord((data_read >> shift_by) & 0xFFFFFFFF);
rddata[t] = XWord((data_read >> shift_by) & 0xFFFFFFFF);
break;
default:
std::abort();
@ -616,7 +616,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
for (int t = 0; t < num_threads; ++t) {
if (!tmask_.test(t))
continue;
DWord mem_addr = rsdata[t][0] + immsrc;
XWord mem_addr = rsdata[t][0] + immsrc;
trace->mem_addrs.at(t).push_back({mem_addr, (1u << func3)});
DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr);
switch (func3) {

6
sim/simx/instr.h
View file

@ -75,7 +75,7 @@ public:
void setFunc2(Word func2) { func2_ = func2; }
void setFunc3(Word func3) { func3_ = func3; }
void setFunc7(Word func7) { func7_ = func7; }
void setImm(DWord imm) { has_imm_ = true; imm_ = imm; }
void setImm(XWord imm) { has_imm_ = true; imm_ = imm; }
void setVlsWidth(Word width) { vlsWidth_ = width; }
void setVmop(Word mop) { vMop_ = mop; }
void setVnf(Word nf) { vNf_ = nf; }
@ -98,7 +98,7 @@ public:
int getRDest() const { return rdest_; }
RegType getRDType() const { return rdest_type_; }
bool hasImm() const { return has_imm_; }
DWord getImm() const { return imm_; }
XWord getImm() const { return imm_; }
Word getVlsWidth() const { return vlsWidth_; }
Word getVmop() const { return vMop_; }
Word getvNf() const { return vNf_; }
@ -118,7 +118,7 @@ private:
int num_rsrcs_;
bool has_imm_;
RegType rdest_type_;
DWord imm_;
XWord imm_;
RegType rsrc_type_[MAX_REG_SOURCES];
int rsrc_[MAX_REG_SOURCES];
int rdest_;

2
sim/simx/pipeline.h
View file

@ -18,7 +18,7 @@ struct pipeline_trace_t {
int cid;
int wid;
ThreadMask tmask;
DWord PC;
XWord PC;
//--
bool fetch_stall;

18
sim/simx/types.h
View file

@ -8,15 +8,25 @@
#include <VX_config.h>
#include <simobject.h>
#if XLEN == 32
#define uintx_t uint32_t
#define intx_t int32_t
#elif XLEN == 64
#define uintx_t uint64_t
#define intx_t int64_t
#else
#error unsupported XLEN
#endif
namespace vortex {
typedef uint8_t Byte;
typedef uint32_t Word;
typedef int32_t WordI;
typedef uint64_t DWord;
typedef int64_t DWordI;
typedef uintx_t XWord;
typedef intx_t XWordI;
typedef uint64_t Addr;
typedef uintx_t Addr;
typedef uint32_t Size;
typedef std::bitset<32> RegMask;
@ -133,7 +143,7 @@ struct mem_addr_size_t {
uint32_t size;
};
inline AddrType get_addr_type(DWord addr, uint32_t size) {
inline AddrType get_addr_type(XWord addr, uint32_t size) {
__unused (size);
if (SM_ENABLE) {
if (addr >= (SMEM_BASE_ADDR - SMEM_SIZE)

4
sim/simx/warp.cpp
View file

@ -13,8 +13,8 @@ using namespace vortex;
Warp::Warp(Core *core, Word id)
: id_(id)
, core_(core)
, ireg_file_(core->arch().num_threads(), std::vector<DWord>(core->arch().num_regs()))
, freg_file_(core->arch().num_threads(), std::vector<DWord>(core->arch().num_regs()))
, ireg_file_(core->arch().num_threads(), std::vector<XWord>(core->arch().num_regs()))
, freg_file_(core->arch().num_threads(), std::vector<XWord>(core->arch().num_regs()))
, vreg_file_(core->arch().num_threads(), std::vector<Byte>(core->arch().vsize()))
{
this->clear();

10
sim/simx/warp.h
View file

@ -11,7 +11,7 @@ class Core;
class Instr;
class pipeline_trace_t;
struct DomStackEntry {
DomStackEntry(const ThreadMask &tmask, DWord PC)
DomStackEntry(const ThreadMask &tmask, XWord PC)
: tmask(tmask)
, PC(PC)
, fallThrough(false)
@ -26,7 +26,7 @@ struct DomStackEntry {
{}
ThreadMask tmask;
DWord PC;
XWord PC;
bool fallThrough;
bool unanimous;
};
@ -99,11 +99,11 @@ private:
Core *core_;
bool active_;
DWord PC_;
XWord PC_;
ThreadMask tmask_;
std::vector<std::vector<DWord>> ireg_file_;
std::vector<std::vector<DWord>> freg_file_;
std::vector<std::vector<XWord>> ireg_file_;
std::vector<std::vector<XWord>> freg_file_;
std::vector<std::vector<Byte>> vreg_file_;
std::stack<DomStackEntry> dom_stack_;