mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
0a0b28aac0
commit
af84e01856
21 changed files with 870 additions and 889 deletions
|
|
@ -13,11 +13,11 @@ module VX_alu_unit #(
|
|||
VX_branch_ctl_if branch_ctl_if,
|
||||
VX_exu_to_cmt_if alu_commit_if
|
||||
);
|
||||
reg [`NUM_THREADS-1:0][31:0] alu_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] alu_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] add_result;
|
||||
reg [`NUM_THREADS-1:0][32:0] sub_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] shift_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] misc_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] shr_result;
|
||||
reg [`NUM_THREADS-1:0][31:0] msc_result;
|
||||
|
||||
wire is_br_op = alu_req_if.is_br_op;
|
||||
wire [`ALU_BITS-1:0] alu_op = `ALU_OP(alu_req_if.op_type);
|
||||
|
|
@ -48,23 +48,23 @@ module VX_alu_unit #(
|
|||
end
|
||||
|
||||
for (genvar i = 0; i < `NUM_THREADS; i++) begin
|
||||
wire [32:0] shift_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
|
||||
wire [32:0] shr_in1 = {alu_signed & alu_in1[i][31], alu_in1[i]};
|
||||
`IGNORE_WARNINGS_BEGIN
|
||||
wire [32:0] shift_value = $signed(shift_in1) >>> alu_in2_imm[i][4:0];
|
||||
wire [32:0] shr_value = $signed(shr_in1) >>> alu_in2_imm[i][4:0];
|
||||
`IGNORE_WARNINGS_END
|
||||
always @(*) begin
|
||||
shift_result[i] = shift_value[31:0];
|
||||
shr_result[i] = shr_value[31:0];
|
||||
end
|
||||
end
|
||||
|
||||
for (genvar i = 0; i < `NUM_THREADS; i++) begin
|
||||
always @(*) begin
|
||||
case (alu_op)
|
||||
`ALU_AND: misc_result[i] = alu_in1[i] & alu_in2_imm[i];
|
||||
`ALU_OR: misc_result[i] = alu_in1[i] | alu_in2_imm[i];
|
||||
`ALU_XOR: misc_result[i] = alu_in1[i] ^ alu_in2_imm[i];
|
||||
`ALU_AND: msc_result[i] = alu_in1[i] & alu_in2_imm[i];
|
||||
`ALU_OR: msc_result[i] = alu_in1[i] | alu_in2_imm[i];
|
||||
`ALU_XOR: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i];
|
||||
//`ALU_SLL,
|
||||
default: misc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
|
||||
default: msc_result[i] = alu_in1[i] << alu_in2_imm[i][4:0];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
|
@ -74,21 +74,20 @@ module VX_alu_unit #(
|
|||
case (alu_op_class)
|
||||
0: alu_result[i] = add_result[i];
|
||||
1: alu_result[i] = {31'b0, sub_result[i][32]};
|
||||
2: alu_result[i] = is_sub ? sub_result[i][31:0] : shift_result[i];
|
||||
default: alu_result[i] = misc_result[i];
|
||||
2: alu_result[i] = is_sub ? sub_result[i][31:0] : shr_result[i];
|
||||
default: alu_result[i] = msc_result[i];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
wire is_jal = is_br_op && (br_op == `BR_JAL || br_op == `BR_JALR);
|
||||
wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result;
|
||||
wire [`NUM_THREADS-1:0][31:0] alu_jal_result = is_jal ? {`NUM_THREADS{alu_req_if.next_PC}} : alu_result;
|
||||
|
||||
wire [31:0] br_dest = add_result[alu_req_if.tid];
|
||||
wire [32:0] cmp_result = sub_result[alu_req_if.tid];
|
||||
wire is_less = cmp_result[32];
|
||||
wire is_equal = ~(| cmp_result[31:0]);
|
||||
wire [32:0] cmp_result = sub_result[alu_req_if.tid];
|
||||
|
||||
wire is_br_op_r, is_less_r, is_equal_r;
|
||||
wire [32:0] cmp_result_r;
|
||||
wire is_br_op_r;
|
||||
`IGNORE_WARNINGS_BEGIN
|
||||
wire [`BR_BITS-1:0] br_op_r;
|
||||
`IGNORE_WARNINGS_END
|
||||
|
|
@ -98,20 +97,23 @@ module VX_alu_unit #(
|
|||
wire stall_out = ~alu_commit_if.ready && alu_commit_if.valid;
|
||||
|
||||
VX_generic_register #(
|
||||
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 1 + 1 + 32)
|
||||
.N(1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 1 + `BR_BITS + 32 + 33)
|
||||
) alu_reg (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (stall_out),
|
||||
.flush (1'b0),
|
||||
.in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.thread_mask, alu_req_if.curr_PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, is_less, is_equal, br_dest}),
|
||||
.out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.thread_mask, alu_commit_if.curr_PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, is_less_r, is_equal_r, branch_ctl_if.dest})
|
||||
.in ({alu_req_if.valid, alu_req_if.wid, alu_req_if.thread_mask, alu_req_if.curr_PC, alu_req_if.rd, alu_req_if.wb, alu_jal_result, is_br_op, br_op, br_dest, cmp_result}),
|
||||
.out ({alu_commit_if.valid, alu_commit_if.wid, alu_commit_if.thread_mask, alu_commit_if.curr_PC, alu_commit_if.rd, alu_commit_if.wb, alu_commit_if.data, is_br_op_r, br_op_r, branch_ctl_if.dest, cmp_result_r})
|
||||
);
|
||||
|
||||
wire is_less = cmp_result_r[32];
|
||||
wire is_equal = ~(| cmp_result_r[31:0]);
|
||||
|
||||
wire br_neg = `BR_NEG(br_op_r);
|
||||
wire br_less = `BR_LESS(br_op_r);
|
||||
wire br_static = `BR_STATIC(br_op_r);
|
||||
wire br_taken = ((br_less ? is_less_r : is_equal_r) ^ br_neg) | br_static;
|
||||
wire br_taken = ((br_less ? is_less : is_equal) ^ br_neg) | br_static;
|
||||
|
||||
assign branch_ctl_if.valid = alu_commit_if.valid && alu_commit_if.ready && is_br_op_r;
|
||||
assign branch_ctl_if.wid = alu_commit_if.wid;
|
||||
|
|
|
|||
|
|
@ -15,39 +15,37 @@ module VX_gpr_fp_ctrl (
|
|||
);
|
||||
|
||||
reg [`NUM_THREADS-1:0][31:0] rs1_tmp_data, rs2_tmp_data, rs3_tmp_data;
|
||||
reg read_rs3;
|
||||
reg read_rs1;
|
||||
reg [`NW_BITS-1:0] rs3_wid;
|
||||
|
||||
wire rs3_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && ~read_rs3;
|
||||
wire rs3_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && read_rs1;
|
||||
wire read_fire = gpr_read_if.valid && gpr_read_if.ready_out;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
read_rs3 <= 0;
|
||||
rs3_wid <= 0;
|
||||
rs1_tmp_data <= 0;
|
||||
rs2_tmp_data <= 0;
|
||||
rs3_tmp_data <= 0;
|
||||
read_rs1 <= 1;
|
||||
end else begin
|
||||
if (rs3_delay) begin
|
||||
read_rs3 <= 1;
|
||||
read_rs1 <= 0;
|
||||
rs3_wid <= gpr_read_if.wid;
|
||||
end else if (read_fire) begin
|
||||
read_rs3 <= 0;
|
||||
read_rs1 <= 1;
|
||||
end
|
||||
|
||||
if (~read_rs3) begin
|
||||
rs1_tmp_data <= rs1_data;
|
||||
end
|
||||
rs2_tmp_data <= rs2_data;
|
||||
rs3_tmp_data <= rs1_data;
|
||||
|
||||
assert(!read_rs3 || rs3_wid == gpr_read_if.wid);
|
||||
assert(read_rs1 || rs3_wid == gpr_read_if.wid);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (read_rs1) begin
|
||||
rs1_tmp_data <= rs1_data;
|
||||
end
|
||||
rs2_tmp_data <= rs2_data;
|
||||
rs3_tmp_data <= rs1_data;
|
||||
end
|
||||
|
||||
// outputs
|
||||
wire [`NR_BITS-1:0] rs1 = read_rs3 ? gpr_read_if.rs3 : gpr_read_if.rs1;
|
||||
wire [`NR_BITS-1:0] rs1 = read_rs1 ? gpr_read_if.rs1 : gpr_read_if.rs3;
|
||||
assign raddr1 = {gpr_read_if.wid, rs1};
|
||||
assign gpr_read_if.ready_in = ~rs3_delay;
|
||||
assign gpr_read_if.rs1_data = rs1_tmp_data;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ module VX_ibuffer #(
|
|||
VX_decode_if ibuf_enq_if,
|
||||
|
||||
// outputs
|
||||
output wire [`NW_BITS-1:0] deq_wid_next,
|
||||
VX_decode_if ibuf_deq_if
|
||||
);
|
||||
localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + 1 + `NUM_REGS;
|
||||
|
|
@ -84,12 +85,10 @@ module VX_ibuffer #(
|
|||
reg deq_valid, deq_valid_n;
|
||||
reg [DATAW-1:0] deq_instr, deq_instr_n;
|
||||
|
||||
reg [DATAW-1:0] q_data_prev_r, q_data_out_r;
|
||||
|
||||
always @(*) begin
|
||||
valid_table_n = valid_table;
|
||||
if (deq_fire) begin
|
||||
valid_table_n[ibuf_deq_if.wid] = (q_size[deq_wid] != SIZEW'(1));
|
||||
valid_table_n[deq_wid] = (q_size[deq_wid] != SIZEW'(1));
|
||||
end
|
||||
if (enq_fire) begin
|
||||
valid_table_n[ibuf_enq_if.wid] = 1;
|
||||
|
|
@ -99,26 +98,26 @@ module VX_ibuffer #(
|
|||
// schedule the next instruction to issue
|
||||
// does round-robin scheduling when multiple warps are present
|
||||
always @(*) begin
|
||||
deq_valid_n = 0;
|
||||
deq_wid_n = 'x;
|
||||
deq_instr_n = 'x;
|
||||
deq_valid_n = 0;
|
||||
deq_wid_n = 'x;
|
||||
deq_instr_n = 'x;
|
||||
|
||||
schedule_table_n = schedule_table;
|
||||
|
||||
if (0 == num_warps) begin
|
||||
deq_valid_n = enq_fire;
|
||||
deq_wid_n = ibuf_enq_if.wid;
|
||||
deq_instr_n = q_data_in;
|
||||
deq_valid_n = enq_fire;
|
||||
deq_wid_n = ibuf_enq_if.wid;
|
||||
deq_instr_n = q_data_in;
|
||||
end else if ((1 == num_warps) || freeze) begin
|
||||
deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire;
|
||||
deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid;
|
||||
deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev_r : q_data_in) : q_data_out_r;
|
||||
deq_valid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) || enq_fire;
|
||||
deq_wid_n = (!deq_fire || (q_size[deq_wid] != SIZEW'(1))) ? deq_wid : ibuf_enq_if.wid;
|
||||
deq_instr_n = deq_fire ? ((q_size[deq_wid] != SIZEW'(1)) ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid];
|
||||
end else begin
|
||||
for (integer i = 0; i < `NUM_WARPS; i++) begin
|
||||
if (schedule_table_n[i]) begin
|
||||
deq_valid_n = 1;
|
||||
deq_wid_n = `NW_BITS'(i);
|
||||
deq_instr_n = q_data_out[i];
|
||||
deq_valid_n = 1;
|
||||
deq_wid_n = `NW_BITS'(i);
|
||||
deq_instr_n = q_data_out[i];
|
||||
schedule_table_n[i] = 0;
|
||||
break;
|
||||
end
|
||||
|
|
@ -127,7 +126,7 @@ module VX_ibuffer #(
|
|||
end
|
||||
|
||||
wire warp_added = enq_fire && (0 == q_size[ibuf_enq_if.wid]);
|
||||
wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == ibuf_deq_if.wid) && (1 == q_size[ibuf_deq_if.wid]);
|
||||
wire warp_removed = deq_fire && ~(enq_fire && ibuf_enq_if.wid == deq_wid) && ~(q_size[deq_wid] != SIZEW'(1));
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
|
|
@ -145,12 +144,9 @@ module VX_ibuffer #(
|
|||
schedule_table[deq_wid_n] <= 0;
|
||||
end
|
||||
|
||||
q_data_out_r <= (0 == num_warps) ? q_data_in : q_data_out[deq_wid_n];
|
||||
q_data_prev_r <= q_data_prev[deq_wid_n];
|
||||
|
||||
deq_valid <= deq_valid_n;
|
||||
deq_wid <= deq_wid_n;
|
||||
deq_instr <= deq_instr_n;
|
||||
deq_valid <= deq_valid_n;
|
||||
deq_wid <= deq_wid_n;
|
||||
deq_instr <= deq_instr_n;
|
||||
|
||||
if (warp_added && !warp_removed) begin
|
||||
num_warps <= num_warps + NWARPSW'(1);
|
||||
|
|
@ -176,6 +172,8 @@ module VX_ibuffer #(
|
|||
end
|
||||
end
|
||||
|
||||
assign deq_wid_next = deq_wid_n;
|
||||
|
||||
assign ibuf_enq_if.ready = ~q_full[ibuf_enq_if.wid];
|
||||
assign q_data_in = {ibuf_enq_if.thread_mask,
|
||||
ibuf_enq_if.curr_PC,
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ module VX_icache_stage #(
|
|||
always @(posedge clk) begin
|
||||
if (icache_req_fire) begin
|
||||
rsp_curr_PC_buf[req_tag] <= ifetch_req_if.curr_PC;
|
||||
rsp_thread_mask_buf[req_tag] <= ifetch_req_if.thread_mask;
|
||||
rsp_thread_mask_buf[req_tag] <= ifetch_req_if.thread_mask;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ module VX_instr_demux (
|
|||
.ready_in (lsu_req_ready),
|
||||
.valid_in (lsu_req_valid),
|
||||
.data_in ({execute_if.wid, execute_if.thread_mask, execute_if.curr_PC, `LSU_RW(execute_if.op_type), `LSU_BE(execute_if.op_type), execute_if.imm, execute_if.rd, execute_if.wb}),
|
||||
.data_out ({lsu_req_if.wid, lsu_req_if.thread_mask, lsu_req_if.curr_PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb}),
|
||||
.data_out ({lsu_req_if.wid, lsu_req_if.thread_mask, lsu_req_if.curr_PC, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb}),
|
||||
.ready_out (lsu_req_if.ready),
|
||||
.valid_out (lsu_req_if.valid)
|
||||
);
|
||||
|
|
|
|||
|
|
@ -22,15 +22,17 @@ module VX_issue #(
|
|||
VX_gpr_read_if gpr_read_if();
|
||||
|
||||
wire scoreboard_delay;
|
||||
wire [`NW_BITS-1:0] deq_wid_next;
|
||||
|
||||
VX_ibuffer #(
|
||||
.CORE_ID(CORE_ID)
|
||||
) ibuffer (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.freeze (~gpr_read_if.ready_in),
|
||||
.ibuf_enq_if (decode_if),
|
||||
.ibuf_deq_if (ibuf_deq_if),
|
||||
.freeze (~gpr_read_if.ready_in)
|
||||
.deq_wid_next (deq_wid_next),
|
||||
.ibuf_deq_if (ibuf_deq_if)
|
||||
);
|
||||
|
||||
VX_scoreboard #(
|
||||
|
|
@ -40,6 +42,7 @@ module VX_issue #(
|
|||
.reset (reset),
|
||||
.ibuf_deq_if (ibuf_deq_if),
|
||||
.writeback_if (writeback_if),
|
||||
.deq_wid_next (deq_wid_next),
|
||||
.exe_delay (~execute_if.ready),
|
||||
.gpr_delay (~gpr_read_if.ready_in),
|
||||
.delay (scoreboard_delay)
|
||||
|
|
|
|||
|
|
@ -8,15 +8,17 @@ module VX_scoreboard #(
|
|||
|
||||
VX_decode_if ibuf_deq_if,
|
||||
VX_writeback_if writeback_if,
|
||||
input wire [`NW_BITS-1:0] deq_wid_next,
|
||||
input wire exe_delay,
|
||||
input wire gpr_delay,
|
||||
|
||||
output wire delay
|
||||
);
|
||||
reg [`NUM_THREADS-1:0] inuse_registers [(`NUM_WARPS * `NUM_REGS)-1:0];
|
||||
reg [`NUM_REGS-1:0] inuse_reg_mask [`NUM_WARPS-1:0];
|
||||
reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_reg_mask, inuse_reg_mask_n;
|
||||
reg [`NUM_REGS-1:0] deq_used_regs;
|
||||
|
||||
wire [`NUM_REGS-1:0] inuse_regs = inuse_reg_mask[ibuf_deq_if.wid] & ibuf_deq_if.used_regs;
|
||||
wire [`NUM_REGS-1:0] inuse_regs = deq_used_regs & ibuf_deq_if.used_regs;
|
||||
|
||||
assign delay = (| inuse_regs);
|
||||
|
||||
|
|
@ -26,38 +28,49 @@ module VX_scoreboard #(
|
|||
|
||||
wire [`NUM_THREADS-1:0] inuse_registers_n = inuse_registers[{writeback_if.wid, writeback_if.rd}] & ~writeback_if.thread_mask;
|
||||
|
||||
always @(*) begin
|
||||
inuse_reg_mask_n = inuse_reg_mask;
|
||||
if (reserve_reg) begin
|
||||
inuse_reg_mask_n[ibuf_deq_if.wid][ibuf_deq_if.rd] = 1;
|
||||
end
|
||||
if (release_reg) begin
|
||||
inuse_reg_mask_n[writeback_if.wid][writeback_if.rd] = (| inuse_registers_n);
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
for (integer w = 0; w < `NUM_WARPS; w++) begin
|
||||
for (integer i = 0; i < `NUM_REGS; i++) begin
|
||||
inuse_registers[w * `NUM_REGS + i] <= 0;
|
||||
end
|
||||
inuse_reg_mask [w] <= `NUM_REGS'(0);
|
||||
inuse_reg_mask[w] <= `NUM_REGS'(0);
|
||||
end
|
||||
end else begin
|
||||
if (reserve_reg) begin
|
||||
inuse_registers[{ibuf_deq_if.wid, ibuf_deq_if.rd}] <= ibuf_deq_if.thread_mask;
|
||||
inuse_reg_mask[ibuf_deq_if.wid][ibuf_deq_if.rd] <= 1;
|
||||
end
|
||||
if (release_reg) begin
|
||||
assert(inuse_reg_mask[writeback_if.wid][writeback_if.rd] != 0);
|
||||
inuse_registers[{writeback_if.wid, writeback_if.rd}] <= inuse_registers_n;
|
||||
inuse_reg_mask[writeback_if.wid][writeback_if.rd] <= (| inuse_registers_n);
|
||||
end
|
||||
end
|
||||
inuse_reg_mask <= inuse_reg_mask_n;
|
||||
end
|
||||
|
||||
deq_used_regs <= inuse_reg_mask_n[deq_wid_next];
|
||||
end
|
||||
|
||||
// issue the instruction
|
||||
assign ibuf_deq_if.ready = ~(delay || exe_delay || gpr_delay);
|
||||
|
||||
`ifdef DBG_PRINT_PIPELINE
|
||||
always @(posedge clk) begin
|
||||
/*always @(posedge clk) begin
|
||||
if (ibuf_deq_if.valid && ~ibuf_deq_if.ready) begin
|
||||
$display("%t: core%0d-stall: wid=%0d, PC=%0h, rd=%0d, wb=%0d, inuse=%b%b%b%b, exe=%b, gpr=%b",
|
||||
$time, CORE_ID, ibuf_deq_if.wid, ibuf_deq_if.curr_PC, ibuf_deq_if.rd, ibuf_deq_if.wb,
|
||||
inuse_regs[ibuf_deq_if.rd], inuse_regs[ibuf_deq_if.rs1], inuse_regs[ibuf_deq_if.rs2], inuse_regs[ibuf_deq_if.rs3], exe_delay, gpr_delay);
|
||||
end
|
||||
end
|
||||
end*/
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
@ -64,8 +64,9 @@ module VX_writeback #(
|
|||
fpu_valid ? fpu_commit_if.data :
|
||||
0;
|
||||
|
||||
wire stall = ~writeback_if.ready && writeback_if.valid;
|
||||
|
||||
always @(*) assert(writeback_if.ready);
|
||||
wire stall = 0/*~writeback_if.ready && writeback_if.valid*/;
|
||||
|
||||
VX_generic_register #(
|
||||
.N(1 + `NW_BITS + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32))
|
||||
) wb_reg (
|
||||
|
|
|
|||
1
hw/rtl/cache/VX_bank.v
vendored
1
hw/rtl/cache/VX_bank.v
vendored
|
|
@ -650,6 +650,7 @@ module VX_bank #(
|
|||
assign core_rsp_valid = !cwbq_empty;
|
||||
|
||||
// Enqueue DRAM fill request
|
||||
|
||||
wire dram_fill_req_fast = miss_add_unqual; // Completely unqualified hint that we might send a dram_fill_req
|
||||
wire dram_fill_req_unqual = dram_fill_req_fast
|
||||
&& (!mrvq_init_ready_state_st2
|
||||
|
|
|
|||
|
|
@ -271,34 +271,34 @@ module VX_fp_fpga #(
|
|||
.valid_out (per_core_valid_out[11])
|
||||
);
|
||||
|
||||
reg valid_out_r;
|
||||
reg has_fflags_r;
|
||||
reg [`NUM_THREADS-1:0][31:0] result_r;
|
||||
reg [TAGW-1:0] tag_out_r;
|
||||
reg valid_out_n;
|
||||
reg has_fflags_n;
|
||||
reg [`NUM_THREADS-1:0][31:0] result_n;
|
||||
reg [TAGW-1:0] tag_out_n;
|
||||
|
||||
always @(*) begin
|
||||
per_core_ready_out = 0;
|
||||
valid_out_r = 0;
|
||||
has_fflags_r = 'x;
|
||||
result_r = 'x;
|
||||
tag_out_r = 'x;
|
||||
valid_out_n = 0;
|
||||
has_fflags_n = 'x;
|
||||
result_n = 'x;
|
||||
tag_out_n = 'x;
|
||||
for (integer i = 0; i < NUM_FPC; i++) begin
|
||||
if (per_core_valid_out[i]) begin
|
||||
per_core_ready_out[i] = ready_out;
|
||||
valid_out_r = 1;
|
||||
has_fflags_r = fpnew_has_fflags && (i == 0);
|
||||
result_r = per_core_result[i];
|
||||
tag_out_r = per_core_tag_out[i];
|
||||
valid_out_n = 1;
|
||||
has_fflags_n = fpnew_has_fflags && (i == 0);
|
||||
result_n = per_core_result[i];
|
||||
tag_out_n = per_core_tag_out[i];
|
||||
break;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign ready_in = (& per_core_ready_in);
|
||||
assign valid_out = valid_out_r;
|
||||
assign has_fflags = has_fflags_r;
|
||||
assign tag_out = tag_out_r;
|
||||
assign result = result_r;
|
||||
assign valid_out = valid_out_n;
|
||||
assign has_fflags = has_fflags_n;
|
||||
assign tag_out = tag_out_n;
|
||||
assign result = result_n;
|
||||
assign fflags = fpnew_fflags;
|
||||
|
||||
endmodule
|
||||
|
|
@ -45,9 +45,9 @@ module VX_fp_noncomp #(
|
|||
reg [LANES-1:0][31:0] datab_r;
|
||||
|
||||
reg [LANES-1:0] a_sign, b_sign;
|
||||
reg [LANES-1:0][7:0] a_exponent, b_exponent;
|
||||
reg [LANES-1:0][22:0] a_mantissa, b_mantissa;
|
||||
fp_type_t [LANES-1:0] a_type, b_type;
|
||||
reg [LANES-1:0][7:0] a_exponent;
|
||||
reg [LANES-1:0][22:0] a_mantissa;
|
||||
fp_type_t [LANES-1:0] a_type, b_type;
|
||||
reg [LANES-1:0] a_smaller, ab_equal;
|
||||
|
||||
reg [LANES-1:0][31:0] fclass_mask; // generate a 10-bit mask for integer reg
|
||||
|
|
@ -86,14 +86,14 @@ module VX_fp_noncomp #(
|
|||
wire tmp_ab_equal = (dataa[i] == datab[i]) | (tmp_a_type[4] & tmp_b_type[4]);
|
||||
|
||||
VX_generic_register #(
|
||||
.N(1 + 1 + 8 + 8 + 23 + 23 + $bits(fp_type_t) + $bits(fp_type_t) + 1 + 1)
|
||||
.N(1 + 1 + 8 + 23 + $bits(fp_type_t) + $bits(fp_type_t) + 1 + 1)
|
||||
) fnc1_reg (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.stall (stall),
|
||||
.flush (1'b0),
|
||||
.in ({tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_b_exponent, tmp_a_mantissa, tmp_b_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}),
|
||||
.out ({a_sign[i], b_sign[i], a_exponent[i], b_exponent[i], a_mantissa[i], b_mantissa[i], a_type[i], b_type[i], a_smaller[i], ab_equal[i]})
|
||||
.in ({tmp_a_sign, tmp_b_sign, tmp_a_exponent, tmp_a_mantissa, tmp_a_type, tmp_b_type, tmp_a_smaller, tmp_ab_equal}),
|
||||
.out ({a_sign[i], b_sign[i], a_exponent[i], a_mantissa[i], a_type[i], b_type[i], a_smaller[i], ab_equal[i]})
|
||||
);
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@ module VX_fp_type (
|
|||
assign o_type.is_normal = (exponent != 8'd0) && (exponent != 8'hff);
|
||||
assign o_type.is_zero = (exponent == 8'd0) && (mantissa == 23'd0);
|
||||
assign o_type.is_subnormal = (exponent == 8'd0) && !o_type.is_zero;
|
||||
assign o_type.is_inf = ((exponent == 8'hff) && (mantissa == 23'd0));
|
||||
assign o_type.is_nan = ((exponent == 8'hff) && (mantissa != 23'd0));
|
||||
assign o_type.is_inf = (exponent == 8'hff) && (mantissa == 23'd0);
|
||||
assign o_type.is_nan = (exponent == 8'hff) && (mantissa != 23'd0);
|
||||
assign o_type.is_signaling = o_type.is_nan && (mantissa[22] == 1'b0);
|
||||
assign o_type.is_quiet = o_type.is_nan && !o_type.is_signaling;
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fp_ftoi
|
||||
// SystemVerilog created on Wed Aug 5 12:58:15 2020
|
||||
// SystemVerilog created on Mon Aug 31 06:15:18 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
@ -89,8 +89,7 @@ module acl_fp_ftoi (
|
|||
wire [35:0] rndOvfPos_uid47_fpToFxPTest_b;
|
||||
logic [35:0] rndOvfPos_uid47_fpToFxPTest_o;
|
||||
wire [0:0] rndOvfPos_uid47_fpToFxPTest_c;
|
||||
wire [0:0] ovfPostRnd_uid48_fpToFxPTest_qi;
|
||||
reg [0:0] ovfPostRnd_uid48_fpToFxPTest_q;
|
||||
wire [0:0] ovfPostRnd_uid48_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid49_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid50_fpToFxPTest_q;
|
||||
wire [31:0] maxNegValueU_uid51_fpToFxPTest_q;
|
||||
|
|
@ -125,14 +124,14 @@ module acl_fp_ftoi (
|
|||
wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid29_fpToFxPTest_n_5_q;
|
||||
reg [0:0] redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q;
|
||||
reg [0:0] redist3_signX_uid25_fpToFxPTest_b_3_q;
|
||||
reg [0:0] redist4_signX_uid25_fpToFxPTest_b_5_q;
|
||||
reg [0:0] redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q;
|
||||
reg [0:0] redist6_expXIsMax_uid12_fpToFxPTest_q_4_q;
|
||||
reg [0:0] redist7_excZ_x_uid11_fpToFxPTest_q_2_q;
|
||||
reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_2_q;
|
||||
reg [5:0] redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist2_udf_uid29_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
|
||||
reg [0:0] redist5_signX_uid25_fpToFxPTest_b_3_q;
|
||||
reg [0:0] redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
|
||||
reg [0:0] redist7_expXIsMax_uid12_fpToFxPTest_q_3_q;
|
||||
reg [22:0] redist8_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
|
||||
|
||||
// maxNegValueU_uid51_fpToFxPTest(CONSTANT,50)
|
||||
|
|
@ -150,9 +149,9 @@ module acl_fp_ftoi (
|
|||
// signX_uid25_fpToFxPTest(BITSELECT,24)@0
|
||||
assign signX_uid25_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// redist3_signX_uid25_fpToFxPTest_b_3(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist3_signX_uid25_fpToFxPTest_b_3 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist3_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist4_signX_uid25_fpToFxPTest_b_2(DELAY,90)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
|
@ -160,61 +159,61 @@ module acl_fp_ftoi (
|
|||
// rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,80)
|
||||
assign rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@2
|
||||
// rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,79)@1
|
||||
assign rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:3];
|
||||
|
||||
// rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@2
|
||||
// rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,81)@1
|
||||
assign rightShiftStage2Idx3_uid82_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid81_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid80_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,77)
|
||||
assign rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@2
|
||||
// rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,76)@1
|
||||
assign rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:2];
|
||||
|
||||
// rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@2
|
||||
// rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,78)@1
|
||||
assign rightShiftStage2Idx2_uid79_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid78_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid77_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@2
|
||||
// rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,73)@1
|
||||
assign rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:1];
|
||||
|
||||
// rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@2
|
||||
// rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,75)@1
|
||||
assign rightShiftStage2Idx1_uid76_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid74_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,69)
|
||||
assign rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@2
|
||||
// rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,68)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@2
|
||||
// rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,70)@1
|
||||
assign rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid70_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid69_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@2
|
||||
// rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,65)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@2
|
||||
// rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,67)@1
|
||||
assign rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid66_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,63)
|
||||
assign rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@2
|
||||
// rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,62)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b = rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q[31:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@2
|
||||
// rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,64)@1
|
||||
assign rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid64_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid63_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest(CONSTANT,56)
|
||||
assign rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@2
|
||||
// rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest(BITSELECT,55)@1
|
||||
assign rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b = shifterIn_uid37_fpToFxPTest_q[31:16];
|
||||
|
||||
// rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@2
|
||||
// rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest(BITJOIN,57)@1
|
||||
assign rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid57_rightShiferNoStickyOut_uid38_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid56_rightShiferNoStickyOut_uid38_fpToFxPTest_b};
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
|
|
@ -225,27 +224,23 @@ module acl_fp_ftoi (
|
|||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist7_excZ_x_uid11_fpToFxPTest_q_2(DELAY,93)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist7_excZ_x_uid11_fpToFxPTest_q_2 ( .xin(excZ_x_uid11_fpToFxPTest_q), .xout(redist7_excZ_x_uid11_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@2
|
||||
assign invExcXZ_uid22_fpToFxPTest_q = ~ (redist7_excZ_x_uid11_fpToFxPTest_q_2_q);
|
||||
// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
|
||||
assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// redist8_frac_x_uid10_fpToFxPTest_b_2(DELAY,94)
|
||||
dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") )
|
||||
redist8_frac_x_uid10_fpToFxPTest_b_2 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist8_frac_x_uid10_fpToFxPTest_b_1(DELAY,94)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist8_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist8_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@2
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_2_q};
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist8_frac_x_uid10_fpToFxPTest_b_1_q};
|
||||
|
||||
// shifterIn_uid37_fpToFxPTest(BITJOIN,36)@2
|
||||
// shifterIn_uid37_fpToFxPTest(BITJOIN,36)@1
|
||||
assign shifterIn_uid37_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, cstAllZWE_uid8_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@2
|
||||
// rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,61)@1
|
||||
assign rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or shifterIn_uid37_fpToFxPTest_q or rightShiftStage0Idx1_uid58_rightShiferNoStickyOut_uid38_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -258,7 +253,7 @@ module acl_fp_ftoi (
|
|||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@2
|
||||
// rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,72)@1
|
||||
assign rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid73_rightShiferNoStickyOut_uid38_fpToFxPTest_s or en or rightShiftStage0_uid62_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx1_uid65_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx2_uid68_rightShiferNoStickyOut_uid38_fpToFxPTest_q or rightShiftStage1Idx3_uid71_rightShiferNoStickyOut_uid38_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -277,56 +272,53 @@ module acl_fp_ftoi (
|
|||
// ovfExpVal_uid30_fpToFxPTest(CONSTANT,29)
|
||||
assign ovfExpVal_uid30_fpToFxPTest_q = 9'b010011101;
|
||||
|
||||
// shiftValE_uid31_fpToFxPTest(SUB,30)@0 + 1
|
||||
// shiftValE_uid31_fpToFxPTest(SUB,30)@0
|
||||
assign shiftValE_uid31_fpToFxPTest_a = {{2{ovfExpVal_uid30_fpToFxPTest_q[8]}}, ovfExpVal_uid30_fpToFxPTest_q};
|
||||
assign shiftValE_uid31_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftValE_uid31_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
shiftValE_uid31_fpToFxPTest_o <= $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftValE_uid31_fpToFxPTest_o = $signed(shiftValE_uid31_fpToFxPTest_a) - $signed(shiftValE_uid31_fpToFxPTest_b);
|
||||
assign shiftValE_uid31_fpToFxPTest_q = shiftValE_uid31_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@1
|
||||
// shiftValRaw_uid32_fpToFxPTest(BITSELECT,31)@0
|
||||
assign shiftValRaw_uid32_fpToFxPTest_in = shiftValE_uid31_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid32_fpToFxPTest_b = shiftValRaw_uid32_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@1
|
||||
// redist1_shiftValRaw_uid32_fpToFxPTest_b_1(DELAY,87)
|
||||
dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_shiftValRaw_uid32_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid32_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// shiftOutOfRange_uid34_fpToFxPTest(COMPARE,33)@0 + 1
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_a = {{2{shiftValE_uid31_fpToFxPTest_q[9]}}, shiftValE_uid31_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_b = {6'b000000, maxShiftCst_uid33_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_o = $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid35_fpToFxPTest(MUX,34)@1 + 1
|
||||
assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid35_fpToFxPTest_q <= 6'b0;
|
||||
shiftOutOfRange_uid34_fpToFxPTest_o <= 12'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid35_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid35_fpToFxPTest_q <= shiftValRaw_uid32_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid35_fpToFxPTest_q <= maxShiftCst_uid33_fpToFxPTest_q;
|
||||
default : shiftVal_uid35_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
shiftOutOfRange_uid34_fpToFxPTest_o <= $signed(shiftOutOfRange_uid34_fpToFxPTest_a) - $signed(shiftOutOfRange_uid34_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftOutOfRange_uid34_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid34_fpToFxPTest_o[11]);
|
||||
|
||||
// rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@2
|
||||
// shiftVal_uid35_fpToFxPTest(MUX,34)@1
|
||||
assign shiftVal_uid35_fpToFxPTest_s = shiftOutOfRange_uid34_fpToFxPTest_n;
|
||||
always @(shiftVal_uid35_fpToFxPTest_s or en or redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q or maxShiftCst_uid33_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (shiftVal_uid35_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid35_fpToFxPTest_q = redist1_shiftValRaw_uid32_fpToFxPTest_b_1_q;
|
||||
1'b1 : shiftVal_uid35_fpToFxPTest_q = maxShiftCst_uid33_fpToFxPTest_q;
|
||||
default : shiftVal_uid35_fpToFxPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select(BITSELECT,85)@1
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_b = shiftVal_uid35_fpToFxPTest_q[5:4];
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_c = shiftVal_uid35_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d = shiftVal_uid35_fpToFxPTest_q[1:0];
|
||||
|
||||
// rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@2 + 1
|
||||
// rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest(MUX,83)@1 + 1
|
||||
assign rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_s = rightShiftStageSel5Dto4_uid61_rightShiferNoStickyOut_uid38_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
|
|
@ -346,30 +338,20 @@ module acl_fp_ftoi (
|
|||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@3
|
||||
// zRightShiferNoStickyOut_uid41_fpToFxPTest(BITJOIN,40)@2
|
||||
assign zRightShiferNoStickyOut_uid41_fpToFxPTest_q = {GND_q, rightShiftStage2_uid84_rightShiferNoStickyOut_uid38_fpToFxPTest_q};
|
||||
|
||||
// xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@3
|
||||
assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist3_signX_uid25_fpToFxPTest_b_3_q[0]}}, redist3_signX_uid25_fpToFxPTest_b_3_q};
|
||||
// xXorSignE_uid42_fpToFxPTest(LOGICAL,41)@2
|
||||
assign xXorSignE_uid42_fpToFxPTest_b = {{32{redist4_signX_uid25_fpToFxPTest_b_2_q[0]}}, redist4_signX_uid25_fpToFxPTest_b_2_q};
|
||||
assign xXorSignE_uid42_fpToFxPTest_q = zRightShiferNoStickyOut_uid41_fpToFxPTest_q ^ xXorSignE_uid42_fpToFxPTest_b;
|
||||
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@3 + 1
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
|
||||
assign sPostRndFull_uid44_fpToFxPTest_a = {{1{xXorSignE_uid42_fpToFxPTest_q[32]}}, xXorSignE_uid42_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_b = {{31{d0_uid43_fpToFxPTest_q[2]}}, d0_uid43_fpToFxPTest_q};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
sPostRndFull_uid44_fpToFxPTest_o <= 34'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
sPostRndFull_uid44_fpToFxPTest_o <= $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign sPostRndFull_uid44_fpToFxPTest_o = $signed(sPostRndFull_uid44_fpToFxPTest_a) + $signed(sPostRndFull_uid44_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[33:0];
|
||||
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@4
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
|
||||
assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
|
||||
|
||||
|
|
@ -377,9 +359,9 @@ module acl_fp_ftoi (
|
|||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist0_sPostRnd_uid45_fpToFxPTest_b_1 ( .xin(sPostRnd_uid45_fpToFxPTest_b), .xout(redist0_sPostRnd_uid45_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_signX_uid25_fpToFxPTest_b_5(DELAY,90)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist4_signX_uid25_fpToFxPTest_b_5 ( .xin(redist3_signX_uid25_fpToFxPTest_b_3_q), .xout(redist4_signX_uid25_fpToFxPTest_b_5_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist5_signX_uid25_fpToFxPTest_b_3(DELAY,91)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_signX_uid25_fpToFxPTest_b_3 ( .xin(redist4_signX_uid25_fpToFxPTest_b_2_q), .xout(redist5_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid28_fpToFxPTest(CONSTANT,27)
|
||||
assign udfExpVal_uid28_fpToFxPTest_q = 8'b01111101;
|
||||
|
|
@ -400,18 +382,28 @@ module acl_fp_ftoi (
|
|||
end
|
||||
assign udf_uid29_fpToFxPTest_n[0] = ~ (udf_uid29_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid29_fpToFxPTest_n_5(DELAY,87)
|
||||
dspba_delay_ver #( .width(1), .depth(4), .reset_kind("ASYNC") )
|
||||
redist1_udf_uid29_fpToFxPTest_n_5 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist1_udf_uid29_fpToFxPTest_n_5_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist2_udf_uid29_fpToFxPTest_n_3(DELAY,88)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist2_udf_uid29_fpToFxPTest_n_3 ( .xin(udf_uid29_fpToFxPTest_n), .xout(redist2_udf_uid29_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@4
|
||||
// sPostRnd_uid46_fpToFxPTest(BITSELECT,45)@2
|
||||
assign sPostRnd_uid46_fpToFxPTest_in = {{1{sPostRndFull_uid44_fpToFxPTest_q[33]}}, sPostRndFull_uid44_fpToFxPTest_q};
|
||||
assign sPostRnd_uid46_fpToFxPTest_b = sPostRnd_uid46_fpToFxPTest_in[34:1];
|
||||
|
||||
// rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@4
|
||||
// rndOvfPos_uid47_fpToFxPTest(COMPARE,46)@2 + 1
|
||||
assign rndOvfPos_uid47_fpToFxPTest_a = {4'b0000, maxPosValueS_uid39_fpToFxPTest_q};
|
||||
assign rndOvfPos_uid47_fpToFxPTest_b = {{2{sPostRnd_uid46_fpToFxPTest_b[33]}}, sPostRnd_uid46_fpToFxPTest_b};
|
||||
assign rndOvfPos_uid47_fpToFxPTest_o = $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b);
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
rndOvfPos_uid47_fpToFxPTest_o <= 36'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
rndOvfPos_uid47_fpToFxPTest_o <= $signed(rndOvfPos_uid47_fpToFxPTest_a) - $signed(rndOvfPos_uid47_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign rndOvfPos_uid47_fpToFxPTest_c[0] = rndOvfPos_uid47_fpToFxPTest_o[35];
|
||||
|
||||
// ovfExpVal_uid26_fpToFxPTest(CONSTANT,25)
|
||||
|
|
@ -433,21 +425,21 @@ module acl_fp_ftoi (
|
|||
end
|
||||
assign ovfExpRange_uid27_fpToFxPTest_n[0] = ~ (ovfExpRange_uid27_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovfExpRange_uid27_fpToFxPTest_n_4(DELAY,88)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist2_ovfExpRange_uid27_fpToFxPTest_n_4 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist3_ovfExpRange_uid27_fpToFxPTest_n_3(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_ovfExpRange_uid27_fpToFxPTest_n_3 ( .xin(ovfExpRange_uid27_fpToFxPTest_n), .xout(redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@2 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_2_q ? 1'b1 : 1'b0;
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist8_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,91)
|
||||
// redist6_fracXIsZero_uid13_fpToFxPTest_q_2(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist6_fracXIsZero_uid13_fpToFxPTest_q_2 ( .xin(fracXIsZero_uid13_fpToFxPTest_q), .xout(redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// cstAllOWE_uid6_fpToFxPTest(CONSTANT,5)
|
||||
assign cstAllOWE_uid6_fpToFxPTest_q = 8'b11111111;
|
||||
|
|
@ -457,28 +449,26 @@ module acl_fp_ftoi (
|
|||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist6_expXIsMax_uid12_fpToFxPTest_q_4(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist6_expXIsMax_uid12_fpToFxPTest_q_4 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist6_expXIsMax_uid12_fpToFxPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist7_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,93)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist7_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist7_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@4
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist6_expXIsMax_uid12_fpToFxPTest_q_4_q & redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q;
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@3
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@4
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist5_fracXIsZero_uid13_fpToFxPTest_q_2_q);
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (redist6_fracXIsZero_uid13_fpToFxPTest_q_2_q);
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@4
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist6_expXIsMax_uid12_fpToFxPTest_q_4_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@3
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist7_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@4 + 1
|
||||
assign ovfPostRnd_uid48_fpToFxPTest_qi = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist2_ovfExpRange_uid27_fpToFxPTest_n_4_q | rndOvfPos_uid47_fpToFxPTest_c;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
ovfPostRnd_uid48_fpToFxPTest_delay ( .xin(ovfPostRnd_uid48_fpToFxPTest_qi), .xout(ovfPostRnd_uid48_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// ovfPostRnd_uid48_fpToFxPTest(LOGICAL,47)@3
|
||||
assign ovfPostRnd_uid48_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | redist3_ovfExpRange_uid27_fpToFxPTest_n_3_q | rndOvfPos_uid47_fpToFxPTest_c;
|
||||
|
||||
// muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@5
|
||||
assign muxSelConc_uid49_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_5_q, redist1_udf_uid29_fpToFxPTest_n_5_q, ovfPostRnd_uid48_fpToFxPTest_q};
|
||||
// muxSelConc_uid49_fpToFxPTest(BITJOIN,48)@3
|
||||
assign muxSelConc_uid49_fpToFxPTest_q = {redist5_signX_uid25_fpToFxPTest_b_3_q, redist2_udf_uid29_fpToFxPTest_n_3_q, ovfPostRnd_uid48_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid50_fpToFxPTest(LOOKUP,49)@5
|
||||
// muxSel_uid50_fpToFxPTest(LOOKUP,49)@3
|
||||
always @(muxSelConc_uid49_fpToFxPTest_q)
|
||||
begin
|
||||
// Begin reserved scope level
|
||||
|
|
@ -499,7 +489,7 @@ module acl_fp_ftoi (
|
|||
// End reserved scope level
|
||||
end
|
||||
|
||||
// finalOut_uid52_fpToFxPTest(MUX,51)@5
|
||||
// finalOut_uid52_fpToFxPTest(MUX,51)@3
|
||||
assign finalOut_uid52_fpToFxPTest_s = muxSel_uid50_fpToFxPTest_q;
|
||||
always @(finalOut_uid52_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueS_uid39_fpToFxPTest_q or maxNegValueS_uid40_fpToFxPTest_q or maxNegValueU_uid51_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -512,7 +502,7 @@ module acl_fp_ftoi (
|
|||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@5
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid52_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fp_ftou
|
||||
// SystemVerilog created on Wed Aug 5 12:58:15 2020
|
||||
// SystemVerilog created on Mon Aug 31 06:15:18 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
@ -85,8 +85,7 @@ module acl_fp_ftou (
|
|||
wire [31:0] sPostRnd_uid45_fpToFxPTest_b;
|
||||
wire [33:0] sPostRndFullMSBU_uid46_fpToFxPTest_in;
|
||||
wire [0:0] sPostRndFullMSBU_uid46_fpToFxPTest_b;
|
||||
wire [0:0] ovfPostRnd_uid47_fpToFxPTest_qi;
|
||||
reg [0:0] ovfPostRnd_uid47_fpToFxPTest_q;
|
||||
wire [0:0] ovfPostRnd_uid47_fpToFxPTest_q;
|
||||
wire [2:0] muxSelConc_uid48_fpToFxPTest_q;
|
||||
reg [1:0] muxSel_uid49_fpToFxPTest_q;
|
||||
wire [1:0] finalOut_uid51_fpToFxPTest_s;
|
||||
|
|
@ -123,13 +122,12 @@ module acl_fp_ftou (
|
|||
wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
|
||||
wire [1:0] rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
|
||||
reg [31:0] redist0_sPostRnd_uid45_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist1_udf_uid30_fpToFxPTest_n_4_q;
|
||||
reg [0:0] redist2_ovf_uid27_fpToFxPTest_n_3_q;
|
||||
reg [0:0] redist3_signX_uid25_fpToFxPTest_b_3_q;
|
||||
reg [0:0] redist4_signX_uid25_fpToFxPTest_b_4_q;
|
||||
reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_3_q;
|
||||
reg [0:0] redist6_excZ_x_uid11_fpToFxPTest_q_2_q;
|
||||
reg [22:0] redist7_frac_x_uid10_fpToFxPTest_b_2_q;
|
||||
reg [5:0] redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
|
||||
reg [0:0] redist2_udf_uid30_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist3_ovf_uid27_fpToFxPTest_n_2_q;
|
||||
reg [0:0] redist4_signX_uid25_fpToFxPTest_b_2_q;
|
||||
reg [0:0] redist5_expXIsMax_uid12_fpToFxPTest_q_2_q;
|
||||
reg [22:0] redist6_frac_x_uid10_fpToFxPTest_b_1_q;
|
||||
|
||||
|
||||
// maxNegValueU_uid41_fpToFxPTest(CONSTANT,40)
|
||||
|
|
@ -147,70 +145,70 @@ module acl_fp_ftou (
|
|||
// rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,81)
|
||||
assign rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 3'b000;
|
||||
|
||||
// rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@2
|
||||
// rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,80)@1
|
||||
assign rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:3];
|
||||
|
||||
// rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@2
|
||||
// rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,82)@1
|
||||
assign rightShiftStage2Idx3_uid83_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx3Pad3_uid82_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx3Rng3_uid81_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,78)
|
||||
assign rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 2'b00;
|
||||
|
||||
// rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@2
|
||||
// rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,77)@1
|
||||
assign rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:2];
|
||||
|
||||
// rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@2
|
||||
// rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,79)@1
|
||||
assign rightShiftStage2Idx2_uid80_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage2Idx2Pad2_uid79_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage2Idx2Rng2_uid78_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@2
|
||||
// rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,74)@1
|
||||
assign rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:1];
|
||||
|
||||
// rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@2
|
||||
// rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,76)@1
|
||||
assign rightShiftStage2Idx1_uid77_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {GND_q, rightShiftStage2Idx1Rng1_uid75_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,70)
|
||||
assign rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 12'b000000000000;
|
||||
|
||||
// rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@2
|
||||
// rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,69)@1
|
||||
assign rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:12];
|
||||
|
||||
// rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@2
|
||||
// rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,71)@1
|
||||
assign rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx3Pad12_uid71_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx3Rng12_uid70_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// cstAllZWE_uid8_fpToFxPTest(CONSTANT,7)
|
||||
assign cstAllZWE_uid8_fpToFxPTest_q = 8'b00000000;
|
||||
|
||||
// rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@2
|
||||
// rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,66)@1
|
||||
assign rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:8];
|
||||
|
||||
// rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@2
|
||||
// rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,68)@1
|
||||
assign rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {cstAllZWE_uid8_fpToFxPTest_q, rightShiftStage1Idx2Rng8_uid67_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,64)
|
||||
assign rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 4'b0000;
|
||||
|
||||
// rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@2
|
||||
// rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,63)@1
|
||||
assign rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b = rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q[32:4];
|
||||
|
||||
// rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@2
|
||||
// rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,65)@1
|
||||
assign rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage1Idx1Pad4_uid65_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage1Idx1Rng4_uid64_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,60)
|
||||
assign rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 33'b000000000000000000000000000000000;
|
||||
|
||||
// rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@2
|
||||
// rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,57)@1
|
||||
assign rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:32];
|
||||
|
||||
// rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@2
|
||||
// rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,59)@1
|
||||
assign rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {maxNegValueU_uid41_fpToFxPTest_q, rightShiftStage0Idx2Rng32_uid58_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest(CONSTANT,55)
|
||||
assign rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q = 16'b0000000000000000;
|
||||
|
||||
// rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@2
|
||||
// rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest(BITSELECT,54)@1
|
||||
assign rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b = shifterIn_uid38_fpToFxPTest_q[32:16];
|
||||
|
||||
// rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@2
|
||||
// rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest(BITJOIN,56)@1
|
||||
assign rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q = {rightShiftStage0Idx1Pad16_uid56_rightShiferNoStickyOut_uid39_fpToFxPTest_q, rightShiftStage0Idx1Rng16_uid55_rightShiferNoStickyOut_uid39_fpToFxPTest_b};
|
||||
|
||||
// exp_x_uid9_fpToFxPTest(BITSELECT,8)@0
|
||||
|
|
@ -221,30 +219,26 @@ module acl_fp_ftou (
|
|||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
excZ_x_uid11_fpToFxPTest_delay ( .xin(excZ_x_uid11_fpToFxPTest_qi), .xout(excZ_x_uid11_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist6_excZ_x_uid11_fpToFxPTest_q_2(DELAY,93)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_excZ_x_uid11_fpToFxPTest_q_2 ( .xin(excZ_x_uid11_fpToFxPTest_q), .xout(redist6_excZ_x_uid11_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@2
|
||||
assign invExcXZ_uid22_fpToFxPTest_q = ~ (redist6_excZ_x_uid11_fpToFxPTest_q_2_q);
|
||||
// invExcXZ_uid22_fpToFxPTest(LOGICAL,21)@1
|
||||
assign invExcXZ_uid22_fpToFxPTest_q = ~ (excZ_x_uid11_fpToFxPTest_q);
|
||||
|
||||
// frac_x_uid10_fpToFxPTest(BITSELECT,9)@0
|
||||
assign frac_x_uid10_fpToFxPTest_b = a[22:0];
|
||||
|
||||
// redist7_frac_x_uid10_fpToFxPTest_b_2(DELAY,94)
|
||||
dspba_delay_ver #( .width(23), .depth(2), .reset_kind("ASYNC") )
|
||||
redist7_frac_x_uid10_fpToFxPTest_b_2 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist7_frac_x_uid10_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist6_frac_x_uid10_fpToFxPTest_b_1(DELAY,93)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_frac_x_uid10_fpToFxPTest_b_1 ( .xin(frac_x_uid10_fpToFxPTest_b), .xout(redist6_frac_x_uid10_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@2
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist7_frac_x_uid10_fpToFxPTest_b_2_q};
|
||||
// oFracX_uid23_fpToFxPTest(BITJOIN,22)@1
|
||||
assign oFracX_uid23_fpToFxPTest_q = {invExcXZ_uid22_fpToFxPTest_q, redist6_frac_x_uid10_fpToFxPTest_b_1_q};
|
||||
|
||||
// zPadd_uid37_fpToFxPTest(CONSTANT,36)
|
||||
assign zPadd_uid37_fpToFxPTest_q = 9'b000000000;
|
||||
|
||||
// shifterIn_uid38_fpToFxPTest(BITJOIN,37)@2
|
||||
// shifterIn_uid38_fpToFxPTest(BITJOIN,37)@1
|
||||
assign shifterIn_uid38_fpToFxPTest_q = {oFracX_uid23_fpToFxPTest_q, zPadd_uid37_fpToFxPTest_q};
|
||||
|
||||
// rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@2
|
||||
// rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,62)@1
|
||||
assign rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b;
|
||||
always @(rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or shifterIn_uid38_fpToFxPTest_q or rightShiftStage0Idx1_uid57_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx2_uid60_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage0Idx3_uid61_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -257,7 +251,7 @@ module acl_fp_ftou (
|
|||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@2
|
||||
// rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,73)@1
|
||||
assign rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c;
|
||||
always @(rightShiftStage1_uid74_rightShiferNoStickyOut_uid39_fpToFxPTest_s or en or rightShiftStage0_uid63_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx1_uid66_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx2_uid69_rightShiferNoStickyOut_uid39_fpToFxPTest_q or rightShiftStage1Idx3_uid72_rightShiferNoStickyOut_uid39_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -276,56 +270,53 @@ module acl_fp_ftou (
|
|||
// ovfExpVal_uid31_fpToFxPTest(CONSTANT,30)
|
||||
assign ovfExpVal_uid31_fpToFxPTest_q = 9'b010011110;
|
||||
|
||||
// shiftValE_uid32_fpToFxPTest(SUB,31)@0 + 1
|
||||
// shiftValE_uid32_fpToFxPTest(SUB,31)@0
|
||||
assign shiftValE_uid32_fpToFxPTest_a = {{2{ovfExpVal_uid31_fpToFxPTest_q[8]}}, ovfExpVal_uid31_fpToFxPTest_q};
|
||||
assign shiftValE_uid32_fpToFxPTest_b = {3'b000, exp_x_uid9_fpToFxPTest_b};
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftValE_uid32_fpToFxPTest_o <= 11'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
shiftValE_uid32_fpToFxPTest_o <= $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftValE_uid32_fpToFxPTest_o = $signed(shiftValE_uid32_fpToFxPTest_a) - $signed(shiftValE_uid32_fpToFxPTest_b);
|
||||
assign shiftValE_uid32_fpToFxPTest_q = shiftValE_uid32_fpToFxPTest_o[9:0];
|
||||
|
||||
// shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@1
|
||||
// shiftValRaw_uid33_fpToFxPTest(BITSELECT,32)@0
|
||||
assign shiftValRaw_uid33_fpToFxPTest_in = shiftValE_uid32_fpToFxPTest_q[5:0];
|
||||
assign shiftValRaw_uid33_fpToFxPTest_b = shiftValRaw_uid33_fpToFxPTest_in[5:0];
|
||||
|
||||
// shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@1
|
||||
// redist1_shiftValRaw_uid33_fpToFxPTest_b_1(DELAY,88)
|
||||
dspba_delay_ver #( .width(6), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_shiftValRaw_uid33_fpToFxPTest_b_1 ( .xin(shiftValRaw_uid33_fpToFxPTest_b), .xout(redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// shiftOutOfRange_uid35_fpToFxPTest(COMPARE,34)@0 + 1
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_a = {{2{shiftValE_uid32_fpToFxPTest_q[9]}}, shiftValE_uid32_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_b = {6'b000000, maxShiftCst_uid34_fpToFxPTest_q};
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_o = $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b);
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]);
|
||||
|
||||
// shiftVal_uid36_fpToFxPTest(MUX,35)@1 + 1
|
||||
assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
shiftVal_uid36_fpToFxPTest_q <= 6'b0;
|
||||
shiftOutOfRange_uid35_fpToFxPTest_o <= 12'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (shiftVal_uid36_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid36_fpToFxPTest_q <= shiftValRaw_uid33_fpToFxPTest_b;
|
||||
1'b1 : shiftVal_uid36_fpToFxPTest_q <= maxShiftCst_uid34_fpToFxPTest_q;
|
||||
default : shiftVal_uid36_fpToFxPTest_q <= 6'b0;
|
||||
endcase
|
||||
shiftOutOfRange_uid35_fpToFxPTest_o <= $signed(shiftOutOfRange_uid35_fpToFxPTest_a) - $signed(shiftOutOfRange_uid35_fpToFxPTest_b);
|
||||
end
|
||||
end
|
||||
assign shiftOutOfRange_uid35_fpToFxPTest_n[0] = ~ (shiftOutOfRange_uid35_fpToFxPTest_o[11]);
|
||||
|
||||
// rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@2
|
||||
// shiftVal_uid36_fpToFxPTest(MUX,35)@1
|
||||
assign shiftVal_uid36_fpToFxPTest_s = shiftOutOfRange_uid35_fpToFxPTest_n;
|
||||
always @(shiftVal_uid36_fpToFxPTest_s or en or redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q or maxShiftCst_uid34_fpToFxPTest_q)
|
||||
begin
|
||||
unique case (shiftVal_uid36_fpToFxPTest_s)
|
||||
1'b0 : shiftVal_uid36_fpToFxPTest_q = redist1_shiftValRaw_uid33_fpToFxPTest_b_1_q;
|
||||
1'b1 : shiftVal_uid36_fpToFxPTest_q = maxShiftCst_uid34_fpToFxPTest_q;
|
||||
default : shiftVal_uid36_fpToFxPTest_q = 6'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select(BITSELECT,86)@1
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_b = shiftVal_uid36_fpToFxPTest_q[5:4];
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_c = shiftVal_uid36_fpToFxPTest_q[3:2];
|
||||
assign rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d = shiftVal_uid36_fpToFxPTest_q[1:0];
|
||||
|
||||
// rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@2 + 1
|
||||
// rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest(MUX,84)@1 + 1
|
||||
assign rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_s = rightShiftStageSel5Dto4_uid62_rightShiferNoStickyOut_uid39_fpToFxPTest_merged_bit_select_d;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
|
|
@ -345,16 +336,16 @@ module acl_fp_ftou (
|
|||
end
|
||||
end
|
||||
|
||||
// zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@3
|
||||
// zRightShiferNoStickyOut_uid43_fpToFxPTest(BITJOIN,42)@2
|
||||
assign zRightShiferNoStickyOut_uid43_fpToFxPTest_q = {GND_q, rightShiftStage2_uid85_rightShiferNoStickyOut_uid39_fpToFxPTest_q};
|
||||
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@3
|
||||
// sPostRndFull_uid44_fpToFxPTest(ADD,43)@2
|
||||
assign sPostRndFull_uid44_fpToFxPTest_a = {1'b0, zRightShiferNoStickyOut_uid43_fpToFxPTest_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_b = {34'b0000000000000000000000000000000000, VCC_q};
|
||||
assign sPostRndFull_uid44_fpToFxPTest_o = $unsigned(sPostRndFull_uid44_fpToFxPTest_a) + $unsigned(sPostRndFull_uid44_fpToFxPTest_b);
|
||||
assign sPostRndFull_uid44_fpToFxPTest_q = sPostRndFull_uid44_fpToFxPTest_o[34:0];
|
||||
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@3
|
||||
// sPostRnd_uid45_fpToFxPTest(BITSELECT,44)@2
|
||||
assign sPostRnd_uid45_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[32:0];
|
||||
assign sPostRnd_uid45_fpToFxPTest_b = sPostRnd_uid45_fpToFxPTest_in[32:1];
|
||||
|
||||
|
|
@ -365,13 +356,9 @@ module acl_fp_ftou (
|
|||
// signX_uid25_fpToFxPTest(BITSELECT,24)@0
|
||||
assign signX_uid25_fpToFxPTest_b = a[31:31];
|
||||
|
||||
// redist3_signX_uid25_fpToFxPTest_b_3(DELAY,90)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist3_signX_uid25_fpToFxPTest_b_3 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist3_signX_uid25_fpToFxPTest_b_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_signX_uid25_fpToFxPTest_b_4(DELAY,91)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist4_signX_uid25_fpToFxPTest_b_4 ( .xin(redist3_signX_uid25_fpToFxPTest_b_3_q), .xout(redist4_signX_uid25_fpToFxPTest_b_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist4_signX_uid25_fpToFxPTest_b_2(DELAY,91)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist4_signX_uid25_fpToFxPTest_b_2 ( .xin(signX_uid25_fpToFxPTest_b), .xout(redist4_signX_uid25_fpToFxPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udfExpVal_uid29_fpToFxPTest(CONSTANT,28)
|
||||
assign udfExpVal_uid29_fpToFxPTest_q = 8'b01111101;
|
||||
|
|
@ -392,11 +379,11 @@ module acl_fp_ftou (
|
|||
end
|
||||
assign udf_uid30_fpToFxPTest_n[0] = ~ (udf_uid30_fpToFxPTest_o[10]);
|
||||
|
||||
// redist1_udf_uid30_fpToFxPTest_n_4(DELAY,88)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist1_udf_uid30_fpToFxPTest_n_4 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist1_udf_uid30_fpToFxPTest_n_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist2_udf_uid30_fpToFxPTest_n_2(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist2_udf_uid30_fpToFxPTest_n_2 ( .xin(udf_uid30_fpToFxPTest_n), .xout(redist2_udf_uid30_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@3
|
||||
// sPostRndFullMSBU_uid46_fpToFxPTest(BITSELECT,45)@2
|
||||
assign sPostRndFullMSBU_uid46_fpToFxPTest_in = sPostRndFull_uid44_fpToFxPTest_q[33:0];
|
||||
assign sPostRndFullMSBU_uid46_fpToFxPTest_b = sPostRndFullMSBU_uid46_fpToFxPTest_in[33:33];
|
||||
|
||||
|
|
@ -419,18 +406,18 @@ module acl_fp_ftou (
|
|||
end
|
||||
assign ovf_uid27_fpToFxPTest_n[0] = ~ (ovf_uid27_fpToFxPTest_o[10]);
|
||||
|
||||
// redist2_ovf_uid27_fpToFxPTest_n_3(DELAY,89)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist2_ovf_uid27_fpToFxPTest_n_3 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist2_ovf_uid27_fpToFxPTest_n_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist3_ovf_uid27_fpToFxPTest_n_2(DELAY,90)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist3_ovf_uid27_fpToFxPTest_n_2 ( .xin(ovf_uid27_fpToFxPTest_n), .xout(redist3_ovf_uid27_fpToFxPTest_n_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@3
|
||||
assign negOrOvf_uid28_fpToFxPTest_q = redist3_signX_uid25_fpToFxPTest_b_3_q | redist2_ovf_uid27_fpToFxPTest_n_3_q;
|
||||
// negOrOvf_uid28_fpToFxPTest(LOGICAL,27)@2
|
||||
assign negOrOvf_uid28_fpToFxPTest_q = redist4_signX_uid25_fpToFxPTest_b_2_q | redist3_ovf_uid27_fpToFxPTest_n_2_q;
|
||||
|
||||
// cstZeroWF_uid7_fpToFxPTest(CONSTANT,6)
|
||||
assign cstZeroWF_uid7_fpToFxPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@2 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist7_frac_x_uid10_fpToFxPTest_b_2_q ? 1'b1 : 1'b0;
|
||||
// fracXIsZero_uid13_fpToFxPTest(LOGICAL,12)@1 + 1
|
||||
assign fracXIsZero_uid13_fpToFxPTest_qi = cstZeroWF_uid7_fpToFxPTest_q == redist6_frac_x_uid10_fpToFxPTest_b_1_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
fracXIsZero_uid13_fpToFxPTest_delay ( .xin(fracXIsZero_uid13_fpToFxPTest_qi), .xout(fracXIsZero_uid13_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
|
|
@ -442,49 +429,52 @@ module acl_fp_ftou (
|
|||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
expXIsMax_uid12_fpToFxPTest_delay ( .xin(expXIsMax_uid12_fpToFxPTest_qi), .xout(expXIsMax_uid12_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist5_expXIsMax_uid12_fpToFxPTest_q_3(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist5_expXIsMax_uid12_fpToFxPTest_q_3 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist5_expXIsMax_uid12_fpToFxPTest_q_2(DELAY,92)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist5_expXIsMax_uid12_fpToFxPTest_q_2 ( .xin(expXIsMax_uid12_fpToFxPTest_q), .xout(redist5_expXIsMax_uid12_fpToFxPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@3
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
// excI_x_uid15_fpToFxPTest(LOGICAL,14)@2
|
||||
assign excI_x_uid15_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsZero_uid13_fpToFxPTest_q;
|
||||
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@3
|
||||
// fracXIsNotZero_uid14_fpToFxPTest(LOGICAL,13)@2
|
||||
assign fracXIsNotZero_uid14_fpToFxPTest_q = ~ (fracXIsZero_uid13_fpToFxPTest_q);
|
||||
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@3
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_3_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
// excN_x_uid16_fpToFxPTest(LOGICAL,15)@2
|
||||
assign excN_x_uid16_fpToFxPTest_q = redist5_expXIsMax_uid12_fpToFxPTest_q_2_q & fracXIsNotZero_uid14_fpToFxPTest_q;
|
||||
|
||||
// ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@3 + 1
|
||||
assign ovfPostRnd_uid47_fpToFxPTest_qi = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
ovfPostRnd_uid47_fpToFxPTest_delay ( .xin(ovfPostRnd_uid47_fpToFxPTest_qi), .xout(ovfPostRnd_uid47_fpToFxPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// ovfPostRnd_uid47_fpToFxPTest(LOGICAL,46)@2
|
||||
assign ovfPostRnd_uid47_fpToFxPTest_q = excN_x_uid16_fpToFxPTest_q | excI_x_uid15_fpToFxPTest_q | negOrOvf_uid28_fpToFxPTest_q | sPostRndFullMSBU_uid46_fpToFxPTest_b;
|
||||
|
||||
// muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@4
|
||||
assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_4_q, redist1_udf_uid30_fpToFxPTest_n_4_q, ovfPostRnd_uid47_fpToFxPTest_q};
|
||||
// muxSelConc_uid48_fpToFxPTest(BITJOIN,47)@2
|
||||
assign muxSelConc_uid48_fpToFxPTest_q = {redist4_signX_uid25_fpToFxPTest_b_2_q, redist2_udf_uid30_fpToFxPTest_n_2_q, ovfPostRnd_uid47_fpToFxPTest_q};
|
||||
|
||||
// muxSel_uid49_fpToFxPTest(LOOKUP,48)@4
|
||||
always @(muxSelConc_uid48_fpToFxPTest_q)
|
||||
// muxSel_uid49_fpToFxPTest(LOOKUP,48)@2 + 1
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
// Begin reserved scope level
|
||||
unique case (muxSelConc_uid48_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid49_fpToFxPTest_q = 2'b00;
|
||||
3'b001 : muxSel_uid49_fpToFxPTest_q = 2'b01;
|
||||
3'b010 : muxSel_uid49_fpToFxPTest_q = 2'b11;
|
||||
3'b011 : muxSel_uid49_fpToFxPTest_q = 2'b00;
|
||||
3'b100 : muxSel_uid49_fpToFxPTest_q = 2'b10;
|
||||
3'b101 : muxSel_uid49_fpToFxPTest_q = 2'b10;
|
||||
3'b110 : muxSel_uid49_fpToFxPTest_q = 2'b10;
|
||||
3'b111 : muxSel_uid49_fpToFxPTest_q = 2'b10;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid49_fpToFxPTest_q = 2'bxx;
|
||||
end
|
||||
endcase
|
||||
// End reserved scope level
|
||||
if (areset)
|
||||
begin
|
||||
muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (muxSelConc_uid48_fpToFxPTest_q)
|
||||
3'b000 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
3'b001 : muxSel_uid49_fpToFxPTest_q <= 2'b01;
|
||||
3'b010 : muxSel_uid49_fpToFxPTest_q <= 2'b11;
|
||||
3'b011 : muxSel_uid49_fpToFxPTest_q <= 2'b00;
|
||||
3'b100 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b101 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b110 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
3'b111 : muxSel_uid49_fpToFxPTest_q <= 2'b10;
|
||||
default : begin
|
||||
// unreachable
|
||||
muxSel_uid49_fpToFxPTest_q <= 2'bxx;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// finalOut_uid51_fpToFxPTest(MUX,50)@4
|
||||
// finalOut_uid51_fpToFxPTest(MUX,50)@3
|
||||
assign finalOut_uid51_fpToFxPTest_s = muxSel_uid49_fpToFxPTest_q;
|
||||
always @(finalOut_uid51_fpToFxPTest_s or en or redist0_sPostRnd_uid45_fpToFxPTest_b_1_q or maxPosValueU_uid40_fpToFxPTest_q or maxNegValueU_uid41_fpToFxPTest_q)
|
||||
begin
|
||||
|
|
@ -497,7 +487,7 @@ module acl_fp_ftou (
|
|||
endcase
|
||||
end
|
||||
|
||||
// xOut(GPOUT,4)@4
|
||||
// xOut(GPOUT,4)@3
|
||||
assign q = finalOut_uid51_fpToFxPTest_q;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fp_itof
|
||||
// SystemVerilog created on Wed Aug 5 12:58:15 2020
|
||||
// SystemVerilog created on Mon Aug 31 06:15:18 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
@ -31,7 +31,8 @@ module acl_fp_itof (
|
|||
wire [0:0] GND_q;
|
||||
wire [0:0] signX_uid6_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_b;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_q;
|
||||
wire [31:0] xXorSign_uid7_fxpToFPTest_qi;
|
||||
reg [31:0] xXorSign_uid7_fxpToFPTest_q;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_a;
|
||||
wire [32:0] yE_uid8_fxpToFPTest_b;
|
||||
logic [32:0] yE_uid8_fxpToFPTest_o;
|
||||
|
|
@ -50,8 +51,7 @@ module acl_fp_itof (
|
|||
wire [0:0] sticky_uid20_fxpToFPTest_qi;
|
||||
reg [0:0] sticky_uid20_fxpToFPTest_q;
|
||||
wire [0:0] nr_uid21_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid22_fxpToFPTest_qi;
|
||||
reg [0:0] rnd_uid22_fxpToFPTest_q;
|
||||
wire [0:0] rnd_uid22_fxpToFPTest_q;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_a;
|
||||
wire [34:0] expFracR_uid24_fxpToFPTest_b;
|
||||
logic [34:0] expFracR_uid24_fxpToFPTest_o;
|
||||
|
|
@ -131,27 +131,30 @@ module acl_fp_itof (
|
|||
wire [30:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_in;
|
||||
wire [23:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_b;
|
||||
wire [6:0] fracRnd_uid15_fxpToFPTest_merged_bit_select_c;
|
||||
reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q;
|
||||
reg [0:0] redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
|
||||
reg [0:0] redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q;
|
||||
reg [9:0] redist6_expR_uid26_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
reg [32:0] redist8_expFracRnd_uid16_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist9_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist10_y_uid9_fxpToFPTest_b_1_q;
|
||||
reg [31:0] redist11_y_uid9_fxpToFPTest_b_2_q;
|
||||
reg [0:0] redist12_signX_uid6_fxpToFPTest_b_8_q;
|
||||
reg [23:0] redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q;
|
||||
reg [0:0] redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q;
|
||||
reg [0:0] redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q;
|
||||
reg [9:0] redist5_expR_uid26_fxpToFPTest_b_1_q;
|
||||
reg [22:0] redist6_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist7_sticky_uid20_fxpToFPTest_q_2_q;
|
||||
reg [0:0] redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
reg [31:0] redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist10_signX_uid6_fxpToFPTest_b_1_q;
|
||||
reg [0:0] redist11_signX_uid6_fxpToFPTest_b_7_q;
|
||||
|
||||
|
||||
// signX_uid6_fxpToFPTest(BITSELECT,5)@0
|
||||
assign signX_uid6_fxpToFPTest_b = a[31:31];
|
||||
|
||||
// redist12_signX_uid6_fxpToFPTest_b_8(DELAY,107)
|
||||
dspba_delay_ver #( .width(1), .depth(8), .reset_kind("ASYNC") )
|
||||
redist12_signX_uid6_fxpToFPTest_b_8 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist12_signX_uid6_fxpToFPTest_b_8_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist10_signX_uid6_fxpToFPTest_b_1(DELAY,105)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist10_signX_uid6_fxpToFPTest_b_1 ( .xin(signX_uid6_fxpToFPTest_b), .xout(redist10_signX_uid6_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist11_signX_uid6_fxpToFPTest_b_7(DELAY,106)
|
||||
dspba_delay_ver #( .width(1), .depth(6), .reset_kind("ASYNC") )
|
||||
redist11_signX_uid6_fxpToFPTest_b_7 ( .xin(redist10_signX_uid6_fxpToFPTest_b_1_q), .xout(redist11_signX_uid6_fxpToFPTest_b_7_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expInf_uid28_fxpToFPTest(CONSTANT,27)
|
||||
assign expInf_uid28_fxpToFPTest_q = 8'b11111111;
|
||||
|
|
@ -159,14 +162,14 @@ module acl_fp_itof (
|
|||
// expZ_uid37_fxpToFPTest(CONSTANT,36)
|
||||
assign expZ_uid37_fxpToFPTest_q = 8'b00000000;
|
||||
|
||||
// rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@5
|
||||
// rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,93)@4
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[31:31];
|
||||
assign rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
|
||||
// GND(CONSTANT,0)
|
||||
assign GND_q = 1'b0;
|
||||
|
||||
// cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@5
|
||||
// cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,79)@4
|
||||
assign cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, GND_q};
|
||||
|
||||
// rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,92)@4
|
||||
|
|
@ -179,14 +182,14 @@ module acl_fp_itof (
|
|||
// cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,72)@4
|
||||
assign cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@4
|
||||
// rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,91)@3
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[31:28];
|
||||
assign rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q[27:0];
|
||||
|
||||
// zs_uid61_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,60)
|
||||
assign zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q = 4'b0000;
|
||||
|
||||
// cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@4
|
||||
// cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,65)@3
|
||||
assign cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q = {rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_c, zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select(BITSELECT,90)@3
|
||||
|
|
@ -209,39 +212,37 @@ module acl_fp_itof (
|
|||
// zs_uid42_lzcShifterZ1_uid10_fxpToFPTest(CONSTANT,41)
|
||||
assign zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b00000000000000000000000000000000;
|
||||
|
||||
// xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0
|
||||
// xXorSign_uid7_fxpToFPTest(LOGICAL,6)@0 + 1
|
||||
assign xXorSign_uid7_fxpToFPTest_b = {{31{signX_uid6_fxpToFPTest_b[0]}}, signX_uid6_fxpToFPTest_b};
|
||||
assign xXorSign_uid7_fxpToFPTest_q = a ^ xXorSign_uid7_fxpToFPTest_b;
|
||||
assign xXorSign_uid7_fxpToFPTest_qi = a ^ xXorSign_uid7_fxpToFPTest_b;
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
xXorSign_uid7_fxpToFPTest_delay ( .xin(xXorSign_uid7_fxpToFPTest_qi), .xout(xXorSign_uid7_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// yE_uid8_fxpToFPTest(ADD,7)@0
|
||||
// yE_uid8_fxpToFPTest(ADD,7)@1
|
||||
assign yE_uid8_fxpToFPTest_a = {1'b0, xXorSign_uid7_fxpToFPTest_q};
|
||||
assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, signX_uid6_fxpToFPTest_b};
|
||||
assign yE_uid8_fxpToFPTest_b = {32'b00000000000000000000000000000000, redist10_signX_uid6_fxpToFPTest_b_1_q};
|
||||
assign yE_uid8_fxpToFPTest_o = $unsigned(yE_uid8_fxpToFPTest_a) + $unsigned(yE_uid8_fxpToFPTest_b);
|
||||
assign yE_uid8_fxpToFPTest_q = yE_uid8_fxpToFPTest_o[32:0];
|
||||
|
||||
// y_uid9_fxpToFPTest(BITSELECT,8)@0
|
||||
// y_uid9_fxpToFPTest(BITSELECT,8)@1
|
||||
assign y_uid9_fxpToFPTest_in = yE_uid8_fxpToFPTest_q[31:0];
|
||||
assign y_uid9_fxpToFPTest_b = y_uid9_fxpToFPTest_in[31:0];
|
||||
|
||||
// redist10_y_uid9_fxpToFPTest_b_1(DELAY,105)
|
||||
// redist9_y_uid9_fxpToFPTest_b_1(DELAY,104)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist10_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist10_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist11_y_uid9_fxpToFPTest_b_2(DELAY,106)
|
||||
dspba_delay_ver #( .width(32), .depth(1), .reset_kind("ASYNC") )
|
||||
redist11_y_uid9_fxpToFPTest_b_2 ( .xin(redist10_y_uid9_fxpToFPTest_b_1_q), .xout(redist11_y_uid9_fxpToFPTest_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist9_y_uid9_fxpToFPTest_b_1 ( .xin(y_uid9_fxpToFPTest_b), .xout(redist9_y_uid9_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,43)@1 + 1
|
||||
assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = redist10_y_uid9_fxpToFPTest_b_1_q == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
assign vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi = y_uid9_fxpToFPTest_b == zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_delay ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_qi), .xout(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest(MUX,45)@2
|
||||
assign vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist11_y_uid9_fxpToFPTest_b_2_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
always @(vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s or en or redist9_y_uid9_fxpToFPTest_b_1_q or zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist11_y_uid9_fxpToFPTest_b_2_q;
|
||||
1'b0 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = redist9_y_uid9_fxpToFPTest_b_1_q;
|
||||
1'b1 : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = zs_uid42_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid46_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
|
|
@ -271,63 +272,56 @@ module acl_fp_itof (
|
|||
// vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,55)@3
|
||||
assign vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid55_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == expZ_uid37_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3 + 1
|
||||
// vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest(MUX,59)@3
|
||||
assign vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@3
|
||||
assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@3 + 1
|
||||
assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid53_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid59_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,62)@4
|
||||
assign vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid62_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid61_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest(MUX,66)@4
|
||||
assign vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid60_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid66_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,69)@4
|
||||
assign vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid69_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == zs_uid68_lzcShifterZ1_uid10_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4 + 1
|
||||
// vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest(MUX,73)@4
|
||||
assign vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @ (posedge clk or posedge areset)
|
||||
always @(vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
unique case (vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_s)
|
||||
1'b0 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = vStagei_uid67_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
1'b1 : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = cStage_uid73_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
default : vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q = 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@5
|
||||
// vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest(LOGICAL,76)@4
|
||||
assign vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q = rVStage_uid76_lzcShifterZ1_uid10_fxpToFPTest_merged_bit_select_b == GND_q ? 1'b1 : 1'b0;
|
||||
|
||||
// vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@5
|
||||
// vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest(MUX,80)@4
|
||||
assign vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s = vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q;
|
||||
always @(vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_s or en or vStagei_uid74_lzcShifterZ1_uid10_fxpToFPTest_q or cStage_uid80_lzcShifterZ1_uid10_fxpToFPTest_q)
|
||||
begin
|
||||
|
|
@ -338,52 +332,60 @@ module acl_fp_itof (
|
|||
endcase
|
||||
end
|
||||
|
||||
// fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@5
|
||||
// fracRnd_uid15_fxpToFPTest_merged_bit_select(BITSELECT,94)@4
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_in = vStagei_uid81_lzcShifterZ1_uid10_fxpToFPTest_q[30:0];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_b = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[30:7];
|
||||
assign fracRnd_uid15_fxpToFPTest_merged_bit_select_c = fracRnd_uid15_fxpToFPTest_merged_bit_select_in[6:0];
|
||||
|
||||
// sticky_uid20_fxpToFPTest(LOGICAL,19)@5 + 1
|
||||
// sticky_uid20_fxpToFPTest(LOGICAL,19)@4 + 1
|
||||
assign sticky_uid20_fxpToFPTest_qi = fracRnd_uid15_fxpToFPTest_merged_bit_select_c != 7'b0000000 ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
sticky_uid20_fxpToFPTest_delay ( .xin(sticky_uid20_fxpToFPTest_qi), .xout(sticky_uid20_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist7_sticky_uid20_fxpToFPTest_q_2(DELAY,102)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist7_sticky_uid20_fxpToFPTest_q_2 ( .xin(sticky_uid20_fxpToFPTest_q), .xout(redist7_sticky_uid20_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// nr_uid21_fxpToFPTest(LOGICAL,20)@6
|
||||
assign nr_uid21_fxpToFPTest_q = ~ (l_uid17_fxpToFPTest_merged_bit_select_c);
|
||||
|
||||
// l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid22_fxpToFPTest(LOGICAL,21)@6
|
||||
assign rnd_uid22_fxpToFPTest_q = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | redist7_sticky_uid20_fxpToFPTest_q_2_q;
|
||||
|
||||
// maxCount_uid11_fxpToFPTest(CONSTANT,10)
|
||||
assign maxCount_uid11_fxpToFPTest_q = 6'b100000;
|
||||
|
||||
// redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4(DELAY,100)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
|
||||
dspba_delay_ver #( .width(1), .depth(3), .reset_kind("ASYNC") )
|
||||
redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
|
||||
// redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3(DELAY,99)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3 ( .xin(vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
|
||||
// redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2(DELAY,98)
|
||||
dspba_delay_ver #( .width(1), .depth(2), .reset_kind("ASYNC") )
|
||||
redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2 ( .xin(vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,97)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
|
||||
// redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1(DELAY,96)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1 ( .xin(vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q), .xout(redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@5
|
||||
assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist5_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_4_q, redist4_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
// vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest(BITJOIN,81)@4
|
||||
assign vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q = {redist4_vCount_uid44_lzcShifterZ1_uid10_fxpToFPTest_q_3_q, redist3_vCount_uid49_lzcShifterZ1_uid10_fxpToFPTest_q_2_q, redist2_vCount_uid56_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, redist1_vCount_uid63_lzcShifterZ1_uid10_fxpToFPTest_q_1_q, vCount_uid70_lzcShifterZ1_uid10_fxpToFPTest_q, vCount_uid77_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
|
||||
// vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@5
|
||||
// vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest(COMPARE,83)@4
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a = {2'b00, maxCount_uid11_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b = {2'b00, vCount_uid82_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o = $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_a) - $unsigned(vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_b);
|
||||
assign vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c[0] = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_o[7];
|
||||
|
||||
// vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@5 + 1
|
||||
// vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest(MUX,85)@4 + 1
|
||||
assign vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_s = vCountBig_uid84_lzcShifterZ1_uid10_fxpToFPTest_c;
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
|
|
@ -404,78 +406,74 @@ module acl_fp_itof (
|
|||
// msbIn_uid13_fxpToFPTest(CONSTANT,12)
|
||||
assign msbIn_uid13_fxpToFPTest_q = 8'b10011110;
|
||||
|
||||
// expPreRnd_uid14_fxpToFPTest(SUB,13)@6
|
||||
// expPreRnd_uid14_fxpToFPTest(SUB,13)@5 + 1
|
||||
assign expPreRnd_uid14_fxpToFPTest_a = {1'b0, msbIn_uid13_fxpToFPTest_q};
|
||||
assign expPreRnd_uid14_fxpToFPTest_b = {3'b000, vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q};
|
||||
assign expPreRnd_uid14_fxpToFPTest_o = $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
|
||||
always @ (posedge clk or posedge areset)
|
||||
begin
|
||||
if (areset)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= 9'b0;
|
||||
end
|
||||
else if (en == 1'b1)
|
||||
begin
|
||||
expPreRnd_uid14_fxpToFPTest_o <= $unsigned(expPreRnd_uid14_fxpToFPTest_a) - $unsigned(expPreRnd_uid14_fxpToFPTest_b);
|
||||
end
|
||||
end
|
||||
assign expPreRnd_uid14_fxpToFPTest_q = expPreRnd_uid14_fxpToFPTest_o[8:0];
|
||||
|
||||
// redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1(DELAY,95)
|
||||
dspba_delay_ver #( .width(24), .depth(1), .reset_kind("ASYNC") )
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
// redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2(DELAY,95)
|
||||
dspba_delay_ver #( .width(24), .depth(2), .reset_kind("ASYNC") )
|
||||
redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2 ( .xin(fracRnd_uid15_fxpToFPTest_merged_bit_select_b), .xout(redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expFracRnd_uid16_fxpToFPTest(BITJOIN,15)@6
|
||||
assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_1_q};
|
||||
assign expFracRnd_uid16_fxpToFPTest_q = {expPreRnd_uid14_fxpToFPTest_q, redist0_fracRnd_uid15_fxpToFPTest_merged_bit_select_b_2_q};
|
||||
|
||||
// l_uid17_fxpToFPTest_merged_bit_select(BITSELECT,88)@6
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_in = expFracRnd_uid16_fxpToFPTest_q[1:0];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_b = l_uid17_fxpToFPTest_merged_bit_select_in[1:1];
|
||||
assign l_uid17_fxpToFPTest_merged_bit_select_c = l_uid17_fxpToFPTest_merged_bit_select_in[0:0];
|
||||
|
||||
// rnd_uid22_fxpToFPTest(LOGICAL,21)@6 + 1
|
||||
assign rnd_uid22_fxpToFPTest_qi = l_uid17_fxpToFPTest_merged_bit_select_b | nr_uid21_fxpToFPTest_q | sticky_uid20_fxpToFPTest_q;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
rnd_uid22_fxpToFPTest_delay ( .xin(rnd_uid22_fxpToFPTest_qi), .xout(rnd_uid22_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist8_expFracRnd_uid16_fxpToFPTest_q_1(DELAY,103)
|
||||
dspba_delay_ver #( .width(33), .depth(1), .reset_kind("ASYNC") )
|
||||
redist8_expFracRnd_uid16_fxpToFPTest_q_1 ( .xin(expFracRnd_uid16_fxpToFPTest_q), .xout(redist8_expFracRnd_uid16_fxpToFPTest_q_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expFracR_uid24_fxpToFPTest(ADD,23)@7
|
||||
assign expFracR_uid24_fxpToFPTest_a = {{2{redist8_expFracRnd_uid16_fxpToFPTest_q_1_q[32]}}, redist8_expFracRnd_uid16_fxpToFPTest_q_1_q};
|
||||
// expFracR_uid24_fxpToFPTest(ADD,23)@6
|
||||
assign expFracR_uid24_fxpToFPTest_a = {{2{expFracRnd_uid16_fxpToFPTest_q[32]}}, expFracRnd_uid16_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_b = {34'b0000000000000000000000000000000000, rnd_uid22_fxpToFPTest_q};
|
||||
assign expFracR_uid24_fxpToFPTest_o = $signed(expFracR_uid24_fxpToFPTest_a) + $signed(expFracR_uid24_fxpToFPTest_b);
|
||||
assign expFracR_uid24_fxpToFPTest_q = expFracR_uid24_fxpToFPTest_o[33:0];
|
||||
|
||||
// expR_uid26_fxpToFPTest(BITSELECT,25)@7
|
||||
// expR_uid26_fxpToFPTest(BITSELECT,25)@6
|
||||
assign expR_uid26_fxpToFPTest_b = expFracR_uid24_fxpToFPTest_q[33:24];
|
||||
|
||||
// redist6_expR_uid26_fxpToFPTest_b_1(DELAY,101)
|
||||
// redist5_expR_uid26_fxpToFPTest_b_1(DELAY,100)
|
||||
dspba_delay_ver #( .width(10), .depth(1), .reset_kind("ASYNC") )
|
||||
redist6_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist6_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist5_expR_uid26_fxpToFPTest_b_1 ( .xin(expR_uid26_fxpToFPTest_b), .xout(redist5_expR_uid26_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// expR_uid38_fxpToFPTest(BITSELECT,37)@8
|
||||
assign expR_uid38_fxpToFPTest_in = redist6_expR_uid26_fxpToFPTest_b_1_q[7:0];
|
||||
// expR_uid38_fxpToFPTest(BITSELECT,37)@7
|
||||
assign expR_uid38_fxpToFPTest_in = redist5_expR_uid26_fxpToFPTest_b_1_q[7:0];
|
||||
assign expR_uid38_fxpToFPTest_b = expR_uid38_fxpToFPTest_in[7:0];
|
||||
|
||||
// ovf_uid29_fxpToFPTest(COMPARE,28)@8
|
||||
assign ovf_uid29_fxpToFPTest_a = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
// ovf_uid29_fxpToFPTest(COMPARE,28)@7
|
||||
assign ovf_uid29_fxpToFPTest_a = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign ovf_uid29_fxpToFPTest_b = {4'b0000, expInf_uid28_fxpToFPTest_q};
|
||||
assign ovf_uid29_fxpToFPTest_o = $signed(ovf_uid29_fxpToFPTest_a) - $signed(ovf_uid29_fxpToFPTest_b);
|
||||
assign ovf_uid29_fxpToFPTest_n[0] = ~ (ovf_uid29_fxpToFPTest_o[11]);
|
||||
|
||||
// inIsZero_uid12_fxpToFPTest(LOGICAL,11)@6 + 1
|
||||
// inIsZero_uid12_fxpToFPTest(LOGICAL,11)@5 + 1
|
||||
assign inIsZero_uid12_fxpToFPTest_qi = vCountFinal_uid86_lzcShifterZ1_uid10_fxpToFPTest_q == maxCount_uid11_fxpToFPTest_q ? 1'b1 : 1'b0;
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
inIsZero_uid12_fxpToFPTest_delay ( .xin(inIsZero_uid12_fxpToFPTest_qi), .xout(inIsZero_uid12_fxpToFPTest_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// redist9_inIsZero_uid12_fxpToFPTest_q_2(DELAY,104)
|
||||
// redist8_inIsZero_uid12_fxpToFPTest_q_2(DELAY,103)
|
||||
dspba_delay_ver #( .width(1), .depth(1), .reset_kind("ASYNC") )
|
||||
redist9_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist9_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist8_inIsZero_uid12_fxpToFPTest_q_2 ( .xin(inIsZero_uid12_fxpToFPTest_q), .xout(redist8_inIsZero_uid12_fxpToFPTest_q_2_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// udf_uid27_fxpToFPTest(COMPARE,26)@8
|
||||
// udf_uid27_fxpToFPTest(COMPARE,26)@7
|
||||
assign udf_uid27_fxpToFPTest_a = {11'b00000000000, GND_q};
|
||||
assign udf_uid27_fxpToFPTest_b = {{2{redist6_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist6_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign udf_uid27_fxpToFPTest_b = {{2{redist5_expR_uid26_fxpToFPTest_b_1_q[9]}}, redist5_expR_uid26_fxpToFPTest_b_1_q};
|
||||
assign udf_uid27_fxpToFPTest_o = $signed(udf_uid27_fxpToFPTest_a) - $signed(udf_uid27_fxpToFPTest_b);
|
||||
assign udf_uid27_fxpToFPTest_n[0] = ~ (udf_uid27_fxpToFPTest_o[11]);
|
||||
|
||||
// udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@8
|
||||
assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist9_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
// udfOrInZero_uid33_fxpToFPTest(LOGICAL,32)@7
|
||||
assign udfOrInZero_uid33_fxpToFPTest_q = udf_uid27_fxpToFPTest_n | redist8_inIsZero_uid12_fxpToFPTest_q_2_q;
|
||||
|
||||
// excSelector_uid34_fxpToFPTest(BITJOIN,33)@8
|
||||
// excSelector_uid34_fxpToFPTest(BITJOIN,33)@7
|
||||
assign excSelector_uid34_fxpToFPTest_q = {ovf_uid29_fxpToFPTest_n, udfOrInZero_uid33_fxpToFPTest_q};
|
||||
|
||||
// expRPostExc_uid39_fxpToFPTest(MUX,38)@8
|
||||
// expRPostExc_uid39_fxpToFPTest(MUX,38)@7
|
||||
assign expRPostExc_uid39_fxpToFPTest_s = excSelector_uid34_fxpToFPTest_q;
|
||||
always @(expRPostExc_uid39_fxpToFPTest_s or en or expR_uid38_fxpToFPTest_b or expZ_uid37_fxpToFPTest_q or expInf_uid28_fxpToFPTest_q)
|
||||
begin
|
||||
|
|
@ -491,32 +489,32 @@ module acl_fp_itof (
|
|||
// fracZ_uid31_fxpToFPTest(CONSTANT,30)
|
||||
assign fracZ_uid31_fxpToFPTest_q = 23'b00000000000000000000000;
|
||||
|
||||
// fracR_uid25_fxpToFPTest(BITSELECT,24)@7
|
||||
// fracR_uid25_fxpToFPTest(BITSELECT,24)@6
|
||||
assign fracR_uid25_fxpToFPTest_in = expFracR_uid24_fxpToFPTest_q[23:0];
|
||||
assign fracR_uid25_fxpToFPTest_b = fracR_uid25_fxpToFPTest_in[23:1];
|
||||
|
||||
// redist7_fracR_uid25_fxpToFPTest_b_1(DELAY,102)
|
||||
// redist6_fracR_uid25_fxpToFPTest_b_1(DELAY,101)
|
||||
dspba_delay_ver #( .width(23), .depth(1), .reset_kind("ASYNC") )
|
||||
redist7_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist7_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
redist6_fracR_uid25_fxpToFPTest_b_1 ( .xin(fracR_uid25_fxpToFPTest_b), .xout(redist6_fracR_uid25_fxpToFPTest_b_1_q), .ena(en[0]), .clk(clk), .aclr(areset) );
|
||||
|
||||
// excSelector_uid30_fxpToFPTest(LOGICAL,29)@8
|
||||
assign excSelector_uid30_fxpToFPTest_q = redist9_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
|
||||
// excSelector_uid30_fxpToFPTest(LOGICAL,29)@7
|
||||
assign excSelector_uid30_fxpToFPTest_q = redist8_inIsZero_uid12_fxpToFPTest_q_2_q | ovf_uid29_fxpToFPTest_n | udf_uid27_fxpToFPTest_n;
|
||||
|
||||
// fracRPostExc_uid32_fxpToFPTest(MUX,31)@8
|
||||
// fracRPostExc_uid32_fxpToFPTest(MUX,31)@7
|
||||
assign fracRPostExc_uid32_fxpToFPTest_s = excSelector_uid30_fxpToFPTest_q;
|
||||
always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist7_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
|
||||
always @(fracRPostExc_uid32_fxpToFPTest_s or en or redist6_fracR_uid25_fxpToFPTest_b_1_q or fracZ_uid31_fxpToFPTest_q)
|
||||
begin
|
||||
unique case (fracRPostExc_uid32_fxpToFPTest_s)
|
||||
1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist7_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
1'b0 : fracRPostExc_uid32_fxpToFPTest_q = redist6_fracR_uid25_fxpToFPTest_b_1_q;
|
||||
1'b1 : fracRPostExc_uid32_fxpToFPTest_q = fracZ_uid31_fxpToFPTest_q;
|
||||
default : fracRPostExc_uid32_fxpToFPTest_q = 23'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
// outRes_uid40_fxpToFPTest(BITJOIN,39)@8
|
||||
assign outRes_uid40_fxpToFPTest_q = {redist12_signX_uid6_fxpToFPTest_b_8_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
|
||||
// outRes_uid40_fxpToFPTest(BITJOIN,39)@7
|
||||
assign outRes_uid40_fxpToFPTest_q = {redist11_signX_uid6_fxpToFPTest_b_7_q, expRPostExc_uid39_fxpToFPTest_q, fracRPostExc_uid32_fxpToFPTest_q};
|
||||
|
||||
// xOut(GPOUT,4)@8
|
||||
// xOut(GPOUT,4)@7
|
||||
assign q = outRes_uid40_fxpToFPTest_q;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fp_sqrt
|
||||
// SystemVerilog created on Wed Aug 5 12:58:14 2020
|
||||
// SystemVerilog created on Mon Aug 31 06:15:18 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
// ---------------------------------------------------------------------------
|
||||
|
||||
// SystemVerilog created from acl_fp_utof
|
||||
// SystemVerilog created on Wed Aug 5 12:58:16 2020
|
||||
// SystemVerilog created on Mon Aug 31 06:15:18 2020
|
||||
|
||||
|
||||
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
CMD_POLY_EVAL_PATH=$QUARTUS_HOME/dspba/backend/linux64
|
||||
|
||||
OPTIONS="-target Arria10 -lang verilog -frequency 300 -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2"
|
||||
OPTIONS="-target Arria10 -lang verilog -enableHardFP 1 -printMachineReadable -faithfulRounding -noChanValid -enable -speedgrade 2"
|
||||
|
||||
export LD_LIBRARY_PATH=$CMD_POLY_EVAL_PATH:$LD_LIBRARY_PATH
|
||||
|
||||
|
|
@ -14,12 +14,12 @@ FBITS="f$(($EXP_BITS + $MAN_BITS + 1))"
|
|||
|
||||
echo Generating IP cores for $FBITS
|
||||
{
|
||||
$CMD -name acl_fp_div FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name acl_fp_sqrt FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fp_ftoi FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name acl_fp_ftou FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name acl_fp_itof FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fp_utof FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fp_div -frequency 250 FPDiv $EXP_BITS $MAN_BITS 0
|
||||
$CMD -name acl_fp_sqrt -frequency 250 FPSqrt $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fp_ftoi -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 1
|
||||
$CMD -name acl_fp_ftou -frequency 250 FPToFXP $EXP_BITS $MAN_BITS 32 0 0
|
||||
$CMD -name acl_fp_itof -frequency 250 FXPToFP 32 0 1 $EXP_BITS $MAN_BITS
|
||||
$CMD -name acl_fp_utof -frequency 300 FXPToFP 32 0 0 $EXP_BITS $MAN_BITS
|
||||
} > log.txt 2>&1
|
||||
|
||||
cp $QUARTUS_HOME/dspba/backend/Libraries/sv/base/dspba_library_ver.sv .
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
module VX_elastic_buffer #(
|
||||
parameter DATAW = 1,
|
||||
parameter SIZE = 2,
|
||||
parameter BUFFERED = 1
|
||||
parameter BUFFERED = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
module VX_generic_queue #(
|
||||
parameter DATAW = 1,
|
||||
parameter SIZE = 2,
|
||||
parameter BUFFERED = 1,
|
||||
parameter BUFFERED = 0,
|
||||
parameter ADDRW = $clog2(SIZE),
|
||||
parameter SIZEW = $clog2(SIZE+1)
|
||||
) (
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue