minor updates

README.md

@@ -54,9 +54,9 @@ More detailed build instructions can be found [here](docs/install_vortex.md).
     $ git clone --recursive https://github.com/vortexgpgpu/vortex.git
     $ cd Vortex
 ### Install prebuilt toolchain
-    By default, the toolchain will install to /opt folder. 
-    You can install the toolchain to a different directory by overriding TOOLDIR (e.g. export TOOLDIR=$HOME/tools).
-    
+    By default, the toolchain will install to /opt folder which requires sudo access. 
+    You can install the toolchain to a different location of your choice by setting TOOLDIR (e.g. export TOOLDIR=$HOME/tools).
+    $ export TOOLDIR=/opt
     $ ./ci/toolchain_install.sh --all
     $ source ./ci/toolchain_env.sh
 ### Build Vortex sources

hw/rtl/VX_config.vh

@@ -136,6 +136,18 @@
 `endif
 `endif
 
+`ifdef L2_ENABLE
+`define L2_LINE_SIZE `MEM_BLOCK_SIZE
+`else
+`define L2_LINE_SIZE `L1_LINE_SIZE
+`endif
+
+`ifdef L3_ENABLE
+`define L3_LINE_SIZE `MEM_BLOCK_SIZE
+`else
+`define L3_LINE_SIZE `L2_LINE_SIZE
+`endif
+
 `ifdef XLEN_64
 
 `ifndef STARTUP_ADDR

hw/rtl/VX_define.vh

@@ -298,18 +298,6 @@
 `define L1_ENABLE
 `endif
 
-`ifdef L2_ENABLE
-`define L2_LINE_SIZE	        `MEM_BLOCK_SIZE
-`else
-`define L2_LINE_SIZE	        `L1_LINE_SIZE
-`endif
-
-`ifdef L3_ENABLE
-`define L3_LINE_SIZE	        `MEM_BLOCK_SIZE
-`else
-`define L3_LINE_SIZE	        `L2_LINE_SIZE
-`endif
-
 `define VX_MEM_BYTEEN_WIDTH     `L3_LINE_SIZE   
 `define VX_MEM_ADDR_WIDTH       (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE))
 `define VX_MEM_DATA_WIDTH       (`L3_LINE_SIZE * 8)

sim/simx/cluster.cpp

@@ -62,10 +62,10 @@ Cluster::Cluster(const SimContext& ctx,
   snprintf(sname, 100, "cluster%d-l2cache", cluster_id);
   l2cache_ = CacheSim::Create(sname, CacheSim::Config{
     !L2_ENABLED,
-    log2ceil(L2_CACHE_SIZE), // C
-    log2ceil(MEM_BLOCK_SIZE), // L
-    log2ceil(L2_NUM_WAYS),  // W
-    0,                      // A
+    log2ceil(L2_CACHE_SIZE),// C
+    log2ceil(MEM_BLOCK_SIZE),// L
+    log2ceil(L1_LINE_SIZE), // W
+    log2ceil(L2_NUM_WAYS),  // A
     log2ceil(L2_NUM_BANKS), // B
     XLEN,                   // address bits  
     1,                      // number of ports

sim/simx/core.cpp

@@ -210,7 +210,7 @@ void Core::schedule() {
 void Core::fetch() {
   perf_stats_.ifetch_latency += pending_ifetches_;
 
-  // handle icache reponse
+  // handle icache response
   auto& icache_rsp_port = icache_rsp_ports.at(0);
   if (!icache_rsp_port.empty()){
     auto& mem_rsp = icache_rsp_port.front();

sim/simx/execute.cpp

@@ -339,7 +339,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
         break;
       }
       case 1: {
-        // RV64I: SLLI
+        // RV32I: SLLI
         rddata[t].i = rsdata[t][0].i << immsrc;
         break;
       }
@@ -360,11 +360,11 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
       }
       case 5: {
         if (func7) {
-          // RV64I: SRAI
+          // RV32I: SRAI
           Word result = rsdata[t][0].i >> immsrc;
           rddata[t].i = result;
         } else {
-          // RV64I: SRLI
+          // RV32I: SRLI
           Word result = rsdata[t][0].u >> immsrc;
           rddata[t].i = result;
         }

sim/simx/main.cpp

@@ -34,7 +34,7 @@ static void show_usage() {
 uint32_t num_threads = NUM_THREADS;
 uint32_t num_warps = NUM_WARPS;
 uint32_t num_cores = NUM_CORES;
-bool showStats = false;;
+bool showStats = false;
 bool riscv_test = false;
 const char* program = nullptr;
 

sim/simx/processor.cpp

@@ -33,8 +33,8 @@ ProcessorImpl::ProcessorImpl(const Arch& arch)
     !L3_ENABLED,
     log2ceil(L3_CACHE_SIZE),  // C
     log2ceil(MEM_BLOCK_SIZE), // L
-    log2ceil(L3_NUM_WAYS),    // W
-    0,                        // A
+    log2ceil(L2_LINE_SIZE),   // W
+    log2ceil(L3_NUM_WAYS),    // A
     log2ceil(L3_NUM_BANKS),   // B
     XLEN,                     // address bits      
     1,                        // number of ports
@@ -58,7 +58,7 @@ ProcessorImpl::ProcessorImpl(const Arch& arch)
     l3cache_->CoreRspPorts.at(i).bind(&clusters_.at(i)->mem_rsp_port);
   }
 
-  // set up memory perf recording
+  // set up memory profiling
   memsim_->MemReqPort.tx_callback([&](const MemReq& req, uint64_t cycle){
     __unused (cycle);
     perf_mem_reads_   += !req.write;

sim/simx/socket.cpp

@@ -44,7 +44,7 @@ Socket::Socket(const SimContext& ctx,
     XLEN,                   // address bits
     1,                      // number of ports
     1,                      // number of inputs
-    true,                   // write-through
+    false,                  // write-through
     false,                  // write response
     (uint8_t)arch.num_warps(), // mshr
     2,                      // pipeline latency