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minor update

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This commit is contained in:
Blaise Tine 2021-07-16 06:44:28 -07:00
parent f54d2b6272
commit b0d8adc82b
3 changed files with 11 additions and 6 deletions
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2
ci/blackbox.sh
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@ -155,7 +155,7 @@ then
if [ -f "$APP_PATH/trace.vcd" ] if [ -f "$APP_PATH/trace.vcd" ]
then then
mv $APP_PATH/trace.vcd . mv -f $APP_PATH/trace.vcd .
fi fi
else else
if [ $SCOPE -eq 1 ] if [ $SCOPE -eq 1 ]

2
driver/opae/vx_scope.cpp
View file

@ -140,7 +140,7 @@ int vx_scope_stop(fpga_handle hfpga) {
std::cout << "scope trace dump begin..." << std::endl; std::cout << "scope trace dump begin..." << std::endl;
std::ofstream ofs("vx_scope.vcd"); std::ofstream ofs("trace.vcd");
ofs << "$version Generated by Vortex Scope $end" << std::endl; ofs << "$version Generated by Vortex Scope $end" << std::endl;
ofs << "$timescale 1 ns $end" << std::endl; ofs << "$timescale 1 ns $end" << std::endl;

13
hw/rtl/VX_csr_data.v
View file

@ -40,8 +40,6 @@ module VX_csr_data #(
reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr; reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr;
reg [31:0] read_data_r;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
@ -93,8 +91,12 @@ module VX_csr_data #(
end end
end end
reg [31:0] read_data_r;
reg read_addr_valid_r;
always @(*) begin always @(*) begin
read_data_r = 'x; read_data_r = 'x;
read_addr_valid_r = 1;
case (read_addr) case (read_addr)
`CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]); `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]);
`CSR_FRM : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]); `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]);
@ -197,16 +199,19 @@ module VX_csr_data #(
`CSR_MARCHID : read_data_r = `ARCHITECTURE_ID; `CSR_MARCHID : read_data_r = `ARCHITECTURE_ID;
`CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID; `CSR_MIMPID : read_data_r = `IMPLEMENTATION_ID;
default: begin default: begin
if (!((read_addr >= `CSR_MPM_BASE && read_addr < (`CSR_MPM_BASE + 32)) if (!((read_addr >= `CSR_MPM_BASE && read_addr < (`CSR_MPM_BASE + 32))
| (read_addr >= `CSR_MPM_BASE_H && read_addr < (`CSR_MPM_BASE_H + 32)))) begin | (read_addr >= `CSR_MPM_BASE_H && read_addr < (`CSR_MPM_BASE_H + 32)))) begin
assert(~read_enable) else $error("%t: invalid CSR read address: %0h", $time, read_addr); read_addr_valid_r = 0;
end end
end end
endcase endcase
end end
`RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("invalid CSR read address: %0h", read_addr))
assign read_data = read_data_r; assign read_data = read_data_r;
assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]; assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS];
endmodule endmodule