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minor update

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Blaise Tine 2024-03-04 22:19:52 -08:00
parent 288147ac4f
commit b0f3e91006
1 changed files with 3 additions and 1 deletions
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4
hw/rtl/cache/VX_cache_bypass.sv vendored
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@ -66,7 +66,9 @@ module VX_cache_bypass #(
localparam MEM_TAG_BYPASS_BITS = UUID_WIDTH + MEM_TAG_ID_BITS;
localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE);
localparam MEM_ADDRW = `MEM_ADDR_WIDTH - MEM_ASHIFT;
localparam MEM_ADDRW = `MEM_ADDR_WIDTH - MEM_ASHIFT;
`STATIC_ASSERT(0 == (`IO_BASE_ADDR % `MEM_BLOCK_SIZE), ("invalid parameter"))
// handle core requests ///////////////////////////////////////////////////