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https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor update
This commit is contained in:
Blaise Tine
parent
e4fdc740ba
commit
b1ae82bae5
2 changed files with 107 additions and 99 deletions
199
ci/trace_csv.py
199
ci/trace_csv.py
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@ -17,6 +17,7 @@ import sys
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import argparse
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import csv
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import re
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import inspect
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def parse_args():
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parser = argparse.ArgumentParser(description='CPU trace log to CSV format converter.')
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@ -39,24 +40,27 @@ def parse_simx(log_filename):
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with open(log_filename, 'r') as log_file:
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instr_data = None
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for lineno, line in enumerate(log_file, start=1):
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if line.startswith("DEBUG Fetch:"):
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if instr_data:
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entries.append(instr_data)
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instr_data = {}
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instr_data["lineno"] = lineno
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instr_data["PC"] = re.search(pc_pattern, line).group(1)
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instr_data["core_id"] = re.search(core_id_pattern, line).group(1)
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instr_data["warp_id"] = re.search(warp_id_pattern, line).group(1)
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instr_data["tmask"] = re.search(tmask_pattern, line).group(1)
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instr_data["uuid"] = re.search(uuid_pattern, line).group(1)
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elif line.startswith("DEBUG Instr"):
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instr_data["instr"] = re.search(instr_pattern, line).group(1)
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instr_data["opcode"] = re.search(opcode_pattern, line).group(1)
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elif line.startswith("DEBUG Src"):
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src_reg = re.search(operands_pattern, line).group(1)
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instr_data["operands"] = (instr_data["operands"] + ', ' + src_reg) if 'operands' in instr_data else src_reg
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elif line.startswith("DEBUG Dest"):
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instr_data["destination"] = re.search(destination_pattern, line).group(1)
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try:
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if line.startswith("DEBUG Fetch:"):
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if instr_data:
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entries.append(instr_data)
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instr_data = {}
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instr_data["lineno"] = lineno
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instr_data["PC"] = re.search(pc_pattern, line).group(1)
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instr_data["core_id"] = re.search(core_id_pattern, line).group(1)
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instr_data["warp_id"] = re.search(warp_id_pattern, line).group(1)
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instr_data["tmask"] = re.search(tmask_pattern, line).group(1)
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instr_data["uuid"] = re.search(uuid_pattern, line).group(1)
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elif line.startswith("DEBUG Instr"):
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instr_data["instr"] = re.search(instr_pattern, line).group(1)
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instr_data["opcode"] = re.search(opcode_pattern, line).group(1)
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elif line.startswith("DEBUG Src"):
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src_reg = re.search(operands_pattern, line).group(1)
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instr_data["operands"] = (instr_data["operands"] + ', ' + src_reg) if 'operands' in instr_data else src_reg
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elif line.startswith("DEBUG Dest"):
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instr_data["destination"] = re.search(destination_pattern, line).group(1)
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except Exception as e:
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print("Error at line {}: {}".format(lineno, e))
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if instr_data:
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entries.append(instr_data)
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return entries
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@ -115,88 +119,91 @@ def parse_rtlsim(log_filename):
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with open(log_filename, 'r') as log_file:
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instr_data = {}
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for lineno, line in enumerate(log_file, start=1):
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line_match = re.search(line_pattern, line)
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if line_match:
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PC = re.search(pc_pattern, line).group(1)
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warp_id = re.search(warp_id_pattern, line).group(1)
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tmask = re.search(tmask_pattern, line).group(1)
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uuid = re.search(uuid_pattern, line).group(1)
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core_id = line_match.group(1)
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stage = line_match.group(2)
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if stage == "decode":
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trace = {}
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trace["uuid"] = uuid
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trace["PC"] = PC
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trace["core_id"] = core_id
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trace["warp_id"] = warp_id
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trace["tmask"] = reverse_binary(tmask)
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trace["instr"] = re.search(instr_pattern, line).group(1)
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trace["opcode"] = re.search(op_pattern, line).group(1)
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trace["opds"] = bin_to_array(re.search(opds_pattern, line).group(1))
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trace["rd"] = re.search(rd_pattern, line).group(1)
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trace["rs1"] = re.search(rs1_pattern, line).group(1)
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trace["rs2"] = re.search(rs2_pattern, line).group(1)
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trace["rs3"] = re.search(rs3_pattern, line).group(1)
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instr_data[uuid] = trace
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elif stage == "issue":
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if uuid in instr_data:
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trace = instr_data[uuid]
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trace["lineno"] = lineno
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opds = trace["opds"]
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if opds[1]:
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trace["rs1_data"] = re.search(rs1_data_pattern, line).group(1).split(', ')[::-1]
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if opds[2]:
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trace["rs2_data"] = re.search(rs2_data_pattern, line).group(1).split(', ')[::-1]
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if opds[3]:
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trace["rs3_data"] = re.search(rs3_data_pattern, line).group(1).split(', ')[::-1]
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trace["issued"] = True
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try:
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line_match = re.search(line_pattern, line)
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if line_match:
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PC = re.search(pc_pattern, line).group(1)
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warp_id = re.search(warp_id_pattern, line).group(1)
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tmask = re.search(tmask_pattern, line).group(1)
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uuid = re.search(uuid_pattern, line).group(1)
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core_id = line_match.group(1)
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stage = line_match.group(2)
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if stage == "decode":
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trace = {}
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trace["uuid"] = uuid
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trace["PC"] = PC
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trace["core_id"] = core_id
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trace["warp_id"] = warp_id
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trace["tmask"] = reverse_binary(tmask)
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trace["instr"] = re.search(instr_pattern, line).group(1)
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trace["opcode"] = re.search(op_pattern, line).group(1)
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trace["opds"] = bin_to_array(re.search(opds_pattern, line).group(1))
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trace["rd"] = re.search(rd_pattern, line).group(1)
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trace["rs1"] = re.search(rs1_pattern, line).group(1)
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trace["rs2"] = re.search(rs2_pattern, line).group(1)
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trace["rs3"] = re.search(rs3_pattern, line).group(1)
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instr_data[uuid] = trace
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elif stage == "commit":
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if uuid in instr_data:
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trace = instr_data[uuid]
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if "issued" in trace:
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elif stage == "issue":
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if uuid in instr_data:
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trace = instr_data[uuid]
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trace["lineno"] = lineno
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opds = trace["opds"]
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dst_tmask_arr = bin_to_array(tmask)[::-1]
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wb = re.search(wb_pattern, line).group(1) == "1"
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if wb:
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rd_data = re.search(rd_data_pattern, line).group(1).split(', ')[::-1]
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if 'rd_data' in trace:
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merged_rd_data = trace['rd_data']
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for i in range(len(dst_tmask_arr)):
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if dst_tmask_arr[i] == 1:
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merged_rd_data[i] = rd_data[i]
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trace['rd_data'] = merged_rd_data
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else:
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trace['rd_data'] = rd_data
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if opds[1]:
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trace["rs1_data"] = re.search(rs1_data_pattern, line).group(1).split(', ')[::-1]
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if opds[2]:
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trace["rs2_data"] = re.search(rs2_data_pattern, line).group(1).split(', ')[::-1]
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if opds[3]:
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trace["rs3_data"] = re.search(rs3_data_pattern, line).group(1).split(', ')[::-1]
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trace["issued"] = True
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instr_data[uuid] = trace
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eop = re.search(eop_pattern, line).group(1) == "1"
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if eop:
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tmask_arr = bin_to_array(trace["tmask"])
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destination = ''
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elif stage == "commit":
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if uuid in instr_data:
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trace = instr_data[uuid]
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if "issued" in trace:
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opds = trace["opds"]
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dst_tmask_arr = bin_to_array(tmask)[::-1]
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wb = re.search(wb_pattern, line).group(1) == "1"
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if wb:
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destination, sep = append_value(destination, trace["rd"], trace['rd_data'], tmask_arr, False)
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del trace['rd_data']
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trace["destination"] = destination
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operands = ''
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sep = False
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if opds[1]:
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operands, sep = append_value(operands, trace["rs1"], trace["rs1_data"], tmask_arr, sep)
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del trace["rs1_data"]
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if opds[2]:
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operands, sep = append_value(operands, trace["rs2"], trace["rs2_data"], tmask_arr, sep)
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del trace["rs2_data"]
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if opds[3]:
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operands, sep = append_value(operands, trace["rs3"], trace["rs3_data"], tmask_arr, sep)
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del trace["rs3_data"]
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trace["operands"] = operands
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del trace["opds"]
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del trace["rd"]
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del trace["rs1"]
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del trace["rs2"]
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del trace["rs3"]
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del trace["issued"]
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del instr_data[uuid]
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entries.append(trace)
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rd_data = re.search(rd_data_pattern, line).group(1).split(', ')[::-1]
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if 'rd_data' in trace:
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merged_rd_data = trace['rd_data']
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for i in range(len(dst_tmask_arr)):
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if dst_tmask_arr[i] == 1:
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merged_rd_data[i] = rd_data[i]
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trace['rd_data'] = merged_rd_data
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else:
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trace['rd_data'] = rd_data
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instr_data[uuid] = trace
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eop = re.search(eop_pattern, line).group(1) == "1"
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if eop:
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tmask_arr = bin_to_array(trace["tmask"])
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destination = ''
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if wb:
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destination, sep = append_value(destination, trace["rd"], trace['rd_data'], tmask_arr, False)
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del trace['rd_data']
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trace["destination"] = destination
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operands = ''
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sep = False
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if opds[1]:
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operands, sep = append_value(operands, trace["rs1"], trace["rs1_data"], tmask_arr, sep)
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del trace["rs1_data"]
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if opds[2]:
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operands, sep = append_value(operands, trace["rs2"], trace["rs2_data"], tmask_arr, sep)
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del trace["rs2_data"]
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if opds[3]:
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operands, sep = append_value(operands, trace["rs3"], trace["rs3_data"], tmask_arr, sep)
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del trace["rs3_data"]
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trace["operands"] = operands
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del trace["opds"]
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del trace["rd"]
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del trace["rs1"]
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del trace["rs2"]
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del trace["rs3"]
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del trace["issued"]
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del instr_data[uuid]
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entries.append(trace)
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except Exception as e:
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print("Error at line {}: {}".format(lineno, e))
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return entries
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def write_csv(log_filename, csv_filename, log_type):
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@ -27,9 +27,9 @@
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endtask
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task trace_ex_op(input int level,
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input [`EX_BITS-1:0] ex_type,
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input [`INST_OP_BITS-1:0] op_type,
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input VX_gpu_pkg::op_mod_t op_mod
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input [`EX_BITS-1:0] ex_type,
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input [`INST_OP_BITS-1:0] op_type,
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input VX_gpu_pkg::op_mod_t op_mod
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);
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case (ex_type)
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`EX_ALU: begin
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@ -131,6 +131,7 @@
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endcase
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end
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end
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default: `TRACE(level, ("?"));
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endcase
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end
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`EX_LSU: begin
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