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warp scheduler optimization
This commit is contained in:
Blaise Tine
parent
5b8e58e15e
commit
b1eef0fb7c
6 changed files with 66 additions and 66 deletions
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@ -221,6 +221,7 @@ module VX_decode #(
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use_rd = 1;
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use_imm = 1;
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use_PC = 1;
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is_wstall = 1;
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imm = 32'd4;
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`USED_IREG (rd);
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end
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@ -406,8 +407,9 @@ module VX_decode #(
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assign join_if.valid = ifetch_rsp_fire && is_join;
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assign join_if.wid = ifetch_rsp_if.wid;
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assign wstall_if.valid = ifetch_rsp_fire && is_wstall;
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assign wstall_if.valid = ifetch_rsp_fire;
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assign wstall_if.wid = ifetch_rsp_if.wid;
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assign wstall_if.stalled = is_wstall;
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assign ifetch_rsp_if.ready = decode_if.ready;
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@ -44,7 +44,6 @@ module VX_fetch #(
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.branch_ctl_if (branch_ctl_if),
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.ifetch_req_if (ifetch_req_if),
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.ifetch_rsp_if (ifetch_rsp_if),
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.fetch_to_csr_if (fetch_to_csr_if),
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@ -38,7 +38,7 @@ task print_ex_op (
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`BR_MRET: $write("MRET");
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`BR_SRET: $write("SRET");
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`BR_DRET: $write("DRET");
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default: $write("?");
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default: $write("?");
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endcase
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end else if (`ALU_IS_MUL(op_mod)) begin
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case (`MUL_BITS'(op_type))
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@ -13,7 +13,6 @@ module VX_warp_sched #(
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VX_join_if join_if,
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VX_branch_ctl_if branch_ctl_if,
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VX_ifetch_rsp_if ifetch_rsp_if,
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VX_ifetch_req_if ifetch_req_if,
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VX_fetch_to_csr_if fetch_to_csr_if,
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@ -30,26 +29,25 @@ module VX_warp_sched #(
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reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // real active warps (updated when a warp is activated or disabled)
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reg [`NUM_WARPS-1:0] stalled_warps; // asserted when a branch/gpgpu instructions are issued
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// Lock warp until instruction decode to resolve branches
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reg [`NUM_WARPS-1:0] fetch_lock;
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reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks;
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reg [`NUM_WARPS-1:0][31:0] warp_pcs, warp_next_pcs;
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// barriers
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reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_stall_mask; // warps waiting on barrier
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reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks; // warps waiting on barrier
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wire reached_barrier_limit; // the expected number of warps reached the barrier
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// wspawn
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reg [31:0] use_wspawn_pc;
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reg [31:0] wspawn_pc;
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reg [`NUM_WARPS-1:0] use_wspawn;
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wire [`NW_BITS-1:0] schedule_warp;
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wire [`NW_BITS-1:0] schedule_wid;
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wire [`NUM_THREADS-1:0] schedule_tmask;
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wire [31:0] schedule_pc;
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wire schedule_valid;
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wire warp_scheduled;
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wire ifetch_req_fire = ifetch_req_if.valid && ifetch_req_if.ready;
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wire ifetch_rsp_fire = ifetch_rsp_if.valid && ifetch_rsp_if.ready;
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wire tmc_active = (warp_ctl_if.tmc.tmask != 0);
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always @(*) begin
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@ -64,55 +62,44 @@ module VX_warp_sched #(
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always @(posedge clk) begin
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if (reset) begin
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for (integer i = 0; i < `NUM_BARRIERS; i++) begin
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barrier_stall_mask[i] <= 0;
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end
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barrier_masks <= 0;
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use_wspawn <= 0;
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stalled_warps <= 0;
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warp_pcs <= '0;
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active_warps <= '0;
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thread_masks <= '0;
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use_wspawn_pc <= 0;
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use_wspawn <= 0;
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warp_pcs[0] <= `STARTUP_ADDR;
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active_warps[0] <= 1; // Activating first warp
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thread_masks[0] <= 1; // Activating first thread in first warp
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stalled_warps <= 0;
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fetch_lock <= 0;
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for (integer i = 1; i < `NUM_WARPS; i++) begin
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warp_pcs[i] <= 0;
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active_warps[i] <= 0;
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thread_masks[i] <= 0;
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end
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// activate first warp
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warp_pcs[0] <= `STARTUP_ADDR;
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active_warps[0] <= '1;
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thread_masks[0] <= '1;
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end else begin
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if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin
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use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1));
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use_wspawn_pc <= warp_ctl_if.wspawn.pc;
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use_wspawn <= warp_ctl_if.wspawn.wmask & (~`NUM_WARPS'(1));
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wspawn_pc <= warp_ctl_if.wspawn.pc;
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end
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if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin
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stalled_warps[warp_ctl_if.wid] <= 0;
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if (reached_barrier_limit) begin
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barrier_stall_mask[warp_ctl_if.barrier.id] <= 0;
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barrier_masks[warp_ctl_if.barrier.id] <= 0;
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end else begin
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barrier_stall_mask[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1;
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barrier_masks[warp_ctl_if.barrier.id][warp_ctl_if.wid] <= 1;
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end
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end else if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin
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end
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if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin
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thread_masks[warp_ctl_if.wid] <= warp_ctl_if.tmc.tmask;
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stalled_warps[warp_ctl_if.wid] <= 0;
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end else if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin
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end
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if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin
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stalled_warps[warp_ctl_if.wid] <= 0;
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if (warp_ctl_if.split.diverged) begin
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thread_masks[warp_ctl_if.wid] <= warp_ctl_if.split.then_tmask;
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end
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end
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if (use_wspawn[schedule_warp] && warp_scheduled) begin
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use_wspawn[schedule_warp] <= 0;
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thread_masks[schedule_warp] <= 1;
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end
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// Stalling the scheduling of warps
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if (wstall_if.valid) begin
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stalled_warps[wstall_if.wid] <= 1;
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end
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// Branch
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if (branch_ctl_if.valid) begin
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@ -122,18 +109,24 @@ module VX_warp_sched #(
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stalled_warps[branch_ctl_if.wid] <= 0;
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end
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// Lock warp until instruction decode to resolve branches
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if (warp_scheduled) begin
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fetch_lock[schedule_warp] <= 1;
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// stall the warp until decode stage
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stalled_warps[schedule_wid] <= 1;
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// release wspawn
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use_wspawn[schedule_wid] <= 0;
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if (use_wspawn[schedule_wid]) begin
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thread_masks[schedule_wid] <= 1;
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end
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end
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if (ifetch_req_fire) begin
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warp_next_pcs[ifetch_req_if.wid] <= ifetch_req_if.PC + 4;
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end
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if (ifetch_rsp_fire) begin
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fetch_lock[ifetch_rsp_if.wid] <= 0;
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warp_pcs[ifetch_rsp_if.wid] <= warp_next_pcs[ifetch_rsp_if.wid];
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if (wstall_if.valid) begin
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stalled_warps[wstall_if.wid] <= wstall_if.stalled;
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warp_pcs[wstall_if.wid] <= warp_next_pcs[wstall_if.wid];
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end
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// join handling
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@ -156,15 +149,15 @@ module VX_warp_sched #(
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`IGNORE_UNUSED_BEGIN
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wire [`NW_BITS:0] active_barrier_count;
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`IGNORE_UNUSED_END
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assign active_barrier_count = $countones(barrier_stall_mask[warp_ctl_if.barrier.id]);
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assign active_barrier_count = $countones(barrier_masks[warp_ctl_if.barrier.id]);
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assign reached_barrier_limit = (active_barrier_count[`NW_BITS-1:0] == warp_ctl_if.barrier.size_m1);
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reg [`NUM_WARPS-1:0] total_barrier_stall;
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reg [`NUM_WARPS-1:0] barrier_stalls;
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always @(*) begin
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total_barrier_stall = barrier_stall_mask[0];
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barrier_stalls = barrier_masks[0];
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for (integer i = 1; i < `NUM_BARRIERS; ++i) begin
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total_barrier_stall |= barrier_stall_mask[i];
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barrier_stalls |= barrier_masks[i];
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end
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end
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@ -205,22 +198,27 @@ module VX_warp_sched #(
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// round-robin warp scheduling
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wire schedule_valid;
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wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~(stalled_warps | barrier_stalls);
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VX_rr_arbiter #(
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.NUM_REQS (`NUM_WARPS)
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) rr_arbiter (
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.clk (clk),
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.reset (reset),
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.requests (active_warps & ~(stalled_warps | total_barrier_stall | fetch_lock)),
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.grant_index (schedule_warp),
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.requests (ready_warps),
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.grant_index (schedule_wid),
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.grant_valid (schedule_valid),
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`UNUSED_PIN (grant_onehot),
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`UNUSED_PIN (enable)
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);
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wire [`NUM_THREADS-1:0] thread_mask = use_wspawn[schedule_warp] ? `NUM_THREADS'(1) : thread_masks[schedule_warp];
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wire [31:0] warp_pc = use_wspawn[schedule_warp] ? use_wspawn_pc : warp_pcs[schedule_warp];
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wire [`NUM_WARPS-1:0][(`NUM_THREADS + 32)-1:0] schedule_data;
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for (genvar i = 0; i < `NUM_WARPS; ++i) begin
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assign schedule_data[i] = {(use_wspawn[i] ? `NUM_THREADS'(1) : thread_masks[i]),
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(use_wspawn[i] ? wspawn_pc : warp_pcs[i])};
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end
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assign {schedule_tmask, schedule_pc} = schedule_data[schedule_wid];
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wire stall_out = ~ifetch_req_if.ready && ifetch_req_if.valid;
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@ -233,17 +231,17 @@ module VX_warp_sched #(
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.clk (clk),
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.reset (reset),
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.enable (!stall_out),
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.data_in ({schedule_valid, thread_mask, warp_pc, schedule_warp}),
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.data_in ({schedule_valid, schedule_tmask, schedule_pc, schedule_wid}),
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.data_out ({ifetch_req_if.valid, ifetch_req_if.tmask, ifetch_req_if.PC, ifetch_req_if.wid})
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);
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assign busy = (active_warps != 0);
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`SCOPE_ASSIGN (wsched_scheduled_warp, warp_scheduled);
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`SCOPE_ASSIGN (wsched_scheduled, warp_scheduled);
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`SCOPE_ASSIGN (wsched_active_warps, active_warps);
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`SCOPE_ASSIGN (wsched_schedule_table, schedule_table);
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`SCOPE_ASSIGN (wsched_schedule_ready, schedule_ready);
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`SCOPE_ASSIGN (wsched_warp_to_schedule, schedule_warp);
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`SCOPE_ASSIGN (wsched_warp_pc, warp_pc);
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`SCOPE_ASSIGN (wsched_stalled_warps, stalled_warps);
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`SCOPE_ASSIGN (wsched_schedule_wid, schedule_wid);
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`SCOPE_ASSIGN (wsched_schedule_tmask, schedule_tmask);
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`SCOPE_ASSIGN (wsched_schedule_pc, schedule_pc);
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endmodule
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@ -7,6 +7,7 @@ interface VX_wstall_if();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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wire stalled;
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endinterface
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@ -140,9 +140,9 @@
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"afu/vortex/cluster/core/pipeline/fetch/warp_sched": {
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"?wsched_scheduled_warp": 1,
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"wsched_active_warps": "`NUM_WARPS",
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"wsched_schedule_table": "`NUM_WARPS",
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"wsched_schedule_ready": "`NUM_WARPS",
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"wsched_warp_to_schedule": "`NW_BITS",
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"wsched_stalled_warps": "`NUM_WARPS",
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"wsched_schedule_tmask": "`NUM_THREADS",
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"wsched_schedule_wid": "`NW_BITS",
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"wsched_warp_pc": "32"
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},
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"afu/vortex/cluster/core/pipeline/execute/gpu_unit": {
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