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data/dram bus refactoring

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This commit is contained in:
Blaise Tine 2020-12-06 03:37:22 -08:00
parent d0f2a3984d
commit b2652527bb
9 changed files with 624 additions and 573 deletions
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372
hw/rtl/VX_cluster.v
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@ -68,31 +68,18 @@ module VX_cluster #(
output wire busy,
output wire ebreak
);
wire [`NUM_CORES-1:0] per_core_D_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_D_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_D_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_D_dram_req_addr;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_req_data;
wire [`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_D_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] per_core_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_dram_req_addr;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_req_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_D_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_D_dram_rsp_data;
wire [`NUM_CORES-1:0][`DDRAM_TAG_WIDTH-1:0] per_core_D_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_D_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_I_dram_req_valid;
wire [`NUM_CORES-1:0] per_core_I_dram_req_rw;
wire [`NUM_CORES-1:0][`IDRAM_BYTEEN_WIDTH-1:0] per_core_I_dram_req_byteen;
wire [`NUM_CORES-1:0][`IDRAM_ADDR_WIDTH-1:0] per_core_I_dram_req_addr;
wire [`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_req_data;
wire [`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_req_tag;
wire [`NUM_CORES-1:0] per_core_I_dram_req_ready;
wire [`NUM_CORES-1:0] per_core_I_dram_rsp_valid;
wire [`NUM_CORES-1:0][`IDRAM_LINE_WIDTH-1:0] per_core_I_dram_rsp_data;
wire [`NUM_CORES-1:0][`IDRAM_TAG_WIDTH-1:0] per_core_I_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_I_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] per_core_dram_rsp_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] per_core_dram_rsp_tag;
wire [`NUM_CORES-1:0] per_core_dram_rsp_ready;
wire [`NUM_CORES-1:0] per_core_snp_req_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] per_core_snp_req_addr;
@ -139,69 +126,58 @@ module VX_cluster #(
.clk (clk),
.reset (reset),
.D_dram_req_valid (per_core_D_dram_req_valid [i]),
.D_dram_req_rw (per_core_D_dram_req_rw [i]),
.D_dram_req_byteen (per_core_D_dram_req_byteen [i]),
.D_dram_req_addr (per_core_D_dram_req_addr [i]),
.D_dram_req_data (per_core_D_dram_req_data [i]),
.D_dram_req_tag (per_core_D_dram_req_tag [i]),
.D_dram_req_ready (per_core_D_dram_req_ready [i]),
.D_dram_rsp_valid (per_core_D_dram_rsp_valid [i]),
.D_dram_rsp_data (per_core_D_dram_rsp_data [i]),
.D_dram_rsp_tag (per_core_D_dram_rsp_tag [i]),
.D_dram_rsp_ready (per_core_D_dram_rsp_ready [i]),
.dram_req_valid (per_core_dram_req_valid [i]),
.dram_req_rw (per_core_dram_req_rw [i]),
.dram_req_byteen (per_core_dram_req_byteen [i]),
.dram_req_addr (per_core_dram_req_addr [i]),
.dram_req_data (per_core_dram_req_data [i]),
.dram_req_tag (per_core_dram_req_tag [i]),
.dram_req_ready (per_core_dram_req_ready [i]),
.dram_rsp_valid (per_core_dram_rsp_valid [i]),
.dram_rsp_data (per_core_dram_rsp_data [i]),
.dram_rsp_tag (per_core_dram_rsp_tag [i]),
.dram_rsp_ready (per_core_dram_rsp_ready [i]),
.I_dram_req_valid (per_core_I_dram_req_valid [i]),
.I_dram_req_rw (per_core_I_dram_req_rw [i]),
.I_dram_req_byteen (per_core_I_dram_req_byteen [i]),
.I_dram_req_addr (per_core_I_dram_req_addr [i]),
.I_dram_req_data (per_core_I_dram_req_data [i]),
.I_dram_req_tag (per_core_I_dram_req_tag [i]),
.I_dram_req_ready (per_core_I_dram_req_ready [i]),
.I_dram_rsp_valid (per_core_I_dram_rsp_valid [i]),
.I_dram_rsp_tag (per_core_I_dram_rsp_tag [i]),
.I_dram_rsp_data (per_core_I_dram_rsp_data [i]),
.I_dram_rsp_ready (per_core_I_dram_rsp_ready [i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.snp_req_valid (per_core_snp_req_valid [i]),
.snp_req_addr (per_core_snp_req_addr [i]),
.snp_req_inv (per_core_snp_req_inv [i]),
.snp_req_tag (per_core_snp_req_tag [i]),
.snp_req_ready (per_core_snp_req_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.snp_rsp_valid (per_core_snp_rsp_valid [i]),
.snp_rsp_tag (per_core_snp_rsp_tag [i]),
.snp_rsp_ready (per_core_snp_rsp_ready [i]),
.io_req_valid (per_core_io_req_valid [i]),
.io_req_rw (per_core_io_req_rw [i]),
.io_req_byteen (per_core_io_req_byteen [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_tag (per_core_io_req_tag [i]),
.io_req_ready (per_core_io_req_ready [i]),
.io_req_valid (per_core_io_req_valid [i]),
.io_req_rw (per_core_io_req_rw [i]),
.io_req_byteen (per_core_io_req_byteen [i]),
.io_req_addr (per_core_io_req_addr [i]),
.io_req_data (per_core_io_req_data [i]),
.io_req_tag (per_core_io_req_tag [i]),
.io_req_ready (per_core_io_req_ready [i]),
.io_rsp_valid (per_core_io_rsp_valid [i]),
.io_rsp_data (per_core_io_rsp_data [i]),
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.io_rsp_valid (per_core_io_rsp_valid [i]),
.io_rsp_data (per_core_io_rsp_data [i]),
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.csr_io_req_valid (per_core_csr_io_req_valid[i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready[i]),
.csr_io_req_valid (per_core_csr_io_req_valid [i]),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready [i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready[i]),
.csr_io_rsp_valid (per_core_csr_io_rsp_valid [i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready [i]),
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
);
end
VX_io_arb #(
VX_databus_arb #(
.NUM_REQS (`NUM_CORES),
.WORD_SIZE (4),
.TAG_IN_WIDTH (`DCORE_TAG_WIDTH),
@ -283,102 +259,76 @@ module VX_cluster #(
// L2 Cache ///////////////////////////////////////////////////////////
wire[`L2NUM_REQUESTS-1:0] core_dram_req_valid;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire core_dram_req_ready;
wire [`NUM_CORES-1:0] core_dram_req_valid;
wire [`NUM_CORES-1:0] core_dram_req_rw;
wire [`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire core_dram_req_ready;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_valid;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire core_dram_rsp_ready;
wire [`NUM_CORES-1:0] core_dram_rsp_valid;
wire [`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire [`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire [`NUM_CORES-1:0] core_snp_fwdout_valid;
wire [`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire [`NUM_CORES-1:0] core_snp_fwdout_inv;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire [`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
wire [`NUM_CORES-1:0] core_snp_fwdin_valid;
wire [`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire [`NUM_CORES-1:0] core_snp_fwdin_ready;
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
wire snp_fwd_rsp_valid;
wire [`L2DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L2SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
reg [`L2NUM_REQUESTS-1:0] core_dram_rsp_ready_other;
reg core_dram_rsp_ready_all;
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign core_dram_req_valid [i] = per_core_dram_req_valid [i];
assign core_dram_req_rw [i] = per_core_dram_req_rw [i];
assign core_dram_req_byteen [i] = per_core_dram_req_byteen [i];
assign core_dram_req_addr [i] = per_core_dram_req_addr [i];
assign core_dram_req_data [i] = per_core_dram_req_data [i];
assign core_dram_req_tag [i] = per_core_dram_req_tag [i];
assign per_core_dram_req_ready [i] = core_dram_req_ready;
end
reg [`NUM_CORES-1:0] core_dram_rsp_ready_other;
always @(*) begin
core_dram_rsp_ready_other = {`L2NUM_REQUESTS{1'b1}};
core_dram_rsp_ready_all = 1'b1;
for (integer i = 0; i < `L2NUM_REQUESTS; i++) begin
for (integer j = 0; j < `L2NUM_REQUESTS; j++) begin
core_dram_rsp_ready_other = {`NUM_CORES{1'b1}};
for (integer i = 0; i < `NUM_CORES; i++) begin
for (integer j = 0; j < `NUM_CORES; j++) begin
if (i != j) begin
if (0 == (j & 1))
core_dram_rsp_ready_other[i] &= (per_core_D_dram_rsp_ready [(j/2)] | !core_dram_rsp_valid [j]);
else
core_dram_rsp_ready_other[i] &= (per_core_I_dram_rsp_ready [(j/2)] | !core_dram_rsp_valid [j]);
core_dram_rsp_ready_other[i] &= (per_core_dram_rsp_ready [j] | !core_dram_rsp_valid [j]);
end
end
if (0 == (i & 1))
core_dram_rsp_ready_all &= (per_core_D_dram_rsp_ready [(i/2)] | !core_dram_rsp_valid [i]);
else
core_dram_rsp_ready_all &= (per_core_I_dram_rsp_ready [(i/2)] | !core_dram_rsp_valid [i]);
end
end
for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign core_dram_req_valid [i] = per_core_D_dram_req_valid [(i/2)];
assign core_dram_req_valid [i+1] = per_core_I_dram_req_valid [(i/2)];
assign core_dram_req_rw [i] = per_core_D_dram_req_rw [(i/2)];
assign core_dram_req_rw [i+1] = per_core_I_dram_req_rw [(i/2)];
assign core_dram_req_byteen [i] = per_core_D_dram_req_byteen [(i/2)];
assign core_dram_req_byteen [i+1] = per_core_I_dram_req_byteen [(i/2)];
assign core_dram_req_addr [i] = per_core_D_dram_req_addr [(i/2)];
assign core_dram_req_addr [i+1] = per_core_I_dram_req_addr [(i/2)];
assign core_dram_req_data [i] = per_core_D_dram_req_data [(i/2)];
assign core_dram_req_data [i+1] = per_core_I_dram_req_data [(i/2)];
assign core_dram_req_tag [i] = per_core_D_dram_req_tag [(i/2)];
assign core_dram_req_tag [i+1] = per_core_I_dram_req_tag [(i/2)];
assign per_core_D_dram_req_ready [(i/2)] = core_dram_req_ready;
assign per_core_I_dram_req_ready [(i/2)] = core_dram_req_ready;
assign per_core_D_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i] & core_dram_rsp_ready_other [i];
assign per_core_I_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i+1] & core_dram_rsp_ready_other [i+1];
assign per_core_D_dram_rsp_data [(i/2)] = core_dram_rsp_data[i];
assign per_core_I_dram_rsp_data [(i/2)] = core_dram_rsp_data[i+1];
assign per_core_D_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i];
assign per_core_I_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i+1];
assign per_core_snp_req_valid [(i/2)] = core_snp_fwdout_valid [(i/2)];
assign per_core_snp_req_addr [(i/2)] = core_snp_fwdout_addr [(i/2)];
assign per_core_snp_req_inv [(i/2)] = core_snp_fwdout_inv [(i/2)];
assign per_core_snp_req_tag [(i/2)] = core_snp_fwdout_tag [(i/2)];
assign core_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
assign core_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
assign core_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
assign per_core_snp_rsp_ready [(i/2)] = core_snp_fwdin_ready [(i/2)];
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_dram_rsp_valid [i] = core_dram_rsp_valid[i] & core_dram_rsp_ready_other [i];
assign per_core_dram_rsp_data [i] = core_dram_rsp_data[i];
assign per_core_dram_rsp_tag [i] = core_dram_rsp_tag[i];
end
assign core_dram_rsp_ready = & (per_core_dram_rsp_ready | ~core_dram_rsp_valid);
assign core_dram_rsp_ready = core_dram_rsp_ready_all;
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign per_core_snp_req_valid [i] = core_snp_fwdout_valid [i];
assign per_core_snp_req_addr [i] = core_snp_fwdout_addr [i];
assign per_core_snp_req_inv [i] = core_snp_fwdout_inv [i];
assign per_core_snp_req_tag [i] = core_snp_fwdout_tag [i];
assign core_snp_fwdout_ready [i] = per_core_snp_req_ready[i];
assign core_snp_fwdin_valid [i] = per_core_snp_rsp_valid [i];
assign core_snp_fwdin_tag [i] = per_core_snp_rsp_tag [i];
assign per_core_snp_rsp_ready [i] = core_snp_fwdin_ready [i];
end
VX_snp_forwarder #(
.CACHE_ID (`L2CACHE_ID),
@ -420,7 +370,7 @@ module VX_cluster #(
.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
.NUM_BANKS (`L2NUM_BANKS),
.WORD_SIZE (`L2WORD_SIZE),
.NUM_REQS (`L2NUM_REQUESTS),
.NUM_REQS (`NUM_CORES),
.CREQ_SIZE (`L2CREQ_SIZE),
.MSHR_SIZE (`L2MSHR_SIZE),
.DRFQ_SIZE (`L2DRFQ_SIZE),
@ -431,7 +381,7 @@ module VX_cluster #(
.DRAM_ENABLE (1),
.FLUSH_ENABLE (1),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.CORE_TAG_WIDTH (`XDRAM_TAG_WIDTH),
.CORE_TAG_ID_BITS (0),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH),
.SNP_TAG_WIDTH (`L2SNP_TAG_WIDTH)
@ -489,72 +439,52 @@ module VX_cluster #(
end else begin
wire[`L2NUM_REQUESTS-1:0] core_dram_req_valid;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_rw;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire[`L2NUM_REQUESTS-1:0] core_dram_req_ready;
wire[`NUM_CORES-1:0] core_dram_req_valid;
wire[`NUM_CORES-1:0] core_dram_req_rw;
wire[`NUM_CORES-1:0][`DDRAM_BYTEEN_WIDTH-1:0] core_dram_req_byteen;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_dram_req_addr;
wire[`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_req_tag;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_req_data;
wire[`NUM_CORES-1:0] core_dram_req_ready;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_valid;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`L2NUM_REQUESTS-1:0][`DDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire[`L2NUM_REQUESTS-1:0] core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_dram_rsp_valid;
wire[`NUM_CORES-1:0][`DDRAM_LINE_WIDTH-1:0] core_dram_rsp_data;
wire[`NUM_CORES-1:0][`XDRAM_TAG_WIDTH-1:0] core_dram_rsp_tag;
wire[`NUM_CORES-1:0] core_dram_rsp_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdout_valid;
wire[`NUM_CORES-1:0][`DDRAM_ADDR_WIDTH-1:0] core_snp_fwdout_addr;
wire[`NUM_CORES-1:0] core_snp_fwdout_inv;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdout_tag;
wire[`NUM_CORES-1:0] core_snp_fwdout_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
wire[`NUM_CORES-1:0] core_snp_fwdin_valid;
wire[`NUM_CORES-1:0][`DSNP_TAG_WIDTH-1:0] core_snp_fwdin_tag;
wire[`NUM_CORES-1:0] core_snp_fwdin_ready;
for (genvar i = 0; i < `L2NUM_REQUESTS; i = i + 2) begin
assign core_dram_req_valid [i] = per_core_D_dram_req_valid[(i/2)];
assign core_dram_req_valid [i+1] = per_core_I_dram_req_valid[(i/2)];
for (genvar i = 0; i < `NUM_CORES; i++) begin
assign core_dram_req_valid [i] = per_core_dram_req_valid [i];
assign core_dram_req_rw [i] = per_core_dram_req_rw [i];
assign core_dram_req_byteen [i] = per_core_dram_req_byteen [i];
assign core_dram_req_addr [i] = per_core_dram_req_addr [i];
assign core_dram_req_data [i] = per_core_dram_req_data [i];
assign core_dram_req_tag [i] = per_core_dram_req_tag [i];
assign per_core_dram_req_ready [i] = core_dram_req_ready [i];
assign core_dram_req_rw [i] = per_core_D_dram_req_rw[(i/2)];
assign core_dram_req_rw [i+1] = per_core_I_dram_req_rw[(i/2)];
assign per_core_dram_rsp_valid [i] = core_dram_rsp_valid [i];
assign per_core_dram_rsp_data [i] = core_dram_rsp_data [i];
assign per_core_dram_rsp_tag [i] = core_dram_rsp_tag [i];
assign core_dram_rsp_ready [i] = per_core_dram_rsp_ready [i];
assign core_dram_req_byteen[i] = per_core_D_dram_req_byteen[(i/2)];
assign core_dram_req_byteen[i+1] = per_core_I_dram_req_byteen[(i/2)];
assign per_core_snp_req_valid [i] = core_snp_fwdout_valid [i];
assign per_core_snp_req_addr [i] = core_snp_fwdout_addr [i];
assign per_core_snp_req_inv [i] = core_snp_fwdout_inv [i];
assign per_core_snp_req_tag [i] = core_snp_fwdout_tag [i];
assign core_snp_fwdout_ready [i] = per_core_snp_req_ready [i];
assign core_dram_req_addr [i] = per_core_D_dram_req_addr[(i/2)];
assign core_dram_req_addr [i+1] = per_core_I_dram_req_addr[(i/2)];
assign core_dram_req_data [i] = per_core_D_dram_req_data[(i/2)];
assign core_dram_req_data [i+1] = per_core_I_dram_req_data[(i/2)];
assign core_dram_req_tag [i] = per_core_D_dram_req_tag[(i/2)];
assign core_dram_req_tag [i+1] = per_core_I_dram_req_tag[(i/2)];
assign per_core_D_dram_req_ready [(i/2)] = core_dram_req_ready[i];
assign per_core_I_dram_req_ready [(i/2)] = core_dram_req_ready[i+1];
assign per_core_D_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i];
assign per_core_I_dram_rsp_valid [(i/2)] = core_dram_rsp_valid[i+1];
assign per_core_D_dram_rsp_data [(i/2)] = core_dram_rsp_data[i];
assign per_core_I_dram_rsp_data [(i/2)] = core_dram_rsp_data[i+1];
assign per_core_D_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i];
assign per_core_I_dram_rsp_tag [(i/2)] = core_dram_rsp_tag[i+1];
assign core_dram_rsp_ready [i] = per_core_D_dram_rsp_ready[(i/2)];
assign core_dram_rsp_ready [i+1] = per_core_I_dram_rsp_ready[(i/2)];
assign per_core_snp_req_valid [(i/2)] = core_snp_fwdout_valid [(i/2)];
assign per_core_snp_req_addr [(i/2)] = core_snp_fwdout_addr [(i/2)];
assign per_core_snp_req_inv [(i/2)] = core_snp_fwdout_inv [(i/2)];
assign per_core_snp_req_tag [(i/2)] = core_snp_fwdout_tag [(i/2)];
assign core_snp_fwdout_ready [(i/2)] = per_core_snp_req_ready[(i/2)];
assign core_snp_fwdin_valid [(i/2)] = per_core_snp_rsp_valid [(i/2)];
assign core_snp_fwdin_tag [(i/2)] = per_core_snp_rsp_tag [(i/2)];
assign per_core_snp_rsp_ready [(i/2)] = core_snp_fwdin_ready [(i/2)];
assign core_snp_fwdin_valid [i] = per_core_snp_rsp_valid [i];
assign core_snp_fwdin_tag [i] = per_core_snp_rsp_tag [i];
assign per_core_snp_rsp_ready [i] = core_snp_fwdin_ready [i];
end
if (`NUM_CORES > 1) begin
@ -604,9 +534,9 @@ module VX_cluster #(
end
VX_mem_arb #(
.NUM_REQS (`L2NUM_REQUESTS),
.NUM_REQS (`NUM_CORES),
.DATA_WIDTH (`L2DRAM_LINE_WIDTH),
.TAG_IN_WIDTH (`DDRAM_TAG_WIDTH),
.TAG_IN_WIDTH (`XDRAM_TAG_WIDTH),
.TAG_OUT_WIDTH (`L2DRAM_TAG_WIDTH)
) dram_arb (
.clk (clk),

6
hw/rtl/VX_config.vh
View file

@ -267,8 +267,8 @@
// SM Configurable Knobs //////////////////////////////////////////////////////
// Size of cache in bytes
`ifndef SCACHE_SIZE
`define SCACHE_SIZE 4096
`ifndef SMEM_SIZE
`define SMEM_SIZE 4096
`endif
// Number of banks
@ -295,7 +295,7 @@
// Number of banks
`ifndef L2NUM_BANKS
`define L2NUM_BANKS `MIN((`NUM_CORES * 2), 4)
`define L2NUM_BANKS `MIN(`NUM_CORES, 4)
`endif
// Core Request Queue Size

215
hw/rtl/VX_core.v
View file

@ -9,35 +9,20 @@ module VX_core #(
input wire clk,
input wire reset,
// DRAM Dcache request
output wire D_dram_req_valid,
output wire D_dram_req_rw,
output wire [`DDRAM_BYTEEN_WIDTH-1:0] D_dram_req_byteen,
output wire [`DDRAM_ADDR_WIDTH-1:0] D_dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] D_dram_req_data,
output wire [`DDRAM_TAG_WIDTH-1:0] D_dram_req_tag,
input wire D_dram_req_ready,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [`DDRAM_BYTEEN_WIDTH-1:0] dram_req_byteen,
output wire [`DDRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`DDRAM_LINE_WIDTH-1:0] dram_req_data,
output wire [`XDRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM Dcache reponse
input wire D_dram_rsp_valid,
input wire [`DDRAM_LINE_WIDTH-1:0] D_dram_rsp_data,
input wire [`DDRAM_TAG_WIDTH-1:0] D_dram_rsp_tag,
output wire D_dram_rsp_ready,
// DRAM Icache request
output wire I_dram_req_valid,
output wire I_dram_req_rw,
output wire [`IDRAM_BYTEEN_WIDTH-1:0] I_dram_req_byteen,
output wire [`IDRAM_ADDR_WIDTH-1:0] I_dram_req_addr,
output wire [`IDRAM_LINE_WIDTH-1:0] I_dram_req_data,
output wire [`IDRAM_TAG_WIDTH-1:0] I_dram_req_tag,
input wire I_dram_req_ready,
// DRAM Icache response
input wire I_dram_rsp_valid,
input wire [`IDRAM_LINE_WIDTH-1:0] I_dram_rsp_data,
input wire [`IDRAM_TAG_WIDTH-1:0] I_dram_rsp_tag,
output wire I_dram_rsp_ready,
// DRAM reponse
input wire dram_rsp_valid,
input wire [`DDRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire [`XDRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready,
// Snoop request
input wire snp_req_valid,
@ -84,79 +69,92 @@ module VX_core #(
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_req_if();
.DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH)
) dram_req_if();
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if();
.DRAM_TAG_WIDTH(`XDRAM_TAG_WIDTH)
) dram_rsp_if();
assign D_dram_req_valid = dcache_dram_req_if.valid;
assign D_dram_req_rw = dcache_dram_req_if.rw;
assign D_dram_req_byteen= dcache_dram_req_if.byteen;
assign D_dram_req_addr = dcache_dram_req_if.addr;
assign D_dram_req_data = dcache_dram_req_if.data;
assign D_dram_req_tag = dcache_dram_req_if.tag;
assign dcache_dram_req_if.ready = D_dram_req_ready;
assign dram_req_valid = dram_req_if.valid;
assign dram_req_rw = dram_req_if.rw;
assign dram_req_byteen= dram_req_if.byteen;
assign dram_req_addr = dram_req_if.addr;
assign dram_req_data = dram_req_if.data;
assign dram_req_tag = dram_req_if.tag;
assign dram_req_if.ready = dram_req_ready;
assign dcache_dram_rsp_if.valid = D_dram_rsp_valid;
assign dcache_dram_rsp_if.data = D_dram_rsp_data;
assign dcache_dram_rsp_if.tag = D_dram_rsp_tag;
assign D_dram_rsp_ready = dcache_dram_rsp_if.ready;
assign dram_rsp_if.valid = dram_rsp_valid;
assign dram_rsp_if.data = dram_rsp_data;
assign dram_rsp_if.tag = dram_rsp_tag;
assign dram_rsp_ready = dram_rsp_if.ready;
//--
VX_cache_snp_req_if #(
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_req_if();
VX_cache_snp_rsp_if #(
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_rsp_if();
assign dcache_snp_req_if.valid = snp_req_valid;
assign dcache_snp_req_if.addr = snp_req_addr;
assign dcache_snp_req_if.invalidate = snp_req_inv;
assign dcache_snp_req_if.tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.ready;
assign snp_rsp_valid = dcache_snp_rsp_if.valid;
assign snp_rsp_tag = dcache_snp_rsp_if.tag;
assign dcache_snp_rsp_if.ready = snp_rsp_ready;
//--
VX_cache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_req_if(),arb_dcache_req_if(), arb_io_req_if();
) io_req_if();
VX_cache_core_rsp_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if();
) io_rsp_if();
assign io_req_valid = arb_io_req_if.valid;
assign io_req_rw = arb_io_req_if.rw;
assign io_req_byteen = arb_io_req_if.byteen;
assign io_req_addr = arb_io_req_if.addr;
assign io_req_data = arb_io_req_if.data;
assign io_req_tag = arb_io_req_if.tag;
assign arb_io_req_if.ready = io_req_ready;
assign io_req_valid = io_req_if.valid;
assign io_req_rw = io_req_if.rw;
assign io_req_byteen = io_req_if.byteen;
assign io_req_addr = io_req_if.addr;
assign io_req_data = io_req_if.data;
assign io_req_tag = io_req_if.tag;
assign io_req_if.ready = io_req_ready;
assign arb_io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign arb_io_rsp_if.data[0] = io_rsp_data;
assign arb_io_rsp_if.tag = io_rsp_tag;
assign io_rsp_ready = arb_io_rsp_if.ready;
// Icache interfaces
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH(`IDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_req_if();
assign io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid};
assign io_rsp_if.data[0] = io_rsp_data;
assign io_rsp_if.tag = io_rsp_tag;
assign io_rsp_ready = io_rsp_if.ready;
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH(`IDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH)
) icache_dram_rsp_if();
//--
assign I_dram_req_valid = icache_dram_req_if.valid;
assign I_dram_req_rw = icache_dram_req_if.rw;
assign I_dram_req_byteen= icache_dram_req_if.byteen;
assign I_dram_req_addr = icache_dram_req_if.addr;
assign I_dram_req_data = icache_dram_req_if.data;
assign I_dram_req_tag = icache_dram_req_if.tag;
assign icache_dram_req_if.ready = I_dram_req_ready;
VX_cache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_req_if();
assign icache_dram_rsp_if.valid = I_dram_rsp_valid;
assign icache_dram_rsp_if.data = I_dram_rsp_data;
assign icache_dram_rsp_if.tag = I_dram_rsp_tag;
assign I_dram_rsp_ready = icache_dram_rsp_if.ready;
VX_cache_core_rsp_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_dcache_rsp_if();
VX_cache_core_req_if #(
.NUM_REQS(`INUM_REQUESTS),
@ -171,7 +169,7 @@ module VX_core #(
.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
) core_icache_rsp_if();
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
@ -227,26 +225,7 @@ module VX_core #(
.ebreak(ebreak)
);
// Cache snooping interfaces
VX_cache_snp_req_if #(
.DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH),
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_req_if();
VX_cache_snp_rsp_if #(
.SNP_TAG_WIDTH(`DSNP_TAG_WIDTH)
) dcache_snp_rsp_if();
assign dcache_snp_req_if.valid = snp_req_valid;
assign dcache_snp_req_if.addr = snp_req_addr;
assign dcache_snp_req_if.invalidate = snp_req_inv;
assign dcache_snp_req_if.tag = snp_req_tag;
assign snp_req_ready = dcache_snp_req_if.ready;
assign snp_rsp_valid = dcache_snp_rsp_if.valid;
assign snp_rsp_tag = dcache_snp_rsp_if.tag;
assign dcache_snp_rsp_if.ready = snp_rsp_ready;
//--
VX_mem_unit #(
.CORE_ID(CORE_ID)
@ -257,38 +236,24 @@ module VX_core #(
.reset (reset),
// Core <-> Dcache
.core_dcache_req_if (arb_dcache_req_if),
.core_dcache_rsp_if (arb_dcache_rsp_if),
// DRAM <-> Dcache
.dcache_dram_req_if (dcache_dram_req_if),
.dcache_dram_rsp_if (dcache_dram_rsp_if),
.dcache_snp_req_if (dcache_snp_req_if),
.dcache_snp_rsp_if (dcache_snp_rsp_if),
.core_dcache_req_if (core_dcache_req_if),
.core_dcache_rsp_if (core_dcache_rsp_if),
// Core <-> Icache
.core_icache_req_if (core_icache_req_if),
.core_icache_rsp_if (core_icache_rsp_if),
// DRAM <-> Icache
.icache_dram_req_if (icache_dram_req_if),
.icache_dram_rsp_if (icache_dram_rsp_if)
);
// Dcache Snoop
.dcache_snp_req_if (dcache_snp_req_if),
.dcache_snp_rsp_if (dcache_snp_rsp_if),
// select io bus
wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
wire io_req_select = (| core_dcache_req_if.valid) && is_io_addr;
wire io_rsp_select = (| arb_io_rsp_if.valid);
// DRAM
.dram_req_if (dram_req_if),
.dram_rsp_if (dram_rsp_if),
VX_dcache_arb dcache_io_arb (
.core_req_in_if (core_dcache_req_if),
.core_req_out0_if (arb_dcache_req_if),
.core_req_out1_if (arb_io_req_if),
.core_rsp_in0_if (arb_dcache_rsp_if),
.core_rsp_in1_if (arb_io_rsp_if),
.core_rsp_out_if (core_dcache_rsp_if),
.select_req (io_req_select),
.select_rsp (io_rsp_select)
// I/O
.io_req_if (io_req_if),
.io_rsp_if (io_rsp_if)
);
endmodule

2
hw/rtl/VX_io_arb.v → hw/rtl/VX_databus_arb.v
View file

@ -1,6 +1,6 @@
`include "VX_define.vh"
module VX_io_arb #(
module VX_databus_arb #(
parameter NUM_REQS = 1,
parameter WORD_SIZE = 1,
parameter TAG_IN_WIDTH = 1,

161
hw/rtl/VX_dcache_arb.v
View file

@ -1,50 +1,143 @@
`include "VX_define.vh"
module VX_dcache_arb (
input wire clk,
input wire reset,
// input request
VX_cache_core_req_if core_req_in_if,
VX_cache_core_req_if core_req_if,
// output 0 request
VX_cache_core_req_if core_req_out0_if,
// output requests
VX_cache_core_req_if cache_req_if,
VX_cache_core_req_if smem_req_if,
VX_cache_core_req_if io_req_if,
// output 1 request
VX_cache_core_req_if core_req_out1_if,
// input 0 response
VX_cache_core_rsp_if core_rsp_in0_if,
// input 1 response
VX_cache_core_rsp_if core_rsp_in1_if,
// input responses
VX_cache_core_rsp_if cache_rsp_if,
VX_cache_core_rsp_if smem_rsp_if,
VX_cache_core_rsp_if io_rsp_if,
// output response
VX_cache_core_rsp_if core_rsp_out_if,
// bus select
input wire select_req,
input wire select_rsp
VX_cache_core_rsp_if core_rsp_if
);
localparam REQ_DATAW = `NUM_THREADS + 1 + `NUM_THREADS * `DWORD_SIZE + `NUM_THREADS * (32-`CLOG2(`DWORD_SIZE)) + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
//
// input request buffer
//
VX_cache_core_req_if #(
.NUM_REQS(`DNUM_REQUESTS),
.WORD_SIZE(`DWORD_SIZE),
.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
) core_req_qual_if();
wire core_req_valid;
VX_skid_buffer #(
.DATAW (REQ_DATAW)
) req_buffer (
.clk (clk),
.reset (reset),
.valid_in ((| core_req_if.valid)),
.data_in ({core_req_if.valid, core_req_if.rw, core_req_if.byteen, core_req_if.addr, core_req_if.data, core_req_if.tag}),
.ready_in (core_req_if.ready),
.valid_out (core_req_valid),
.data_out ({core_req_qual_if.valid, core_req_qual_if.rw, core_req_qual_if.byteen, core_req_qual_if.addr, core_req_qual_if.data, core_req_qual_if.tag}),
.ready_out (core_req_qual_if.ready)
);
//
// select request
assign core_req_out0_if.valid = core_req_in_if.valid & {`NUM_THREADS{~select_req}};
assign core_req_out0_if.rw = core_req_in_if.rw;
assign core_req_out0_if.byteen = core_req_in_if.byteen;
assign core_req_out0_if.addr = core_req_in_if.addr;
assign core_req_out0_if.data = core_req_in_if.data;
assign core_req_out0_if.tag = core_req_in_if.tag;
//
assign core_req_out1_if.valid = core_req_in_if.valid & {`NUM_THREADS{select_req}};
assign core_req_out1_if.rw = core_req_in_if.rw;
assign core_req_out1_if.byteen = core_req_in_if.byteen;
assign core_req_out1_if.addr = core_req_in_if.addr;
assign core_req_out1_if.data = core_req_in_if.data;
assign core_req_out1_if.tag = core_req_in_if.tag;
// select shared memory bus
wire is_smem_addr = core_req_valid
&& ({core_req_qual_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
&& ({core_req_qual_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SMEM_SIZE));
assign core_req_in_if.ready = select_req ? core_req_out1_if.ready : core_req_out0_if.ready;
// select io bus
wire is_io_addr = core_req_valid
&& ({core_req_qual_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR);
reg [2:0] req_select;
reg req_ready;
assign cache_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[0]}};
assign cache_req_if.rw = core_req_qual_if.rw;
assign cache_req_if.byteen = core_req_qual_if.byteen;
assign cache_req_if.addr = core_req_qual_if.addr;
assign cache_req_if.data = core_req_qual_if.data;
assign cache_req_if.tag = core_req_qual_if.tag;
assign smem_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[1]}};
assign smem_req_if.rw = core_req_qual_if.rw;
assign smem_req_if.byteen = core_req_qual_if.byteen;
assign smem_req_if.addr = core_req_qual_if.addr;
assign smem_req_if.data = core_req_qual_if.data;
assign smem_req_if.tag = core_req_qual_if.tag;
assign io_req_if.valid = core_req_qual_if.valid & {`NUM_THREADS{req_select[2]}};
assign io_req_if.rw = core_req_qual_if.rw;
assign io_req_if.byteen = core_req_qual_if.byteen;
assign io_req_if.addr = core_req_qual_if.addr;
assign io_req_if.data = core_req_qual_if.data;
assign io_req_if.tag = core_req_qual_if.tag;
assign core_req_qual_if.ready = req_ready;
always @(*) begin
req_select = 0;
if (is_smem_addr) begin
req_select[1] = 1;
req_ready = smem_req_if.ready;
end else if (is_io_addr) begin
req_select[2] = 1;
req_ready = io_req_if.ready;
end else begin
req_select[0] = 1;
req_ready = cache_req_if.ready;
end
end
//
// select response
assign core_rsp_out_if.valid = select_rsp ? core_rsp_in1_if.valid : core_rsp_in0_if.valid;
assign core_rsp_out_if.data = select_rsp ? core_rsp_in1_if.data : core_rsp_in0_if.data;
assign core_rsp_out_if.tag = select_rsp ? core_rsp_in1_if.tag : core_rsp_in0_if.tag;
assign core_rsp_in0_if.ready = core_rsp_out_if.ready && ~select_rsp;
assign core_rsp_in1_if.ready = core_rsp_out_if.ready && select_rsp;
//
wire [2:0][RSP_DATAW-1:0] rsp_data_in;
wire [2:0] rsp_valid_in;
wire [2:0] rsp_ready_in;
wire core_rsp_valid;
wire [`NUM_THREADS-1:0] core_rsp_tmask;
assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag};
assign rsp_data_in[2] = {io_rsp_if.valid, io_rsp_if.data, io_rsp_if.tag};
assign rsp_valid_in[0] = (| cache_rsp_if.valid);
assign rsp_valid_in[1] = (| smem_rsp_if.valid);
assign rsp_valid_in[2] = (| io_rsp_if.valid);
VX_stream_arbiter #(
.NUM_REQS (3),
.DATAW (RSP_DATAW),
.BUFFERED (1)
) rsp_arb (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_in),
.data_in (rsp_data_in),
.ready_in (rsp_ready_in),
.valid_out (core_rsp_valid),
.data_out ({core_rsp_tmask, core_rsp_if.data, core_rsp_if.tag}),
.ready_out (core_rsp_if.ready)
);
assign cache_rsp_if.ready = rsp_ready_in[0];
assign smem_rsp_if.ready = rsp_ready_in[1];
assign io_rsp_if.ready = rsp_ready_in[2];
assign core_rsp_if.valid = core_rsp_tmask & {`NUM_THREADS{core_rsp_valid}};
endmodule

14
hw/rtl/VX_define.vh
View file

@ -363,14 +363,11 @@
`define L2DRAM_BYTEEN_WIDTH `L2BANK_LINE_SIZE
// DRAM request tag bits
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`L2DRAM_ADDR_WIDTH+`CLOG2(`NUM_CORES*2)))
`define L2DRAM_TAG_WIDTH (`L2_ENABLE ? `L2DRAM_ADDR_WIDTH : (`XDRAM_TAG_WIDTH+`CLOG2(`NUM_CORES)))
// Snoop request tag bits
`define L2SNP_TAG_WIDTH (`L3_ENABLE ? `LOG2UP(`L3SNRQ_SIZE) : `L3SNP_TAG_WIDTH)
// Core request size
`define L2NUM_REQUESTS (2 * `NUM_CORES)
////////////////////////// L3cache Configurable Knobs /////////////////////////
// Cache ID
@ -398,10 +395,7 @@
`define L3DRAM_TAG_WIDTH (`L3_ENABLE ? `L3DRAM_ADDR_WIDTH : `L2DRAM_TAG_WIDTH)
// Snoop request tag bits
`define L3SNP_TAG_WIDTH 16
// Core request size
`define L3NUM_REQUESTS `NUM_CLUSTERS
`define L3SNP_TAG_WIDTH 16
///////////////////////////////////////////////////////////////////////////////
@ -413,7 +407,9 @@
`define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH
`define VX_CSR_ID_WIDTH `LOG2UP(`NUM_CLUSTERS * `NUM_CORES)
`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
`define TO_FULL_ADDR(x) {x, (32-$bits(x))'(0)}
`define XDRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH+`CLOG2(2))
`include "VX_types.vh"

389
hw/rtl/VX_mem_unit.v
View file

@ -11,123 +11,75 @@ module VX_mem_unit # (
// Core <-> Dcache
VX_cache_core_req_if core_dcache_req_if,
VX_cache_core_rsp_if core_dcache_rsp_if,
// DRAM <-> Dcache
VX_cache_dram_req_if dcache_dram_req_if,
VX_cache_dram_rsp_if dcache_dram_rsp_if,
VX_cache_snp_req_if dcache_snp_req_if,
VX_cache_snp_rsp_if dcache_snp_rsp_if,
// Core <-> Icache
VX_cache_core_req_if core_icache_req_if,
VX_cache_core_rsp_if core_icache_rsp_if,
// DRAM <-> Icache
VX_cache_dram_req_if icache_dram_req_if,
VX_cache_dram_rsp_if icache_dram_rsp_if
// Dcache Snoop
VX_cache_snp_req_if dcache_snp_req_if,
VX_cache_snp_rsp_if dcache_snp_rsp_if,
// DRAM
VX_cache_dram_req_if dram_req_if,
VX_cache_dram_rsp_if dram_rsp_if,
// I/O
VX_cache_core_req_if io_req_if,
VX_cache_core_rsp_if io_rsp_if
);
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH (`DDRAM_LINE_WIDTH),
.DRAM_ADDR_WIDTH (`DDRAM_ADDR_WIDTH),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH)
) dcache_dram_req_if(), icache_dram_req_if();
VX_cache_dram_rsp_if #(
.DRAM_LINE_WIDTH (`DDRAM_LINE_WIDTH),
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH)
) dcache_dram_rsp_if(), icache_dram_rsp_if();
VX_cache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) core_dcache_req_qual_if(), core_smem_req_if();
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_req_if();
VX_cache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) core_dcache_rsp_qual_if(), core_smem_rsp_if();
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) dcache_rsp_if();
// select shared memory bus
wire is_smem_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `SHARED_MEM_BASE_ADDR)
&& ({core_dcache_req_if.addr[0], 2'b0} < (`SHARED_MEM_BASE_ADDR + `SCACHE_SIZE));
VX_cache_core_req_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) smem_req_if();
wire smem_req_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0;
wire smem_rsp_select = (| core_smem_rsp_if.valid);
VX_cache_core_rsp_if #(
.NUM_REQS (`DNUM_REQUESTS),
.WORD_SIZE (`DWORD_SIZE),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS)
) smem_rsp_if();
VX_dcache_arb dcache_smem_arb (
.core_req_in_if (core_dcache_req_if),
.core_req_out0_if (core_dcache_req_qual_if),
.core_req_out1_if (core_smem_req_if),
.core_rsp_in0_if (core_dcache_rsp_qual_if),
.core_rsp_in1_if (core_smem_rsp_if),
.core_rsp_out_if (core_dcache_rsp_if),
.select_req (smem_req_select),
.select_rsp (smem_rsp_select)
);
VX_dcache_arb dcache_arb (
.clk (clk),
.reset (reset),
VX_cache #(
.CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SCACHE_SIZE),
.BANK_LINE_SIZE (`SBANK_LINE_SIZE),
.NUM_BANKS (`SNUM_BANKS),
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQS (`SNUM_REQUESTS),
.CREQ_SIZE (`SCREQ_SIZE),
.MSHR_SIZE (8),
.DRFQ_SIZE (1),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DREQ_SIZE (1),
.SNPQ_SIZE (1),
.DRAM_ENABLE (0),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_BIND_VX_mem_unit_smem
.clk (clk),
.reset (reset),
.core_req_if (core_dcache_req_if),
.cache_req_if (dcache_req_if),
.smem_req_if (smem_req_if),
.io_req_if (io_req_if),
// Core request
.core_req_valid (core_smem_req_if.valid),
.core_req_rw (core_smem_req_if.rw),
.core_req_byteen (core_smem_req_if.byteen),
.core_req_addr (core_smem_req_if.addr),
.core_req_data (core_smem_req_if.data),
.core_req_tag (core_smem_req_if.tag),
.core_req_ready (core_smem_req_if.ready),
// Core response
.core_rsp_valid (core_smem_rsp_if.valid),
.core_rsp_data (core_smem_rsp_if.data),
.core_rsp_tag (core_smem_rsp_if.tag),
.core_rsp_ready (core_smem_rsp_if.ready),
// DRAM request
`UNUSED_PIN (dram_req_valid),
`UNUSED_PIN (dram_req_rw),
`UNUSED_PIN (dram_req_byteen),
`UNUSED_PIN (dram_req_addr),
`UNUSED_PIN (dram_req_data),
`UNUSED_PIN (dram_req_tag),
.dram_req_ready (1'b0),
// DRAM response
.dram_rsp_valid (0),
.dram_rsp_data (0),
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Miss status
`UNUSED_PIN (miss_vec)
.cache_rsp_if (dcache_rsp_if),
.smem_rsp_if (smem_rsp_if),
.io_rsp_if (io_rsp_if),
.core_rsp_if (core_dcache_rsp_if)
);
VX_cache #(
@ -158,19 +110,19 @@ module VX_mem_unit # (
.reset (reset),
// Core req
.core_req_valid (core_dcache_req_qual_if.valid),
.core_req_rw (core_dcache_req_qual_if.rw),
.core_req_byteen (core_dcache_req_qual_if.byteen),
.core_req_addr (core_dcache_req_qual_if.addr),
.core_req_data (core_dcache_req_qual_if.data),
.core_req_tag (core_dcache_req_qual_if.tag),
.core_req_ready (core_dcache_req_qual_if.ready),
.core_req_valid (dcache_req_if.valid),
.core_req_rw (dcache_req_if.rw),
.core_req_byteen (dcache_req_if.byteen),
.core_req_addr (dcache_req_if.addr),
.core_req_data (dcache_req_if.data),
.core_req_tag (dcache_req_if.tag),
.core_req_ready (dcache_req_if.ready),
// Core response
.core_rsp_valid (core_dcache_rsp_qual_if.valid),
.core_rsp_data (core_dcache_rsp_qual_if.data),
.core_rsp_tag (core_dcache_rsp_qual_if.tag),
.core_rsp_ready (core_dcache_rsp_qual_if.ready),
.core_rsp_valid (dcache_rsp_if.valid),
.core_rsp_data (dcache_rsp_if.data),
.core_rsp_tag (dcache_rsp_if.tag),
.core_rsp_ready (dcache_rsp_if.ready),
// DRAM request
.dram_req_valid (dcache_dram_req_if.valid),
@ -204,66 +156,66 @@ module VX_mem_unit # (
);
VX_cache #(
.CACHE_ID (`ICACHE_ID),
.CACHE_SIZE (`ICACHE_SIZE),
.BANK_LINE_SIZE (`IBANK_LINE_SIZE),
.NUM_BANKS (`INUM_BANKS),
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQS (`INUM_REQUESTS),
.CREQ_SIZE (`ICREQ_SIZE),
.MSHR_SIZE (`IMSHR_SIZE),
.DRFQ_SIZE (`IDRFQ_SIZE),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DREQ_SIZE (`IDREQ_SIZE),
.SNPQ_SIZE (1),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (0),
.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
.CACHE_ID (`ICACHE_ID),
.CACHE_SIZE (`ICACHE_SIZE),
.BANK_LINE_SIZE (`IBANK_LINE_SIZE),
.NUM_BANKS (`INUM_BANKS),
.WORD_SIZE (`IWORD_SIZE),
.NUM_REQS (`INUM_REQUESTS),
.CREQ_SIZE (`ICREQ_SIZE),
.MSHR_SIZE (`IMSHR_SIZE),
.DRFQ_SIZE (`IDRFQ_SIZE),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`ICWBQ_SIZE),
.DREQ_SIZE (`IDREQ_SIZE),
.SNPQ_SIZE (1),
.DRAM_ENABLE (1),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (0),
.CORE_TAG_WIDTH (`ICORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) icache (
`SCOPE_BIND_VX_mem_unit_icache
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core request
.core_req_valid (core_icache_req_if.valid),
.core_req_rw (core_icache_req_if.rw),
.core_req_byteen (core_icache_req_if.byteen),
.core_req_addr (core_icache_req_if.addr),
.core_req_data (core_icache_req_if.data),
.core_req_tag (core_icache_req_if.tag),
.core_req_ready (core_icache_req_if.ready),
.core_req_valid (core_icache_req_if.valid),
.core_req_rw (core_icache_req_if.rw),
.core_req_byteen (core_icache_req_if.byteen),
.core_req_addr (core_icache_req_if.addr),
.core_req_data (core_icache_req_if.data),
.core_req_tag (core_icache_req_if.tag),
.core_req_ready (core_icache_req_if.ready),
// Core response
.core_rsp_valid (core_icache_rsp_if.valid),
.core_rsp_data (core_icache_rsp_if.data),
.core_rsp_tag (core_icache_rsp_if.tag),
.core_rsp_ready (core_icache_rsp_if.ready),
.core_rsp_valid (core_icache_rsp_if.valid),
.core_rsp_data (core_icache_rsp_if.data),
.core_rsp_tag (core_icache_rsp_if.tag),
.core_rsp_ready (core_icache_rsp_if.ready),
// DRAM Req
.dram_req_valid (icache_dram_req_if.valid),
.dram_req_rw (icache_dram_req_if.rw),
.dram_req_byteen (icache_dram_req_if.byteen),
.dram_req_addr (icache_dram_req_if.addr),
.dram_req_data (icache_dram_req_if.data),
.dram_req_tag (icache_dram_req_if.tag),
.dram_req_ready (icache_dram_req_if.ready),
.dram_req_valid (icache_dram_req_if.valid),
.dram_req_rw (icache_dram_req_if.rw),
.dram_req_byteen (icache_dram_req_if.byteen),
.dram_req_addr (icache_dram_req_if.addr),
.dram_req_data (icache_dram_req_if.data),
.dram_req_tag (icache_dram_req_if.tag),
.dram_req_ready (icache_dram_req_if.ready),
// DRAM response
.dram_rsp_valid (icache_dram_rsp_if.valid),
.dram_rsp_data (icache_dram_rsp_if.data),
.dram_rsp_tag (icache_dram_rsp_if.tag),
.dram_rsp_ready (icache_dram_rsp_if.ready),
.dram_rsp_valid (icache_dram_rsp_if.valid),
.dram_rsp_data (icache_dram_rsp_if.data),
.dram_rsp_tag (icache_dram_rsp_if.tag),
.dram_rsp_ready (icache_dram_rsp_if.ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (1'b0),
.snp_req_tag (0),
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (1'b0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
// Snoop response
@ -273,6 +225,119 @@ module VX_mem_unit # (
// Miss status
`UNUSED_PIN (miss_vec)
);
VX_cache #(
.CACHE_ID (`SCACHE_ID),
.CACHE_SIZE (`SMEM_SIZE),
.BANK_LINE_SIZE (`SBANK_LINE_SIZE),
.NUM_BANKS (`SNUM_BANKS),
.WORD_SIZE (`SWORD_SIZE),
.NUM_REQS (`SNUM_REQUESTS),
.CREQ_SIZE (`SCREQ_SIZE),
.MSHR_SIZE (8),
.DRFQ_SIZE (1),
.SNRQ_SIZE (1),
.CWBQ_SIZE (`SCWBQ_SIZE),
.DREQ_SIZE (1),
.SNPQ_SIZE (1),
.DRAM_ENABLE (0),
.FLUSH_ENABLE (0),
.WRITE_ENABLE (1),
.CORE_TAG_WIDTH (`DCORE_TAG_WIDTH),
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_BIND_VX_mem_unit_smem
.clk (clk),
.reset (reset),
// Core request
.core_req_valid (smem_req_if.valid),
.core_req_rw (smem_req_if.rw),
.core_req_byteen (smem_req_if.byteen),
.core_req_addr (smem_req_if.addr),
.core_req_data (smem_req_if.data),
.core_req_tag (smem_req_if.tag),
.core_req_ready (smem_req_if.ready),
// Core response
.core_rsp_valid (smem_rsp_if.valid),
.core_rsp_data (smem_rsp_if.data),
.core_rsp_tag (smem_rsp_if.tag),
.core_rsp_ready (smem_rsp_if.ready),
// DRAM request
`UNUSED_PIN (dram_req_valid),
`UNUSED_PIN (dram_req_rw),
`UNUSED_PIN (dram_req_byteen),
`UNUSED_PIN (dram_req_addr),
`UNUSED_PIN (dram_req_data),
`UNUSED_PIN (dram_req_tag),
.dram_req_ready (1'b0),
// DRAM response
.dram_rsp_valid (0),
.dram_rsp_data (0),
.dram_rsp_tag (0),
`UNUSED_PIN (dram_rsp_ready),
// Snoop request
.snp_req_valid (1'b0),
.snp_req_addr (0),
.snp_req_inv (0),
.snp_req_tag (0),
`UNUSED_PIN (snp_req_ready),
// Snoop response
`UNUSED_PIN (snp_rsp_valid),
`UNUSED_PIN (snp_rsp_tag),
.snp_rsp_ready (1'b0),
// Miss status
`UNUSED_PIN (miss_vec)
);
VX_mem_arb #(
.NUM_REQS (2),
.DATA_WIDTH (`DDRAM_LINE_WIDTH),
.ADDR_WIDTH (`DDRAM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DDRAM_TAG_WIDTH),
.TAG_OUT_WIDTH (`XDRAM_TAG_WIDTH)
) dram_arb (
.clk (clk),
.reset (reset),
// Source request
.req_valid_in ({dcache_dram_req_if.valid, icache_dram_req_if.valid}),
.req_rw_in ({dcache_dram_req_if.rw, icache_dram_req_if.rw}),
.req_byteen_in ({dcache_dram_req_if.byteen, icache_dram_req_if.byteen}),
.req_addr_in ({dcache_dram_req_if.addr, icache_dram_req_if.addr}),
.req_data_in ({dcache_dram_req_if.data, icache_dram_req_if.data}),
.req_tag_in ({dcache_dram_req_if.tag, icache_dram_req_if.tag}),
.req_ready_in ({dcache_dram_req_if.ready, icache_dram_req_if.ready}),
// DRAM request
.req_valid_out (dram_req_if.valid),
.req_rw_out (dram_req_if.rw),
.req_byteen_out (dram_req_if.byteen),
.req_addr_out (dram_req_if.addr),
.req_data_out (dram_req_if.data),
.req_tag_out (dram_req_if.tag),
.req_ready_out (dram_req_if.ready),
// Source response
.rsp_valid_out ({dcache_dram_rsp_if.valid, icache_dram_rsp_if.valid}),
.rsp_data_out ({dcache_dram_rsp_if.data, icache_dram_rsp_if.data}),
.rsp_tag_out ({dcache_dram_rsp_if.tag, icache_dram_rsp_if.tag}),
.rsp_ready_out ({dcache_dram_rsp_if.ready, icache_dram_rsp_if.ready}),
// DRAM response
.rsp_valid_in (dram_rsp_if.valid),
.rsp_tag_in (dram_rsp_if.tag),
.rsp_data_in (dram_rsp_if.data),
.rsp_ready_in (dram_rsp_if.ready)
);
endmodule

35
hw/rtl/Vortex.v
View file

@ -242,7 +242,7 @@ module Vortex (
);
end
VX_io_arb #(
VX_databus_arb #(
.NUM_REQS (`NUM_CLUSTERS),
.WORD_SIZE (4),
.TAG_IN_WIDTH (`L2CORE_TAG_WIDTH),
@ -322,30 +322,31 @@ module Vortex (
// L3 Cache ///////////////////////////////////////////////////////////
wire [`L3NUM_REQUESTS-1:0] cluster_dram_rsp_valid;
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] cluster_dram_rsp_data;
wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] cluster_dram_rsp_tag;
wire cluster_dram_rsp_ready;
wire [`NUM_CLUSTERS-1:0] cluster_dram_rsp_valid;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] cluster_dram_rsp_data;
wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] cluster_dram_rsp_tag;
wire cluster_dram_rsp_ready;
wire snp_fwd_rsp_valid;
wire [`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L3SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
wire snp_fwd_rsp_valid;
wire [`L3DRAM_ADDR_WIDTH-1:0] snp_fwd_rsp_addr;
wire snp_fwd_rsp_inv;
wire [`L3SNP_TAG_WIDTH-1:0] snp_fwd_rsp_tag;
wire snp_fwd_rsp_ready;
reg [`L3NUM_REQUESTS-1:0] cluster_dram_rsp_ready_other;
reg [`NUM_CLUSTERS-1:0] cluster_dram_rsp_ready_other;
always @(*) begin
cluster_dram_rsp_ready_other = {`L3NUM_REQUESTS{1'b1}};
for (integer i = 0; i < `L3NUM_REQUESTS; i++) begin
for (integer j = 0; j < `L3NUM_REQUESTS; j++) begin
if (i != j)
cluster_dram_rsp_ready_other = {`NUM_CLUSTERS{1'b1}};
for (integer i = 0; i < `NUM_CLUSTERS; i++) begin
for (integer j = 0; j < `NUM_CLUSTERS; j++) begin
if (i != j) begin
cluster_dram_rsp_ready_other[i] &= (per_cluster_dram_rsp_ready [j] | !cluster_dram_rsp_valid [j]);
end
end
end
end
for (genvar i = 0; i < `L3NUM_REQUESTS; i++) begin
for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin
// Core Response
assign per_cluster_dram_rsp_valid [i] = cluster_dram_rsp_valid [i] & cluster_dram_rsp_ready_other [i];
assign per_cluster_dram_rsp_data [i] = cluster_dram_rsp_data [i];
@ -393,7 +394,7 @@ module Vortex (
.BANK_LINE_SIZE (`L3BANK_LINE_SIZE),
.NUM_BANKS (`L3NUM_BANKS),
.WORD_SIZE (`L3WORD_SIZE),
.NUM_REQS (`L3NUM_REQUESTS),
.NUM_REQS (`NUM_CLUSTERS),
.CREQ_SIZE (`L3CREQ_SIZE),
.MSHR_SIZE (`L3MSHR_SIZE),
.DRFQ_SIZE (`L3DRFQ_SIZE),

3
hw/rtl/libs/VX_fixed_arbiter.v
View file

@ -35,7 +35,8 @@ module VX_fixed_arbiter #(
for (integer i = 0; i < NUM_REQS; ++i) begin
if (requests[i]) begin
grant_index_r = LOG_NUM_REQS'(i);
grant_onehot_r = NUM_REQS'(1) << i;
grant_onehot_r = NUM_REQS'(0);
grant_onehot_r[i] = 1;
break;
end
end