migration to Verilator v4.228

ci/prebuilt.sh

@@ -21,15 +21,6 @@ riscv()
 }
 
 llvm() 
-{
-    echo "prebuilt llvm-riscv..."
-    tar -C $SRCDIR -cvjf llvm-riscv.tar.bz2 llvm-riscv
-    split -b 50M llvm-riscv.tar.bz2 "llvm-riscv.tar.bz2.part"    
-    mv llvm-riscv.tar.bz2.part* $DESTDIR/llvm-riscv/$OS_DIR
-    rm llvm-riscv.tar.bz2
-}
-
-llvm2() 
 {
     echo "prebuilt llvm-riscv2..."
     tar -C $SRCDIR -cvjf llvm-riscv2.tar.bz2 llvm-riscv
@@ -40,36 +31,27 @@ llvm2()
 
 pocl() 
 {
-    echo "prebuilt pocl..."
-    tar -C $SRCDIR -cvjf pocl.tar.bz2 pocl
-    mv pocl.tar.bz2 $DESTDIR/pocl/$OS_DIR
-}
-
-pocl2() 
-{
-    echo "prebuilt pocl..."
+    echo "prebuilt pocl2..."
     tar -C $SRCDIR -cvjf pocl2.tar.bz2 pocl
     mv pocl2.tar.bz2 $DESTDIR/pocl/$OS_DIR
 }
 
 verilator() 
 {
-    echo "prebuilt verilator..."
-    tar -C $SRCDIR -cvjf verilator.tar.bz2 verilator
-    mv verilator.tar.bz2 $DESTDIR/verilator/$OS_DIR
+    echo "prebuilt verilator2..."
+    tar -C $SRCDIR -cvjf verilator2.tar.bz2 verilator
+    mv verilator2.tar.bz2 $DESTDIR/verilator/$OS_DIR
 }
 
 usage()
 {
-    echo "usage: prebuilt [[-riscv] [-llvm] [-pocl] [-llvm2] [-pocl2] [-verilator] [-all] [-h|--help]]"
+    echo "usage: prebuilt [[-riscv] [-llvm] [-pocl] [-verilator] [-all] [-h|--help]]"
 }
 
 while [ "$1" != "" ]; do
     case $1 in
         -pocl ) pocl
                 ;;
-        -pocl2 ) pocl2
-                ;;
         -verilator ) verilator
                      ;;
         -riscv ) riscv
@@ -77,8 +59,8 @@ while [ "$1" != "" ]; do
         -llvm ) llvm
                 ;;
         -all ) riscv
-               llvm2
-               pocl2
+               llvm
+               pocl
                verilator
                ;;
         -h | --help ) usage

ci/regression.sh

@@ -267,6 +267,8 @@ usage()
     echo "usage: regression [-smoke] [-unittest] [-coverage] [-tex] [-rop] [-raster] [-graphics] [-cluster] [-debug] [-config] [-stress[#n]] [-all] [-h|--help]"
 }
 
+start=$SECONDS
+
 while [ "$1" != "" ]; do
     case $1 in
         -smoke ) smoke
@@ -315,4 +317,9 @@ while [ "$1" != "" ]; do
                       exit 1
     esac
     shift
-done
+done
+
+echo "Regression completed!"
+
+duration=$(( SECONDS - start ))
+awk -v t=$duration 'BEGIN{t=int(t*1000); printf "Elapsed Time: %d:%02d:%02d\n", t/3600000, t/60000%60, t/1000%60}'

ci/toolchain_install.sh

@@ -42,25 +42,6 @@ riscv64()
 }
 
 llvm()
-{
-    case $OS in
-    "centos/7") parts=$(eval echo {a..g}) ;;
-    *)          parts=$(eval echo {a..b}) ;;
-    esac
-    echo $parts
-    rm -f llvm-riscv.tar.bz2.parta*
-    for x in $parts
-    do
-        wget $REPOSITORY/llvm-riscv/$OS/llvm-riscv.tar.bz2.parta$x
-    done
-    cat llvm-riscv.tar.bz2.parta* > llvm-riscv.tar.bz2
-    tar -xvf llvm-riscv.tar.bz2
-    rm -f llvm-riscv.tar.bz2*
-    cp -r llvm-riscv $DESTDIR
-    rm -rf llvm-riscv
-}
-
-llvm2()
 {
     case $OS in
     "centos/7") parts=$(eval echo {a..g}) ;;
@@ -80,15 +61,6 @@ llvm2()
 }
 
 pocl()
-{
-    wget $REPOSITORY/pocl/$OS/pocl.tar.bz2
-    tar -xvf pocl.tar.bz2
-    rm -f pocl.tar.bz2
-    cp -r pocl $DESTDIR
-    rm -rf pocl
-}
-
-pocl2()
 {
     wget $REPOSITORY/pocl/$OS/pocl2.tar.bz2
     tar -xvf pocl2.tar.bz2
@@ -99,24 +71,22 @@ pocl2()
 
 verilator()
 {
-    wget $REPOSITORY/verilator/$OS/verilator.tar.bz2
-    tar -xvf verilator.tar.bz2
-    rm -f verilator.tar.bz2
+    wget $REPOSITORY/verilator/$OS/verilator2.tar.bz2
+    tar -xvf verilator2.tar.bz2
+    rm -f verilator2.tar.bz2
     cp -r verilator $DESTDIR
     rm -rf verilator
 }
 
 usage()
 {
-    echo "usage: toolchain_install [[-riscv] [-riscv64] [-llvm] [-llvm2] [-pocl] [-pocl2] [-verilator] [-all] [-h|--help]]"
+    echo "usage: toolchain_install [[-riscv] [-riscv64] [-llvm] [-pocl] [-verilator] [-all] [-h|--help]]"
 }
 
 while [ "$1" != "" ]; do
     case $1 in
         -pocl ) pocl
                 ;;
-        -pocl2 ) pocl2
-                ;;
         -verilator ) verilator
                      ;;
         -riscv ) riscv
@@ -125,12 +95,10 @@ while [ "$1" != "" ]; do
                  ;;
         -llvm ) llvm
                 ;;
-        -llvm2 ) llvm2
-                ;;
         -all ) riscv
                riscv64
-               llvm2
-               pocl2
+               llvm
+               pocl
                verilator
                ;;
         -h | --help ) usage

hw/rtl/VX_core.sv

@@ -622,4 +622,4 @@ module VX_core_top #(
         .busy           (busy)
     );
 
-endmodule
+endmodule

hw/rtl/VX_gpu_types.vh

@@ -35,6 +35,8 @@ typedef struct packed {
     logic [7:0]             mpm_class;
 } base_dcrs_t;
 
+/* verilator lint_off UNUSED */
+
 ////////////////////////// Icache Parameters //////////////////////////////////
 
 // Word size in bytes
@@ -258,6 +260,8 @@ localparam L3_MEM_TAG_WIDTH     = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM
 localparam L3_MEM_TAG_WIDTH     = `CACHE_NC_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH);
 `endif
 
+/* verilator lint_on UNUSED */
+
 endpackage
 
 `define GPU_TMC_BITS        $bits(VX_gpu_types::gpu_tmc_t)
@@ -265,4 +269,4 @@ endpackage
 `define GPU_SPLIT_BITS      $bits(VX_gpu_types::gpu_split_t)
 `define GPU_BARRIER_BITS    $bits(VX_gpu_types::gpu_barrier_t)
 
-`endif
+`endif

hw/rtl/VX_gpu_unit.sv

@@ -57,6 +57,10 @@ module VX_gpu_unit #(
     localparam RSP_ARB_IDX_ROP    = RSP_ARB_IDX_RASTER + `EXT_RASTER_ENABLED;    
     localparam RSP_ARB_IDX_TEX    = RSP_ARB_IDX_ROP + `EXT_ROP_ENABLED;    
     localparam RSP_ARB_IDX_IMADD  = RSP_ARB_IDX_TEX + `EXT_TEX_ENABLED;
+    `UNUSED_PARAM (RSP_ARB_IDX_RASTER)
+    `UNUSED_PARAM (RSP_ARB_IDX_ROP)
+    `UNUSED_PARAM (RSP_ARB_IDX_TEX)
+    `UNUSED_PARAM (RSP_ARB_IDX_IMADD)
 
     wire [RSP_ARB_SIZE-1:0] rsp_arb_valid_in;
     wire [RSP_ARB_SIZE-1:0] rsp_arb_ready_in;

hw/rtl/VX_lsu_unit.sv

@@ -31,6 +31,7 @@ module VX_lsu_unit #(
     localparam MEM_ADDRW  = 32 - MEM_ASHIFT;
     localparam REQ_ASHIFT = `CLOG2(DCACHE_WORD_SIZE);
 
+`ifdef SM_ENABLE
     localparam STACK_SIZE_W = `STACK_SIZE >> MEM_ASHIFT;
     localparam STACK_ADDR_W = `CLOG2(STACK_SIZE_W);
     localparam SMEM_LOCAL_SIZE_W = `SMEM_LOCAL_SIZE >> MEM_ASHIFT;
@@ -38,6 +39,7 @@ module VX_lsu_unit #(
     localparam TOTAL_STACK_SIZE = `STACK_SIZE * `NUM_THREADS * `NUM_WARPS * `NUM_CORES;
     localparam STACK_START_W = MEM_ADDRW'(`STACK_BASE_ADDR >> MEM_ASHIFT);
     localparam STACK_END_W = MEM_ADDRW'((`STACK_BASE_ADDR - TOTAL_STACK_SIZE) >> MEM_ASHIFT);
+`endif
 
     //                     uuid,        addr_type,                               wid,       PC,  tmask,         rd,        op_type,         align,                        is_dup
     localparam TAG_WIDTH = UUID_WIDTH + (`NUM_THREADS * `CACHE_ADDR_TYPE_BITS) + NW_WIDTH + 32 + `NUM_THREADS + `NR_BITS + `INST_LSU_BITS + (`NUM_THREADS * REQ_ASHIFT) + 1;

hw/rtl/VX_mem_unit.sv

@@ -150,7 +150,6 @@ module VX_mem_unit # (
         .UUID_WIDTH     (`UUID_BITS),
         .WRITE_ENABLE   (1),        
         .NC_ENABLE      (1),
-        .NC_TAG_BIT     (0),
         .CORE_OUT_REG   (`SM_ENABLED ? 2 : 3),
         .MEM_OUT_REG    (3)
     ) dcache (

hw/rtl/VX_platform.vh

@@ -56,6 +56,10 @@
                          localparam  __``x = x; \
                          /* verilator lint_on UNUSED */
 
+`define UNUSED_SPARAM(x) /* verilator lint_off UNUSED */ \
+                         localparam `STRING_TYPE __``x = x; \
+                         /* verilator lint_on UNUSED */
+
 `define UNUSED_VAR(x) always @(x) begin end
 
 `define UNUSED_PIN(x)  /* verilator lint_off PINCONNECTEMPTY */ \
@@ -77,6 +81,7 @@
 `define IGNORE_WARNINGS_BEGIN
 `define IGNORE_WARNINGS_END
 `define UNUSED_PARAM(x)
+`define UNUSED_SPARAM(x)
 `define UNUSED_VAR(x)
 `define UNUSED_PIN(x) . x ()
 `define TRACE(level, args) $write args

hw/rtl/cache/VX_cache_cluster.sv

@@ -44,7 +44,6 @@ module VX_cache_cluster #(
     parameter TAG_WIDTH             = UUID_WIDTH + 1,
 
     // enable bypass for non-cacheable addresses
-    parameter NC_TAG_BIT            = 0,
     parameter NC_ENABLE             = 0,
 
     // Core response output register
@@ -256,7 +255,6 @@ module VX_cache_cluster_top #(
     parameter TAG_WIDTH             = 16,
 
     // enable bypass for non-cacheable addresses
-    parameter NC_TAG_BIT            = 0,
     parameter NC_ENABLE             = 1,
 
     // Core response output register
@@ -381,8 +379,6 @@ module VX_cache_cluster_top #(
         .TAG_WIDTH      (TAG_WIDTH),
         .UUID_WIDTH     (UUID_WIDTH),
         .WRITE_ENABLE   (WRITE_ENABLE),
-        .NC_TAG_BIT     (NC_TAG_BIT),
-        .NC_ENABLE      (NC_ENABLE),
         .CORE_OUT_REG   (CORE_OUT_REG),
         .MEM_OUT_REG    (MEM_OUT_REG)
     ) cache (

hw/rtl/cache/VX_cache_wrap.sv

@@ -79,7 +79,6 @@ module VX_cache_wrap #(
     `STATIC_ASSERT(NUM_PORTS <= NUM_REQS, ("invalid parameter"))
     `STATIC_ASSERT(NUM_PORTS <= `WORDS_PER_LINE, ("invalid parameter"))
 
-    localparam WORD_SEL_BITS    = `UP(`WORD_SEL_BITS);
     localparam MSHR_ADDR_WIDTH  = `LOG2UP(MSHR_SIZE);    
     localparam CORE_TAG_X_WIDTH = TAG_WIDTH - NC_ENABLE;
     localparam MEM_TAG_X_WIDTH  = MSHR_ADDR_WIDTH + `BANK_SEL_BITS;
@@ -91,9 +90,6 @@ module VX_cache_wrap #(
     localparam NC_BYPASS = (NC_ENABLE || PASSTHRU);
     localparam DIRECT_PASSTHRU = PASSTHRU && (`WORD_SEL_BITS == 0) && (NUM_REQS == 1);
 
-    localparam CORE_REQ_BUF_ENABLE = (1 != NUM_BANKS) || (1 != NUM_REQS);
-    localparam MEM_REQ_BUF_ENABLE  = (1 != NUM_BANKS);
-
     wire [NUM_REQS-1:0]                     core_req_valid;
     wire [NUM_REQS-1:0]                     core_req_rw;
     wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr;

hw/rtl/cache/VX_data_access.sv

@@ -42,6 +42,7 @@ module VX_data_access #(
 
     output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] read_data
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
     `UNUSED_PARAM (BANK_ID)
     `UNUSED_PARAM (WORD_SIZE)
     `UNUSED_VAR (reset)

hw/rtl/cache/VX_shared_mem.sv

@@ -48,6 +48,8 @@ module VX_shared_mem #(
     output wire [NUM_REQS-1:0][TAG_WIDTH-1:0]   rsp_tag,
     input  wire [NUM_REQS-1:0]                  rsp_ready
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
+    `UNUSED_PARAM (UUID_WIDTH)
 
     localparam WORD_WIDTH      = WORD_SIZE * 8;
     localparam REQ_SEL_BITS    = `CLOG2(NUM_REQS);

hw/rtl/cache/VX_tag_access.sv

@@ -33,12 +33,12 @@ module VX_tag_access #(
     output wire [NUM_WAYS-1:0]          way_sel,
     output wire                         tag_match
 );
-
+    `UNUSED_SPARAM (INSTANCE_ID)
     `UNUSED_PARAM (BANK_ID)
     `UNUSED_VAR (reset)
     `UNUSED_VAR (lookup)
 
-    localparam TAG_WIDTH = `TAG_SEL_BITS + 1;
+    localparam TAG_WIDTH = 1 + `TAG_SEL_BITS;
 
     wire [NUM_WAYS-1:0] tag_matches;
     wire [`LINE_SEL_BITS-1:0] line_addr = addr[`LINE_SEL_BITS-1:0];
@@ -68,7 +68,7 @@ module VX_tag_access #(
         wire read_valid;
 
         VX_sp_ram #(
-            .DATAW (1 + `TAG_SEL_BITS),
+            .DATAW (TAG_WIDTH),
             .SIZE  (`LINES_PER_BANK),
             .NO_RWCHECK (1)
         ) tag_store (

hw/rtl/fpu_unit/VX_fpu_agent.sv

@@ -21,6 +21,8 @@ module VX_fpu_agent #(
     input wire              csr_pending,
     output wire             req_pending
 );
+    `UNUSED_PARAM (CORE_ID)
+    
     localparam UUID_WIDTH = `UP(`UUID_BITS);
     localparam NW_WIDTH   = `UP(`NW_BITS);
     

hw/rtl/fpu_unit/VX_fpu_unit.sv

@@ -15,7 +15,9 @@ module VX_fpu_unit #(
 
     VX_fpu_req_if.slave fpu_req_if,
     VX_fpu_rsp_if.master fpu_rsp_if
-); 
+);
+    `UNUSED_SPARAM (INSTANCE_ID)
+
 `ifdef FPU_DPI
 
     VX_fpu_dpi #(

hw/rtl/libs/VX_avs_adapter.sv

@@ -189,4 +189,4 @@ module VX_avs_adapter #(
     );
 
 endmodule
-`TRACING_ON
+`TRACING_ON

hw/rtl/libs/VX_axi_adapter.sv

@@ -153,4 +153,4 @@ module VX_axi_adapter #(
     `RUNTIME_ASSERT(~m_axi_rvalid || m_axi_rresp == 0, ("%t: *** AXI response error", $time));
 
 endmodule
-`TRACING_ON
+`TRACING_ON

hw/rtl/libs/VX_mem_scheduler.sv

@@ -61,7 +61,6 @@ module VX_mem_scheduler #(
   );
 
     localparam REM_BATCH_SIZE = NUM_REQS % NUM_BANKS;
-    localparam BATCH_DATAW = NUM_BANKS * (1 + BYTEENW + ADDR_WIDTH + DATA_WIDTH);
     localparam REQ_CNTW = $clog2(NUM_REQS + 1);
     localparam BANK_CNTW = $clog2(NUM_BANKS + 1);
     localparam TAG_ONLY_WIDTH = TAG_WIDTH - MEM_TAG_ID;

hw/rtl/libs/VX_reduce.sv

@@ -32,4 +32,4 @@ module VX_reduce #(
     assign data_out = tmp[N-1];
   
 endmodule
-`TRACING_ON
+`TRACING_ON

hw/rtl/libs/VX_stream_arb.sv

@@ -319,7 +319,6 @@ module VX_stream_arb #(
 
             for (genvar i = 0; i < NUM_REQS; ++i) begin
                 for (genvar j = 0; j < NUM_LANES; ++j) begin
-                    localparam ii = i * NUM_LANES + j;
                     VX_skid_buffer #(
                         .DATAW    (DATAW),
                         .PASSTHRU (BUFFERED == 0),
@@ -344,7 +343,6 @@ module VX_stream_arb #(
 
         for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
             for (genvar j = 0; j < NUM_LANES; ++j) begin
-                localparam ii = i * NUM_LANES + j;
                 VX_skid_buffer #(
                     .DATAW    (DATAW),
                     .PASSTHRU (BUFFERED == 0),

hw/rtl/libs/VX_stream_switch.sv

@@ -6,7 +6,6 @@ module VX_stream_switch #(
     parameter NUM_OUTPUTS   = 1,
     parameter NUM_LANES     = 1,
     parameter DATAW         = 1,
-    parameter LOCK_ENABLE   = 1,
     parameter BUFFERED      = 0,
     parameter NUM_REQS      = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS),
     parameter SEL_COUNT     = `MIN(NUM_INPUTS, NUM_OUTPUTS),
@@ -133,7 +132,6 @@ module VX_stream_switch #(
 
         for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
             for (genvar j = 0; j < NUM_LANES; ++j) begin
-                localparam ii = i * NUM_LANES + j;
                 VX_skid_buffer #(
                     .DATAW    (DATAW),
                     .PASSTHRU (BUFFERED == 0),

hw/rtl/raster_unit/VX_raster_agent.sv

@@ -14,6 +14,7 @@ module VX_raster_agent #(
     VX_commit_if.master    raster_commit_if,
     VX_gpu_csr_if.slave    raster_csr_if    
 );
+    `UNUSED_PARAM (CORE_ID)
 
     localparam UUID_WIDTH = `UP(`UUID_BITS);
     localparam NW_WIDTH   = `UP(`NW_BITS);

hw/rtl/raster_unit/VX_raster_csr.sv

@@ -16,6 +16,8 @@ module VX_raster_csr #(
     // Output
     VX_gpu_csr_if.slave raster_csr_if
 );
+    `UNUSED_PARAM (CORE_ID)
+
     `UNUSED_VAR (reset)
 
     localparam NW_WIDTH      = `UP(`NW_BITS);

hw/rtl/raster_unit/VX_raster_dcr.sv

@@ -14,10 +14,12 @@ module VX_raster_dcr #(
     // Output
     output raster_dcrs_t    raster_dcrs
 );
-    localparam LOG2_NUM_INSTANCES = `CLOG2(NUM_INSTANCES);
+    `UNUSED_SPARAM (INSTANCE_ID)
 
     `UNUSED_VAR (reset)
 
+    localparam LOG2_NUM_INSTANCES = `CLOG2(NUM_INSTANCES);    
+
     // DCR registers
     raster_dcrs_t dcrs;
 

hw/rtl/raster_unit/VX_raster_qe.sv

@@ -36,6 +36,8 @@ module VX_raster_qe #(
     output wire [NUM_QUADS-1:0][`RASTER_DIM_BITS-1:0]   y_loc_out,    
     output wire [NUM_QUADS-1:0][2:0][3:0][`RASTER_DATA_BITS-1:0] bcoords_out
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
+
     `UNUSED_VAR (dcrs)
 
     wire [NUM_QUADS-1:0] valid;

hw/rtl/raster_unit/VX_raster_te.sv

@@ -32,6 +32,8 @@ module VX_raster_te #(
     output wire [2:0][2:0][`RASTER_DATA_BITS-1:0] edges_out,
     input wire                          ready_out
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
+
     localparam LEVEL_BITS      = (TILE_LOGSIZE - BLOCK_LOGSIZE) + 1;
     localparam TILE_FIFO_DEPTH = 1 << (2 * (TILE_LOGSIZE - BLOCK_LOGSIZE));
     localparam FIFO_DATA_WIDTH = 2 * `RASTER_DIM_BITS + 3 * `RASTER_DATA_BITS + LEVEL_BITS;

hw/rtl/rop_unit/VX_rop_agent.sv

@@ -14,6 +14,7 @@ module VX_rop_agent #(
     VX_commit_if.master   rop_commit_if,
     VX_rop_req_if.master  rop_req_if
 );
+    `UNUSED_PARAM (CORE_ID)
     
     localparam UUID_WIDTH = `UP(`UUID_BITS);
     localparam NW_WIDTH   = `UP(`NW_BITS);

hw/rtl/rop_unit/VX_rop_blend.sv

@@ -27,6 +27,8 @@ module VX_rop_blend #(
     // Output values
     output rgba_t [NUM_LANES-1:0] color_out
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
+
     localparam LATENCY = `LATENCY_IMUL + 1;
 
     `UNUSED_VAR (dcrs)

hw/rtl/rop_unit/VX_rop_csr.sv

@@ -12,6 +12,7 @@ module VX_rop_csr #(
     // Output
     output rop_csrs_t rop_csrs
 );
+    `UNUSED_PARAM (CORE_ID)
 
     // CSR registers
 

hw/rtl/rop_unit/VX_rop_dcr.sv

@@ -12,6 +12,7 @@ module VX_rop_dcr #(
     // Output
     output rop_dcrs_t       rop_dcrs
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
 
     `UNUSED_VAR (reset)
 

hw/rtl/rop_unit/VX_rop_ds.sv

@@ -31,6 +31,8 @@ module VX_rop_ds #(
     output wire [NUM_LANES-1:0][`ROP_STENCIL_BITS-1:0]  stencil_out,
     output wire [NUM_LANES-1:0]                         pass_out
 ); 
+    `UNUSED_SPARAM (INSTANCE_ID)
+
     `UNUSED_VAR (dcrs)
 
     wire stall = ~ready_out && valid_out;

hw/rtl/tex_unit/VX_tex_addr.sv

@@ -35,6 +35,7 @@ module VX_tex_addr #(
     output wire [REQ_INFOW-1:0]         rsp_info,  
     input wire                          rsp_ready
 );
+    `UNUSED_SPARAM (INSTANCE_ID)
 
     localparam SHIFT_BITS = $clog2(`TEX_FXD_FRAC+1);
     localparam PITCH_BITS = `MAX(`TEX_LOD_BITS, `TEX_LGSTRIDE_BITS) + 1;

hw/rtl/tex_unit/VX_tex_agent.sv

@@ -15,6 +15,7 @@ module VX_tex_agent #(
     VX_tex_req_if.master    tex_req_if,
     VX_commit_if.master     tex_commit_if
 );
+    `UNUSED_PARAM (CORE_ID)
 
     localparam UUID_WIDTH = `UP(`UUID_BITS);
     localparam NW_WIDTH   = `UP(`NW_BITS);

hw/rtl/tex_unit/VX_tex_csr.sv

@@ -12,6 +12,7 @@ module VX_tex_csr #(
     // Output
     output tex_csrs_t tex_csrs
 );
+    `UNUSED_PARAM (CORE_ID)
 
     // CSR registers
 

hw/rtl/tex_unit/VX_tex_dcr.sv

@@ -14,7 +14,8 @@ module VX_tex_dcr #(
     input wire [`TEX_STAGE_BITS-1:0]    stage,
     output tex_dcrs_t                   tex_dcrs
 );
-
+    `UNUSED_SPARAM (INSTANCE_ID)
+    
     `UNUSED_VAR (reset)
 
     // DCR registers

hw/rtl/tex_unit/VX_tex_sampler.sv

@@ -22,7 +22,8 @@ module VX_tex_sampler #(
     output wire [REQ_INFOW-1:0]         rsp_info,    
     input wire                          rsp_ready
 );   
-
+    `UNUSED_SPARAM (INSTANCE_ID)
+    
     wire valid_s0, valid_s1;
     wire [REQ_INFOW-1:0] req_info_s0, req_info_s1;
     wire [NUM_LANES-1:0][31:0] texel_ul, texel_uh;

hw/rtl/tex_unit/VX_tex_unit.sv

@@ -24,7 +24,8 @@ module VX_tex_unit #(
     // Outputs
     VX_tex_rsp_if.master    tex_rsp_if
 );
-
+    `UNUSED_SPARAM (INSTANCE_ID)
+    
     localparam BLEND_FRAC_W = (2 * NUM_LANES * `TEX_BLEND_FRAC);  
 
     // DCRs
@@ -387,4 +388,4 @@ module VX_tex_unit_top #(
         .cache_rsp_if (cache_rsp_if)
     );
 
-endmodule
+endmodule

sim/opaesim/opae_sim.cpp

@@ -394,7 +394,7 @@ private:
       unsigned byte_addr = device_->avs_address[b] * MEM_BLOCK_SIZE;
       if (device_->avs_write[b]) {           
         uint64_t byteen = device_->avs_byteenable[b];        
-        uint8_t* data = (uint8_t*)(device_->avs_writedata[b]);
+        uint8_t* data = (uint8_t*)(device_->avs_writedata[b].data());
         for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
           if ((byteen >> i) & 0x1) {            
             (*ram_)[byte_addr + i] = data[i];

sim/opaesim/verilator.vlt

@@ -8,4 +8,4 @@ lint_off -rule UNUSED -file "../../third_party/fpnew/*"
 lint_off -rule LITENDIAN -file "../../third_party/fpnew/*"
 lint_off -rule IMPORTSTAR -file "../../third_party/fpnew/*"
 lint_off -rule PINCONNECTEMPTY -file "../../third_party/fpnew/*"
-lint_off -file "../../third_party/fpnew/*"
+lint_off -file "../../third_party/fpnew/*"

sim/opaesim/vortex_afu_shim.sv

@@ -167,4 +167,4 @@ assign af2cp_sTxPort_c2_hdr_tid = af2cp_sTxPort.c2.hdr.tid;
 assign af2cp_sTxPort_c2_mmioRdValid = af2cp_sTxPort.c2.mmioRdValid;  
 assign af2cp_sTxPort_c2_data = af2cp_sTxPort.c2.data;
 
-endmodule
+endmodule

sim/rtlsim/processor.cpp

@@ -481,7 +481,7 @@ private:
           }
           printf("\n");
         */
-        memcpy((uint8_t*)device_->mem_rsp_data, mem_rsp->block.data(), MEM_BLOCK_SIZE);
+        memcpy(device_->mem_rsp_data.data(), mem_rsp->block.data(), MEM_BLOCK_SIZE);
         device_->mem_rsp_tag = mem_rsp->tag;   
         pending_mem_reqs_.erase(mem_rsp_it);
         mem_rd_rsp_active_ = true;
@@ -497,7 +497,7 @@ private:
       if (device_->mem_req_rw) {        
         // process writes
         uint64_t byteen = device_->mem_req_byteen;        
-        uint8_t* data = (uint8_t*)(device_->mem_req_data);
+        uint8_t* data = (uint8_t*)(device_->mem_req_data.data());
 
         // check console output
         if (byte_addr >= IO_COUT_ADDR 

sim/rtlsim/verilator.vlt

@@ -8,4 +8,4 @@ lint_off -rule UNUSED -file "../../third_party/fpnew/*"
 lint_off -rule LITENDIAN -file "../../third_party/fpnew/*"
 lint_off -rule IMPORTSTAR -file "../../third_party/fpnew/*"
 lint_off -rule PINCONNECTEMPTY -file "../../third_party/fpnew/*"
-lint_off -file "../../third_party/fpnew/*"
+lint_off -file "../../third_party/fpnew/*"