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minor update

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This commit is contained in:
Blaise Tine 2024-08-25 05:12:44 -07:00
parent bdcc5f5991
commit b40441b68f
1 changed files with 45 additions and 38 deletions
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83
hw/rtl/libs/VX_pe_serializer.sv
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@ -35,8 +35,8 @@ module VX_pe_serializer #(
// PE
output wire pe_enable,
output wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_in,
input wire [NUM_PES-1:0][DATA_OUT_WIDTH-1:0] pe_data_out,
output wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_out,
input wire [NUM_PES-1:0][DATA_OUT_WIDTH-1:0] pe_data_in,
// output
output wire valid_out,
@ -49,32 +49,44 @@ module VX_pe_serializer #(
wire [TAG_WIDTH-1:0] tag_out_u;
wire ready_out_u;
wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_in_s;
wire valid_out_s;
wire [TAG_WIDTH-1:0] tag_out_s;
wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_out_w;
wire pe_valid_in;
wire [TAG_WIDTH-1:0] pe_tag_in;
wire enable;
VX_shift_register #(
.DATAW (1 + TAG_WIDTH),
.DEPTH (LATENCY + PE_REG),
.DEPTH (PE_REG + LATENCY),
.RESETW (1)
) shift_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in ({valid_in, tag_in}),
.data_out ({valid_out_s, tag_out_s})
.data_in ({valid_in, tag_in}),
.data_out ({pe_valid_in, pe_tag_in})
);
VX_pipe_register #(
.DATAW (NUM_PES * DATA_IN_WIDTH),
.DEPTH (PE_REG)
) pe_reg (
.DATAW (NUM_PES * DATA_IN_WIDTH),
.DEPTH (PE_REG)
) pe_data_reg (
.clk (clk),
.reset (reset),
.enable (enable),
.data_in (pe_data_in_s),
.data_out (pe_data_in)
.data_in (pe_data_out_w),
.data_out (pe_data_out)
);
VX_pipe_register #(
.DATAW (1),
.RESETW (1),
.DEPTH (PE_REG)
) pe_en_reg (
.clk (clk),
.reset (reset),
.enable (1'b1),
.data_in (enable),
.data_out (pe_enable)
);
if (NUM_LANES != NUM_PES) begin
@ -82,35 +94,32 @@ module VX_pe_serializer #(
localparam BATCH_SIZE = NUM_LANES / NUM_PES;
localparam BATCH_SIZEW = `LOG2UP(BATCH_SIZE);
reg [BATCH_SIZEW-1:0] batch_in_idx;
reg [BATCH_SIZEW-1:0] batch_out_idx;
reg [BATCH_SIZEW-1:0] batch_in_idx, batch_out_idx;
reg batch_in_done, batch_out_done;
for (genvar i = 0; i < NUM_PES; ++i) begin
assign pe_data_in_s[i] = data_in[batch_in_idx * NUM_PES + i];
assign pe_data_out_w[i] = data_in[batch_in_idx * NUM_PES + i];
end
always @(posedge clk) begin
if (reset) begin
batch_in_idx <= '0;
batch_out_idx <= '0;
batch_in_idx <= '0;
batch_out_idx <= '0;
batch_in_done <= 0;
batch_out_done <= 0;
end else if (enable) begin
if (valid_in) begin
batch_in_idx <= batch_in_idx + BATCH_SIZEW'(1);
end
if (valid_out_s) begin
batch_out_idx <= batch_out_idx + BATCH_SIZEW'(1);
end
batch_in_idx <= batch_in_idx + BATCH_SIZEW'(valid_in);
batch_out_idx <= batch_out_idx + BATCH_SIZEW'(pe_valid_in);
batch_in_done <= valid_in && (batch_in_idx == BATCH_SIZEW'(BATCH_SIZE-2));
batch_out_done <= pe_valid_in && (batch_out_idx == BATCH_SIZEW'(BATCH_SIZE-2));
end
end
wire batch_in_done = (batch_in_idx == BATCH_SIZEW'(BATCH_SIZE-1));
wire batch_out_done = (batch_out_idx == BATCH_SIZEW'(BATCH_SIZE-1));
reg valid_out_r;
reg [BATCH_SIZE-1:0][NUM_PES-1:0][DATA_OUT_WIDTH-1:0] data_out_r;
reg [TAG_WIDTH-1:0] tag_out_r;
reg valid_out_r;
wire valid_out_b = valid_out_s && batch_out_done;
wire valid_out_b = pe_valid_in && batch_out_done;
wire ready_out_b = ready_out_u || ~valid_out_u;
always @(posedge clk) begin
@ -120,14 +129,13 @@ module VX_pe_serializer #(
valid_out_r <= valid_out_b;
end
if (ready_out_b) begin
data_out_r[batch_out_idx] <= pe_data_out;
tag_out_r <= tag_out_s;
data_out_r[batch_out_idx] <= pe_data_in;
tag_out_r <= pe_tag_in;
end
end
assign enable = ready_out_b || ~valid_out_b;
assign ready_in = enable && batch_in_done;
assign pe_enable = enable;
assign valid_out_u = valid_out_r;
assign data_out_u = data_out_r;
@ -135,15 +143,14 @@ module VX_pe_serializer #(
end else begin
assign pe_data_in_s = data_in;
assign pe_data_out_w = data_in;
assign enable = ready_out_u || ~valid_out_s;
assign enable = ready_out_u || ~pe_valid_in;
assign ready_in = enable;
assign pe_enable = enable;
assign valid_out_u = valid_out_s;
assign data_out_u = pe_data_out;
assign tag_out_u = tag_out_s;
assign valid_out_u = pe_valid_in;
assign data_out_u = pe_data_in;
assign tag_out_u = pe_tag_in;
end