regression fix

This commit is contained in:
Blaise Tine 2022-10-18 04:57:08 -04:00
parent 9e784cb83b
commit b6336ac7f0
7 changed files with 24 additions and 14 deletions

1
hw/.gitignore vendored
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@ -1 +0,0 @@
obj_dir/*

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@ -6,6 +6,7 @@
`define VIVADO
`define EXT_F_DISABLE
//`define EXT_GFX_ENABLE
`define STARTUP_ADDR 32'h80000
`define IO_BASE_ADDR 32'hFF000

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@ -71,7 +71,7 @@ JOBS := $(shell expr $(NCPUS) - 1)
VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem:HBM[0:15]
VPP_FLAGS += --report estimate
VPP_FLAGS += --report 2
VPP_FLAGS += --config ../vitis.ini
# Enable perf counters

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@ -72,7 +72,7 @@ JOBS := $(shell expr $(NCPUS) - 1)
VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem:HBM[0:15]
VPP_FLAGS += --report 2
VPP_FLAGS += --report_level 2
VPP_FLAGS += --config ../vitis.ini
# Enable perf counters

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@ -113,6 +113,17 @@ if { $chipscope == 1 } {
] [get_ips ila_lsu]
generate_target {instantiation_template} [get_files ila_lsu.xci]
set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_msched
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \
CONFIG.C_NUM_OF_PROBES {2} \
CONFIG.C_PROBE0_WIDTH {128} \
CONFIG.C_PROBE1_WIDTH {128} \
] [get_ips ila_msched]
generate_target {instantiation_template} [get_files ila_msched.xci]
set_property generate_synth_checkpoint false [get_files ila_msched.xci]
}
update_compile_order -fileset sources_1

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@ -166,10 +166,14 @@ public:
#endif
// start device
this->reset();
device_->reset = 0;
running_ = true;
// wait for busy to go Hi
while (!device_->busy) {
this->tick();
}
// execute program
while (device_->busy) {
if (get_ebreak()) {
@ -182,6 +186,9 @@ public:
// wait 5 cycles to flush the pipeline
this->wait(5);
// reset
this->reset();
return exitcode;
}
@ -216,15 +223,6 @@ private:
device_->reset = 1;
for (int i = 0; i < RESET_DELAY; ++i) {
device_->clk = 0;
this->eval();
device_->clk = 1;
this->eval();
}
device_->reset = 0;
for (int i = 0; i < RESET_DELAY; ++i) {
device_->clk = 0;
this->eval();

1
tests/.gitignore vendored Normal file
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@ -0,0 +1 @@
**/.run