Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit

hw/rtl/VX_csr_arb.v

@@ -1,6 +1,9 @@
 `include "VX_define.vh"
 
 module VX_csr_arb (    
+    input wire       clk,
+    input wire       reset,
+
     // bus select
     input wire       select_io_req,
     input wire       select_io_rsp,
@@ -19,6 +22,9 @@ module VX_csr_arb (
     VX_commit_if     csr_commit_if,
     VX_csr_io_rsp_if csr_io_rsp_if
 );
+    
+    VX_csr_io_rsp_if csr_io_rsp_tmp_if();
+
     // requests
     assign csr_req_if.valid     = (~select_io_req) ? csr_core_req_if.valid    : csr_io_req_if.valid;
     assign csr_req_if.wid       = (~select_io_req) ? csr_core_req_if.wid      : 0; 
@@ -35,8 +41,8 @@ module VX_csr_arb (
     assign csr_io_req_if.ready  = csr_req_if.ready && select_io_req;   
     
     // responses
-    assign csr_io_rsp_if.valid  = csr_rsp_if.valid & select_io_rsp;
-    assign csr_io_rsp_if.data   = csr_rsp_if.data[0];  
+    assign csr_io_rsp_tmp_if.valid = csr_rsp_if.valid & select_io_rsp;
+    assign csr_io_rsp_tmp_if.data  = csr_rsp_if.data[0];  
 
     assign csr_commit_if.valid  = csr_rsp_if.valid & ~select_io_rsp;
     assign csr_commit_if.wid    = csr_rsp_if.wid;    
@@ -46,6 +52,20 @@ module VX_csr_arb (
     assign csr_commit_if.wb     = csr_rsp_if.wb;
     assign csr_commit_if.data   = csr_rsp_if.data;
 
-    assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_if.ready : csr_commit_if.ready;
+    assign csr_rsp_if.ready = select_io_rsp ? csr_io_rsp_tmp_if.ready : csr_commit_if.ready;
+
+    // Use skid buffer on CSR IO bus to stop backpressure delay propagation
+    VX_elastic_buffer #(
+        .DATAW (32)
+    ) io_skid_buffer (
+        .clk       (clk),
+        .reset     (reset),
+        .valid_in  (csr_io_rsp_tmp_if.valid),
+        .ready_in  (csr_io_rsp_tmp_if.ready),
+        .data_in   (csr_io_rsp_tmp_if.data),
+        .data_out  (csr_io_rsp_if.data),
+        .valid_out (csr_io_rsp_if.valid),
+        .ready_out (csr_io_rsp_if.ready)
+    );
 
 endmodule

hw/rtl/VX_csr_unit.v

@@ -26,6 +26,9 @@ module VX_csr_unit #(
     wire select_io_rsp;
 
     VX_csr_arb csr_arb (
+        .clk              (clk),
+        .reset            (reset),
+        
         .select_io_req    (select_io_req),
         .select_io_rsp    (select_io_rsp),
 

hw/rtl/libs/VX_cam_buffer.v

@@ -7,13 +7,16 @@ module VX_cam_buffer #(
 ) (
     input  wire clk,
     input  wire reset,
+
     output wire [ADDRW-1:0] write_addr,
     input  wire [DATAW-1:0] write_data,            
     input  wire acquire_slot,
+
     input  wire [ADDRW-1:0] read_addr,
     output wire [DATAW-1:0] read_data,
     input  wire [ADDRW-1:0] release_addr,
     input  wire release_slot,
+    
     output wire full
 );
     reg [SIZE-1:0] free_slots, free_slots_n;

hw/rtl/libs/VX_countones.v

@@ -5,7 +5,7 @@ module VX_countones #(
     parameter N = 10,
     parameter N_BITS = $clog2(N+1)
 ) (
-    input wire [N-1:0]  valids,
+    input wire [N-1:0]       valids,
     output wire [N_BITS-1:0] count    
 );
     reg [N_BITS-1:0] count_r;

hw/rtl/libs/VX_divide.v

@@ -10,7 +10,7 @@ module VX_divide #(
     parameter LATENCY = 0
 ) (
     input wire clk,
-    input wire enable,
+    input wire enable, 
     input wire [WIDTHN-1:0] numer,
     input wire [WIDTHD-1:0] denom,
     output wire [WIDTHQ-1:0] quotient,

hw/rtl/libs/VX_elastic_buffer.v

@@ -3,28 +3,35 @@
 module VX_elastic_buffer #(
     parameter DATAW    = 1,
     parameter SIZE     = 2,
-    parameter BUFFERED = 0
+    parameter BUFFERED = 0,
+    parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
     input  wire             reset,
+
     input  wire             valid_in,
     output wire             ready_in,        
     input  wire [DATAW-1:0] data_in,
+    
     output wire [DATAW-1:0] data_out,
     input  wire             ready_out,
     output wire             valid_out
 ); 
     wire empty, full;
 
+    wire push = valid_in && ready_in;
+    wire pop  = valid_out && ready_out;
+
     VX_generic_queue #(
         .DATAW    (DATAW),
         .SIZE     (SIZE),
-        .BUFFERED (BUFFERED)
+        .BUFFERED (BUFFERED),
+        .FASTRAM  (FASTRAM)
     ) queue (
         .clk    (clk),
         .reset  (reset),
-        .push   (valid_in),
-        .pop    (ready_out),
+        .push   (push),
+        .pop    (pop),
         .data_in(data_in),
         .data_out(data_out),        
         .empty  (empty),

hw/rtl/libs/VX_generic_queue.v

@@ -9,7 +9,7 @@ module VX_generic_queue #(
     parameter FASTRAM  = 0
 ) ( 
     input  wire             clk,
-    input  wire             reset,
+    input  wire             reset,    
     input  wire             push,
     input  wire             pop,        
     input  wire [DATAW-1:0] data_in,