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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
9abccbfda5
commit
b8022822bb
3 changed files with 0 additions and 372 deletions
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@ -1,118 +0,0 @@
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`include "VX_define.vh"
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module VX_databus_arb (
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input wire clk,
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input wire reset,
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// input request
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VX_dcache_core_req_if core_req_if,
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// output requests
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VX_dcache_core_req_if cache_req_if,
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VX_dcache_core_req_if smem_req_if,
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// input responses
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VX_dcache_core_rsp_if cache_rsp_if,
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VX_dcache_core_rsp_if smem_rsp_if,
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// output response
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VX_dcache_core_rsp_if core_rsp_if
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);
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localparam SMEM_ASHIFT = `CLOG2(`SHARED_MEM_BASE_ADDR_ALIGN);
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localparam REQ_ASHIFT = `CLOG2(`DWORD_SIZE);
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localparam REQ_ADDRW = 32 - REQ_ASHIFT;
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localparam REQ_DATAW = REQ_ADDRW + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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localparam RSP_DATAW = `NUM_THREADS + `NUM_THREADS * (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH;
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//
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// handle requests
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//
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire cache_req_ready_in;
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wire smem_req_ready_in;
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// select shared memory bus
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wire is_smem_addr = core_req_if.valid[i] && `SM_ENABLE
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&& (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] >= (32-SMEM_ASHIFT)'((`SHARED_MEM_BASE_ADDR - `SMEM_SIZE) >> SMEM_ASHIFT))
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&& (core_req_if.addr[i][REQ_ADDRW-1:SMEM_ASHIFT-REQ_ASHIFT] < (32-SMEM_ASHIFT)'(`SHARED_MEM_BASE_ADDR >> SMEM_ASHIFT));
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VX_skid_buffer #(
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.DATAW (REQ_DATAW)
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) cache_out_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (core_req_if.valid[i] && !is_smem_addr),
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.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}),
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.ready_in (cache_req_ready_in),
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.valid_out (cache_req_if.valid[i]),
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.data_out ({cache_req_if.addr[i], cache_req_if.rw[i], cache_req_if.byteen[i], cache_req_if.data[i], cache_req_if.tag[i]}),
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.ready_out (cache_req_if.ready[i])
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);
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VX_skid_buffer #(
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.DATAW (REQ_DATAW)
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) smem_out_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (core_req_if.valid[i] && is_smem_addr),
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.data_in ({core_req_if.addr[i], core_req_if.rw[i], core_req_if.byteen[i], core_req_if.data[i], core_req_if.tag[i]}),
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.ready_in (smem_req_ready_in),
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.valid_out (smem_req_if.valid[i]),
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.data_out ({smem_req_if.addr[i], smem_req_if.rw[i], smem_req_if.byteen[i], smem_req_if.data[i], smem_req_if.tag[i]}),
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.ready_out (smem_req_if.ready[i])
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);
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assign core_req_if.ready[i] = is_smem_addr ? smem_req_ready_in : cache_req_ready_in;
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end
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//
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// handle responses
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//
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if (`SM_ENABLE ) begin
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wire [1:0][RSP_DATAW-1:0] rsp_data_in;
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wire [1:0] rsp_valid_in;
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wire [1:0] rsp_ready_in;
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wire core_rsp_valid;
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wire [`NUM_THREADS-1:0] core_rsp_valid_tmask;
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assign rsp_data_in[0] = {cache_rsp_if.valid, cache_rsp_if.data, cache_rsp_if.tag};
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assign rsp_data_in[1] = {smem_rsp_if.valid, smem_rsp_if.data, smem_rsp_if.tag};
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assign rsp_valid_in[0] = (| cache_rsp_if.valid);
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assign rsp_valid_in[1] = (| smem_rsp_if.valid) & `SM_ENABLE;
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VX_stream_arbiter #(
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.NUM_REQS (2),
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.DATAW (RSP_DATAW),
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.BUFFERED (0)
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) rsp_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (rsp_valid_in),
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.data_in (rsp_data_in),
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.ready_in (rsp_ready_in),
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.valid_out (core_rsp_valid),
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.data_out ({core_rsp_valid_tmask, core_rsp_if.data, core_rsp_if.tag}),
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.ready_out (core_rsp_if.ready)
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);
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assign cache_rsp_if.ready = rsp_ready_in[0];
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assign smem_rsp_if.ready = rsp_ready_in[1];
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assign core_rsp_if.valid = {`NUM_THREADS{core_rsp_valid}} & core_rsp_valid_tmask;
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end else begin
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assign core_rsp_if.valid = cache_rsp_if.valid;
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assign core_rsp_if.tag = cache_rsp_if.tag;
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assign core_rsp_if.data = cache_rsp_if.data;
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assign cache_rsp_if.ready = core_rsp_if.ready;
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end
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endmodule
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@ -1,118 +0,0 @@
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`include "VX_define.vh"
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module VX_mem_arb #(
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parameter NUM_REQS = 1,
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parameter DATA_WIDTH = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter BUFFERED_REQ = 0,
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parameter BUFFERED_RSP = 0,
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parameter DATA_SIZE = (DATA_WIDTH / 8),
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parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
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parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQS-1:0] req_valid_in,
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input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
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input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_in,
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input wire [NUM_REQS-1:0] req_rw_in,
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input wire [NUM_REQS-1:0][DATA_SIZE-1:0] req_byteen_in,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_in,
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output wire [NUM_REQS-1:0] req_ready_in,
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// output request
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output wire req_valid_out,
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output wire [TAG_OUT_WIDTH-1:0] req_tag_out,
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output wire [ADDR_WIDTH-1:0] req_addr_out,
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output wire req_rw_out,
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output wire [DATA_SIZE-1:0] req_byteen_out,
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output wire [DATA_WIDTH-1:0] req_data_out,
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input wire req_ready_out,
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// input response
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input wire rsp_valid_in,
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input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in,
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input wire [DATA_WIDTH-1:0] rsp_data_in,
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output wire rsp_ready_in,
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// output responses
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output wire [NUM_REQS-1:0] rsp_valid_out,
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output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out,
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input wire [NUM_REQS-1:0] rsp_ready_out
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);
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localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
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localparam RSP_DATAW = TAG_IN_WIDTH + DATA_WIDTH;
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if (NUM_REQS > 1) begin
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_in;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign req_merged_data_in[i] = {{req_tag_in[i], LOG_NUM_REQS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
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end
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VX_stream_arbiter #(
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.NUM_REQS (NUM_REQS),
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.DATAW (REQ_DATAW),
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.BUFFERED (BUFFERED_REQ)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (req_valid_in),
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.data_in (req_merged_data_in),
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.ready_in (req_ready_in),
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.valid_out (req_valid_out),
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.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
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.ready_out (req_ready_out)
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);
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///////////////////////////////////////////////////////////////////////
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wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in [LOG_NUM_REQS-1:0];
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_merged_data_out;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_merged_data_out[i];
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end
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VX_stream_demux #(
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.NUM_REQS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.BUFFERED (BUFFERED_RSP)
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) rsp_demux (
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.clk (clk),
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.reset (reset),
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.sel (rsp_sel),
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.valid_in (rsp_valid_in),
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.data_in ({rsp_tag_in[LOG_NUM_REQS +: TAG_IN_WIDTH], rsp_data_in}),
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.ready_in (rsp_ready_in),
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.valid_out (rsp_valid_out),
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.data_out (rsp_merged_data_out),
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.ready_out (rsp_ready_out)
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);
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_valid_out = req_valid_in;
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assign req_tag_out = req_tag_in;
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assign req_addr_out = req_addr_in;
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assign req_rw_out = req_rw_in;
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assign req_byteen_out = req_byteen_in;
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assign req_data_out = req_data_in;
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assign req_ready_in = req_ready_out;
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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end
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endmodule
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@ -1,136 +0,0 @@
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`include "VX_define.vh"
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module VX_dcache_arb #(
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parameter NUM_REQS = 1,
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parameter LANES = 1,
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parameter WORD_SIZE = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1
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parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQS-1:0][LANES-1:0] req_valid_in,
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input wire [NUM_REQS-1:0][LANES-1:0] req_rw_in,
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input wire [NUM_REQS-1:0][LANES-1:0][WORD_SIZE-1:0] req_byteen_in,
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input wire [NUM_REQS-1:0][LANES-1:0][`WORD_ADDR_WIDTH-1:0] req_addr_in,
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input wire [NUM_REQS-1:0][LANES-1:0][`WORD_WIDTH-1:0] req_data_in,
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input wire [NUM_REQS-1:0][LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
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output wire [NUM_REQS-1:0][LANES-1:0] req_ready_in,
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// output request
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output wire [LANES-1:0] req_valid_out,
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output wire [LANES-1:0] req_rw_out,
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output wire [LANES-1:0][WORD_SIZE-1:0] req_byteen_out,
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output wire [LANES-1:0][`WORD_ADDR_WIDTH-1:0] req_addr_out,
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output wire [LANES-1:0][`WORD_WIDTH-1:0] req_data_out,
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output wire [LANES-1:0][TAG_OUT_WIDTH-1:0] req_tag_out,
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input wire [LANES-1:0] req_ready_out,
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// input response
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input wire [LANES-1:0] rsp_valid_in,
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input wire [LANES-1:0][`WORD_WIDTH-1:0] rsp_data_in,
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input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in,
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output wire rsp_ready_in,
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// output responses
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output wire [NUM_REQS-1:0][LANES-1:0] rsp_valid_out,
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output wire [NUM_REQS-1:0][LANES-1:0][`WORD_WIDTH-1:0] rsp_data_out,
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output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out,
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input wire [NUM_REQS-1:0] rsp_ready_out
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);
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localparam REQ_DATAW = LANES * (1 + TAG_IN_WIDTH + `WORD_ADDR_WIDTH + 1 + WORD_SIZE + `WORD_WIDTH);
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localparam RSP_DATAW = LANES * `WORD_WIDTH + TAG_IN_WIDTH;
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if (NUM_REQS > 1) begin
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_in;
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wire [NUM_REQS-1:0] req_valid_in_any;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign req_merged_data_in[i] = {req_valid_in[i], req_tag_in[i], req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
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assign req_valid_in_any[i] = (| req_valid_in[i]);
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end
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wire sel_valid;
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wire [LOG_NUM_REQS-1:0] sel_idx;
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wire [NUM_REQS-1:0] sel_1hot;
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wire sel_enable = (| req_ready_out);
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VX_rr_arbiter #(
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.NUM_REQS(NUM_REQS),
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.LOCK_ENABLE(1)
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) sel_arb (
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.clk (clk),
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.reset (reset),
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.requests (req_valid_in_any),
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.enable (sel_enable),
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.grant_valid (sel_valid),
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.grant_index (sel_idx),
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.grant_onehot (sel_1hot)
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);
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wire [LANES-1:0] req_valid_out_unqual;
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wire [LANES-1:0][TAG_IN_WIDTH-1:0] req_tag_out_unqual;
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assign {req_valid_out_unqual, req_tag_out_unqual, req_addr_out, req_rw_out, req_byteen_out, req_data_out} = req_merged_data_in[sel_idx];
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assign req_valid_out = req_valid_out_unqual & {LANES{sel_valid}};
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for (genvar i = 0; i < LANES; i++) begin
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assign req_tag_out[i] = {req_tag_out_unqual[i], sel_idx};
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end
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign req_ready_in[i] = req_ready_out & {LANES{sel_1hot[i]}};
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end
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///////////////////////////////////////////////////////////////////////
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wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in [LOG_NUM_REQS-1:0];
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_merged_data_out;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_merged_data_out[i];
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end
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VX_stream_demux #(
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.NUM_REQS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.BUFFERED (BUFFERED_RSP)
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) rsp_demux (
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.clk (clk),
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.reset (reset),
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.sel (rsp_sel),
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.valid_in (rsp_valid_in),
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.data_in ({rsp_tag_in[LOG_NUM_REQS +: TAG_IN_WIDTH], rsp_data_in}),
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.ready_in (rsp_ready_in),
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.valid_out (rsp_valid_out),
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.data_out (rsp_merged_data_out),
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.ready_out (rsp_ready_out)
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);
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_valid_out = req_valid_in;
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assign req_tag_out = req_tag_in;
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assign req_addr_out = req_addr_in;
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assign req_rw_out = req_rw_in;
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assign req_byteen_out = req_byteen_in;
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assign req_data_out = req_data_in;
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assign req_ready_in = req_ready_out;
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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end
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endmodule
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