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minor update

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This commit is contained in:
Blaise Tine 2024-06-19 16:39:04 -07:00
parent 61df2ca428
commit b82a755e44
3 changed files with 18 additions and 18 deletions
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4
hw/rtl/VX_gpu_pkg.sv
View file

@ -241,8 +241,8 @@ package VX_gpu_pkg;
localparam ISSUE_ISW = `CLOG2(`ISSUE_WIDTH);
localparam ISSUE_ISW_W = `UP(ISSUE_ISW);
localparam ISSUE_RATIO = `NUM_WARPS / `ISSUE_WIDTH;
localparam ISSUE_WIS = `CLOG2(ISSUE_RATIO);
localparam PER_ISSUE_WARPS = `NUM_WARPS / `ISSUE_WIDTH;
localparam ISSUE_WIS = `CLOG2(PER_ISSUE_WARPS);
localparam ISSUE_WIS_W = `UP(ISSUE_WIS);
`IGNORE_UNUSED_BEGIN

22
hw/rtl/core/VX_gpr_slice.sv
View file

@ -26,7 +26,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
);
`UNUSED_PARAM (CORE_ID)
localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + `NR_BITS;
localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * ISSUE_RATIO);
localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * PER_ISSUE_WARPS);
localparam STATE_IDLE = 2'd0;
localparam STATE_FETCH1 = 2'd1;
@ -38,13 +38,13 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n;
reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n;
reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [ISSUE_RATIO-1:0];
reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [ISSUE_RATIO-1:0];
reg [`NR_BITS-1:0] cache_reg [ISSUE_RATIO-1:0];
reg [`NR_BITS-1:0] cache_reg_n [ISSUE_RATIO-1:0];
reg [`NUM_THREADS-1:0] cache_tmask [ISSUE_RATIO-1:0];
reg [`NUM_THREADS-1:0] cache_tmask_n [ISSUE_RATIO-1:0];
reg [ISSUE_RATIO-1:0] cache_eop, cache_eop_n;
reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [PER_ISSUE_WARPS-1:0];
reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [PER_ISSUE_WARPS-1:0];
reg [`NR_BITS-1:0] cache_reg [PER_ISSUE_WARPS-1:0];
reg [`NR_BITS-1:0] cache_reg_n [PER_ISSUE_WARPS-1:0];
reg [`NUM_THREADS-1:0] cache_tmask [PER_ISSUE_WARPS-1:0];
reg [`NUM_THREADS-1:0] cache_tmask_n [PER_ISSUE_WARPS-1:0];
reg [PER_ISSUE_WARPS-1:0] cache_eop, cache_eop_n;
reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
@ -155,7 +155,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
if (CACHE_ENABLE != 0 && writeback_if.valid) begin
if ((cache_reg[writeback_if.data.wis] == writeback_if.data.rd)
|| (cache_eop[writeback_if.data.wis] && writeback_if.data.sop)) begin
|| (cache_eop[writeback_if.data.wis] && writeback_if.data.sop)) begin
for (integer j = 0; j < `NUM_THREADS; ++j) begin
if (writeback_if.data.tmask[j]) begin
cache_data_n[writeback_if.data.wis][j] = writeback_if.data.data[j];
@ -172,7 +172,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
always @(posedge clk) begin
if (reset) begin
state <= STATE_IDLE;
cache_eop <= {ISSUE_RATIO{1'b1}};
cache_eop <= {PER_ISSUE_WARPS{1'b1}};
data_ready <= 0;
end else begin
state <= state_n;
@ -261,7 +261,7 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
for (genvar j = 0; j < `NUM_THREADS; ++j) begin
VX_dp_ram #(
.DATAW (`XLEN),
.SIZE (`NUM_REGS * ISSUE_RATIO),
.SIZE (`NUM_REGS * PER_ISSUE_WARPS),
`ifdef GPR_RESET
.INIT_ENABLE (1),
.INIT_VALUE (0),

10
hw/rtl/core/VX_scoreboard.sv
View file

@ -291,11 +291,11 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
`RESET_RELAY (arb_reset, reset);
for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
wire [ISSUE_RATIO-1:0] valid_in;
wire [ISSUE_RATIO-1:0][DATAW-1:0] data_in;
wire [ISSUE_RATIO-1:0] ready_in;
wire [PER_ISSUE_WARPS-1:0] valid_in;
wire [PER_ISSUE_WARPS-1:0][DATAW-1:0] data_in;
wire [PER_ISSUE_WARPS-1:0] ready_in;
for (genvar j = 0; j < ISSUE_RATIO; ++j) begin
for (genvar j = 0; j < PER_ISSUE_WARPS; ++j) begin
wire operands_ready = ~(| staging_opds_busy[j * `ISSUE_WIDTH + i]);
assign valid_in[j] = staging_if[j * `ISSUE_WIDTH + i].valid && operands_ready;
assign data_in[j] = staging_if[j * `ISSUE_WIDTH + i].data;
@ -303,7 +303,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
end
VX_stream_arb #(
.NUM_INPUTS (ISSUE_RATIO),
.NUM_INPUTS (PER_ISSUE_WARPS),
.DATAW (DATAW),
.ARBITER ("R"),
.OUT_BUF (2)