Merge branch 'develop' of https://github.com/vortexgpgpu/vortex into develop

.travis.yml

@@ -37,8 +37,8 @@ jobs:
       script:
         - rm -rf $HOME/build32 && cp -r $PWD $HOME/build32
         - rm -rf $HOME/build64 && cp -r $PWD $HOME/build64
-        - make -C $HOME/build32
-        - XLEN=64 make -C $HOME/build64
+        - make -C $HOME/build32 > /dev/null
+        - XLEN=64 make -C $HOME/build64 > /dev/null
     - stage: test 
       name: unittest
       script: cp -r $HOME/build32 build && cd build && ./ci/travis_run.py ./ci/regression.sh --unittest

README.md

@@ -35,7 +35,7 @@ Vortex is a full-stack open-source RISC-V GPGPU.
 ## Build Instructions
 More detailed build instructions can be found [here](docs/install_vortex.md).
 ### Supported OS Platforms
-- Ubuntu 18.04
+- Ubuntu 18.04, 20.04
 - Centos 7
 ### Toolchain Dependencies
 - [POCL](http://portablecl.org/)

RELEASE

@@ -1,4 +0,0 @@
-
-Release Notes!
-
-* 07/01/2020 - LKG FPGA build - Passed basic, demo, vecadd kernels.

TODO

@@ -1,23 +0,0 @@
-
-
-
-Functionality:
-1) vx_cl_warpSpawn()
-   -> To be used by pocl->ops->run
-
-2) newlib Integration (LoadFile(""))
-   -> To be used by the Rhinio benchmarks
-
-3) POCL OPS Vortex Suite
-
-Performance:
-1) Icache doesn't need SEND_MEM_REQUEST Stage
-   -> Blocks are never dirty, so why not evict right away 
-
-2) Branch not taken speculation
-
-3) Runtime -02 not running on RTL, and -03 not running on RTL and Emulator
-
-
-Vector:
-1) Cycle accurate simulator (would require Cache Simulator)

ci/regression.sh

@@ -22,7 +22,7 @@ rm -f blackbox.*.cache
 unittest() 
 {
 make -C tests/unittest run
-make -C hw/unittest
+make -C hw/unittest > /dev/null
 }
 
 isa() 
@@ -31,33 +31,36 @@ echo "begin isa tests..."
 
 make -C tests/riscv/isa run-simx
 make -C tests/riscv/isa run-rtlsim
-CONFIGS="-DDPI_DISABLE" make -C tests/riscv/isa run-rtlsim
 
-make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim
+make -C sim/rtlsim clean && CONFIGS="-DDPI_DISABLE" make -C sim/rtlsim > /dev/null
+make -C tests/riscv/isa run-rtlsim
+
+make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim > /dev/null
 make -C tests/riscv/isa run-rtlsim-32f
 
-make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim
+make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim > /dev/null
 make -C tests/riscv/isa run-rtlsim-32f
 
-make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim
+make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim > /dev/null
 make -C tests/riscv/isa run-rtlsim-32f
 
 if [ "$XLEN" == "64" ]
 then
-        make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim
+        make -C sim/rtlsim clean && CONFIGS="-DFPU_FPNEW" make -C sim/rtlsim > /dev/null
         make -C tests/riscv/isa run-rtlsim-64f
 
-        make -C sim/rtlsim clean && CONFIGS="-DEXT_D_ENABLE -DFPU_FPNEW" make -C sim/rtlsim
+        make -C sim/rtlsim clean && CONFIGS="-DEXT_D_ENABLE -DFPU_FPNEW" make -C sim/rtlsim > /dev/null
         make -C tests/riscv/isa run-rtlsim-64d || true
 
-        make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim
+        make -C sim/rtlsim clean && CONFIGS="-DFPU_DPI" make -C sim/rtlsim > /dev/null
         make -C tests/riscv/isa run-rtlsim-64f
 
-        make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim
+        make -C sim/rtlsim clean && CONFIGS="-DFPU_DSP" make -C sim/rtlsim > /dev/null
         make -C tests/riscv/isa run-rtlsim-64fx
 fi
 
-make -C sim/rtlsim clean && make -C sim/rtlsim
+# restore default prebuilt configuration
+make -C sim/rtlsim clean && make -C sim/rtlsim > /dev/null
 
 echo "isa tests done!"
 }
@@ -134,15 +137,16 @@ debug()
 echo "begin debugging tests..."
 
 # test CSV trace generation
-make -C sim/simx clean && DEBUG=3 make -C sim/simx
-make -C sim/rtlsim clean && DEBUG=3 CONFIGS="-DGPR_RESET" make -C sim/rtlsim
+make -C sim/simx clean && DEBUG=3 make -C sim/simx > /dev/null
+make -C sim/rtlsim clean && DEBUG=3 CONFIGS="-DGPR_RESET" make -C sim/rtlsim > /dev/null
 make -C tests/riscv/isa run-simx-32im > run_simx.log
 make -C tests/riscv/isa run-rtlsim-32im > run_rtlsim.log
 ./ci/trace_csv.py -trtlsim run_rtlsim.log -otrace_rtlsim.csv
 ./ci/trace_csv.py -tsimx run_simx.log -otrace_simx.csv
 diff trace_rtlsim.csv trace_simx.csv
-make -C sim/simx clean && make -C sim/simx
-make -C sim/rtlsim clean && make -C sim/rtlsim
+# restore default prebuilt configuration
+make -C sim/simx clean && make -C sim/simx > /dev/null
+make -C sim/rtlsim clean && make -C sim/rtlsim > /dev/null
 
 ./ci/blackbox.sh --driver=opae --cores=2 --clusters=2 --l2cache --perf=1 --app=demo --args="-n1"
 ./ci/blackbox.sh --driver=simx --cores=2 --clusters=2 --l2cache --perf=1 --app=demo --args="-n1"

ci/travis_run.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python
 
-# Copyright © 2019-2023
-# 
+# Copyright 2019-2023
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
@@ -34,11 +34,11 @@ def monitor(stop):
             break
 
 def execute(command):
-    process = subprocess.Popen(command, stdout=subprocess.PIPE)
+    process = subprocess.Popen(command, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
     while True:
         output = process.stdout.readline()
         if output:
-            line = output.decode('ascii').rstrip()
+            line = output.decode('utf-8').rstrip()
             print(">>> " + line)
             process.stdout.flush()
         ret = process.poll()