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https://github.com/vortexgpgpu/vortex.git
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duplicate load addresses optimization
This commit is contained in:
Blaise Tine
parent
ea2b73d5b0
commit
ba743678dc
2 changed files with 47 additions and 26 deletions
10
.travis.yml
10
.travis.yml
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@ -25,12 +25,12 @@ script:
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- ./ci/test_riscv_isa.sh
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- ./ci/test_opencl.sh
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- ./ci/test_driver.sh
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --debug
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1"
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1"
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=demo --args="-n1"
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
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- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
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after_success:
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# Gather code coverage
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@ -31,6 +31,7 @@ module VX_lsu_unit #(
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wire req_wb;
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wire [`NW_BITS-1:0] req_wid;
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wire [31:0] req_pc;
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wire req_is_dup;
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wire [`NUM_THREADS-1:0][31:0] full_address;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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@ -67,6 +68,13 @@ module VX_lsu_unit #(
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assign mem_req_data[i] = lsu_req_if.store_data[i] << {full_address[i][1:0], 3'b0};
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end
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reg [`NUM_THREADS-2:0] addr_matches;
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always @(*) begin
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for (integer i = 1; i < `NUM_THREADS; i++) begin
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addr_matches[i-1] = (mem_req_addr[0] == mem_req_addr[i]) || ~lsu_req_if.tmask[i];
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end
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end
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`IGNORE_WARNINGS_BEGIN
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wire [`NUM_THREADS-1:0][31:0] req_address;
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reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH-1:0] pending_tags;
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@ -76,14 +84,14 @@ module VX_lsu_unit #(
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wire stall_in = ~ready_in & req_valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
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.DATAW (1 + 1 + `NW_BITS + `NUM_THREADS + 32 + 1 + `NR_BITS + 1 + (`NUM_THREADS * 32) + 2 + (`NUM_THREADS * (30 + 2 + 4 + 32))),
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.RESETW (1)
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) req_pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall_in),
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.data_in ({lsu_req_if.valid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}),
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.data_out ({req_valid, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data})
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.data_in ({lsu_req_if.valid, (& addr_matches), lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.rw, lsu_req_if.rd, lsu_req_if.wb, full_address, mem_req_sext, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data}),
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.data_out ({req_valid, req_is_dup, req_wid, req_tmask, req_pc, req_rw, req_rd, req_wb, req_address, req_sext, req_addr, req_offset, req_byteen, req_data})
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);
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// Can accept new request?
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@ -95,10 +103,12 @@ module VX_lsu_unit #(
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][1:0] rsp_offset;
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wire [1:0] rsp_sext;
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reg [`NUM_THREADS-1:0][31:0] rsp_data;
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wire rsp_is_dup;
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reg [`LSUQ_SIZE-1:0][`NUM_THREADS-1:0] rsp_rem_mask;
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reg [`NUM_THREADS-1:0] req_sent_mask, rsp_rem_mask_n;
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reg [`NUM_THREADS-1:0] rsp_rem_mask_n;
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reg [`NUM_THREADS-1:0] req_sent_mask;
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wire req_sent_all;
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wire [`DCORE_TAG_ID_BITS-1:0] mbuf_waddr, mbuf_raddr;
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@ -110,12 +120,12 @@ module VX_lsu_unit #(
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wire mbuf_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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wire mbuf_pop = mbuf_pop_part && (0 == rsp_rem_mask_n);
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wire mbuf_pop = mbuf_pop_part && (rsp_rem_mask_n == 0 || rsp_is_dup);
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assign mbuf_raddr = dcache_rsp_if.tag[0][`DCORE_TAG_ID_BITS-1:0];
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VX_index_buffer #(
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.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 2) + 2),
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.DATAW (`NW_BITS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 2) + 2 + 1),
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.SIZE (`LSUQ_SIZE),
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.FASTRAM (1)
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) req_metadata (
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@ -124,14 +134,16 @@ module VX_lsu_unit #(
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.write_addr (mbuf_waddr),
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.acquire_slot (mbuf_push),
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.read_addr (mbuf_raddr),
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.write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext}),
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.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_offset, rsp_sext}),
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.write_data ({req_wid, req_pc, req_rd, req_wb, req_offset, req_sext, req_is_dup}),
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.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_offset, rsp_sext, rsp_is_dup}),
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.release_addr (mbuf_raddr),
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.release_slot (mbuf_pop),
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.full (mbuf_full)
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);
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assign req_sent_all = ((dcache_req_if.ready | req_sent_mask) & req_tmask) == req_tmask;
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assign req_sent_all = (((dcache_req_if.ready | req_sent_mask) & req_tmask) == req_tmask)
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|| req_is_dup;
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always @(posedge clk) begin
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if (reset) begin
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req_sent_mask <= 0;
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@ -164,8 +176,10 @@ module VX_lsu_unit #(
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wire req_ready_dep = (!req_rw && !mbuf_full) || (req_rw && st_commit_if.ready);
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wire [`NUM_THREADS-1:0] dup_mask = {{(`NUM_THREADS-1){~req_is_dup}}, 1'b1};
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// Core Request
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assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_ready_dep}} & req_tmask & ~req_sent_mask;
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assign dcache_req_if.valid = {`NUM_THREADS{req_valid && req_ready_dep}} & req_tmask & dup_mask & ~req_sent_mask;
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assign dcache_req_if.rw = {`NUM_THREADS{req_rw}};
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assign dcache_req_if.byteen = req_byteen;
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assign dcache_req_if.addr = req_addr;
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@ -179,9 +193,14 @@ module VX_lsu_unit #(
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assign ready_in = req_ready_dep && req_sent_all;
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// Core Response
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] rsp_data_shifted = dcache_rsp_if.data[i] >> {rsp_offset[i], 3'b0};
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// load response formatting
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reg [`NUM_THREADS-1:0][31:0] rsp_data;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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wire [31:0] src_data = (i == 0 || rsp_is_dup) ? dcache_rsp_if.data[0] : dcache_rsp_if.data[i];
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wire [31:0] rsp_data_shifted = src_data >> {rsp_offset[i], 3'b0};
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always @(*) begin
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case (rsp_sext)
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1: rsp_data[i] = {{24{rsp_data_shifted[7]}}, rsp_data_shifted[7:0]};
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@ -191,6 +210,8 @@ module VX_lsu_unit #(
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end
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end
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wire [`NUM_THREADS-1:0] rsp_tmask = rsp_is_dup ? rsp_rem_mask[mbuf_raddr] : dcache_rsp_if.valid;
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// send store commit
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wire is_store_rsp = req_valid && req_rw && req_sent_all;
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@ -217,7 +238,7 @@ module VX_lsu_unit #(
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.clk (clk),
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.reset (reset),
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.enable (!load_rsp_stall),
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.data_in ({is_load_rsp, rsp_wid, dcache_rsp_if.valid, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}),
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.data_in ({is_load_rsp, rsp_wid, rsp_tmask, rsp_pc, rsp_rd, rsp_wb, rsp_data, mbuf_pop}),
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.data_out ({ld_commit_if.valid, ld_commit_if.wid, ld_commit_if.tmask, ld_commit_if.PC, ld_commit_if.rd, ld_commit_if.wb, ld_commit_if.data, ld_commit_if.eop})
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);
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@ -238,18 +259,18 @@ module VX_lsu_unit #(
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifdef DBG_PRINT_CORE_DCACHE
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (| (dcache_req_if.valid & dcache_req_if.ready)) begin
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if (dcache_req_if.rw[0])
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$display("%t: D$%0d Wr Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, data=%0h",
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$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, dcache_req_if.data);
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else
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$display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d",
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$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, req_rd);
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$display("%t: D$%0d Rd Req: wid=%0d, PC=%0h, tmask=%b, addr=%0h, tag=%0h, byteen=%0h, rd=%0d, is_dup=%b",
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$time, CORE_ID, req_wid, req_pc, (dcache_req_if.valid & dcache_req_if.ready), req_address, dcache_req_if.tag, dcache_req_if.byteen, req_rd, req_is_dup);
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end
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if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
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$display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h",
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$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data);
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$display("%t: D$%0d Rsp: valid=%b, wid=%0d, PC=%0h, tag=%0h, rd=%0d, data=%0h, is_dup=%b",
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$time, CORE_ID, dcache_rsp_if.valid, rsp_wid, rsp_pc, dcache_rsp_if.tag, rsp_rd, dcache_rsp_if.data, rsp_is_dup);
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end
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if (mbuf_full) begin
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$write("%t: D$%0d queue-full:", $time, CORE_ID);
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