mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
CSRs update
This commit is contained in:
Blaise Tine
parent
c8bae13448
commit
badfb24e01
6 changed files with 61 additions and 51 deletions
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@ -91,7 +91,7 @@
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`endif
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`ifndef NUM_BARRIERS
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`define NUM_BARRIERS 4
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`define NUM_BARRIERS (`NUM_WARPS/2)
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`endif
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`ifndef SOCKET_SIZE
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -32,7 +32,7 @@
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// Machine Performance-monitoring counters classes ////////////////////////////
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`define VX_DCR_MPM_CLASS_NONE 0
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`define VX_DCR_MPM_CLASS_NONE 0
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`define VX_DCR_MPM_CLASS_CORE 1
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`define VX_DCR_MPM_CLASS_MEM 2
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@ -41,7 +41,7 @@
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`define VX_CSR_FFLAGS 12'h001
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`define VX_CSR_FRM 12'h002
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`define VX_CSR_FCSR 12'h003
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`define VX_CSR_SATP 12'h180
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`define VX_CSR_PMPCFG0 12'h3A0
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@ -101,7 +101,7 @@
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`define VX_CSR_MPM_STORES_H 12'hB8D
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`define VX_CSR_MPM_IFETCH_LT 12'hB0E
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`define VX_CSR_MPM_IFETCH_LT_H 12'hB8E
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`define VX_CSR_MPM_LOAD_LT 12'hB0F
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`define VX_CSR_MPM_LOAD_LT 12'hB0F
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`define VX_CSR_MPM_LOAD_LT_H 12'hB8F
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// SFU: scoreboard
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`define VX_CSR_MPM_SCRB_WCTL 12'hB10
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@ -187,11 +187,12 @@
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`define VX_CSR_THREAD_ID 12'hCC0
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`define VX_CSR_WARP_ID 12'hCC1
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`define VX_CSR_CORE_ID 12'hCC2
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`define VX_CSR_WARP_MASK 12'hCC3
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`define VX_CSR_THREAD_MASK 12'hCC4 // warning! this value is also used in LLVM
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`define VX_CSR_ACTIVE_WARPS 12'hCC3
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`define VX_CSR_ACTIVE_THREADS 12'hCC4 // warning! this value is also used in LLVM
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`define VX_CSR_NUM_THREADS 12'hFC0
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`define VX_CSR_NUM_WARPS 12'hFC1
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`define VX_CSR_NUM_CORES 12'hFC2
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`define VX_CSR_NUM_BARRIERS 12'hFC3
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`endif // VX_TYPES_VH
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -62,7 +62,7 @@ import VX_fpu_pkg::*;
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output wire [`XLEN-1:0] read_data_ro,
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output wire [`XLEN-1:0] read_data_rw,
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input wire write_enable,
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input wire write_enable,
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input wire [`UUID_WIDTH-1:0] write_uuid,
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input wire [`NW_WIDTH-1:0] write_wid,
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input wire [`VX_CSR_ADDR_BITS-1:0] write_addr,
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@ -77,7 +77,7 @@ import VX_fpu_pkg::*;
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reg [`XLEN-1:0] mscratch;
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`ifdef EXT_F_ENABLE
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`ifdef EXT_F_ENABLE
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reg [`NUM_WARPS-1:0][`INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr, fcsr_n;
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wire [`NUM_FPU_BLOCKS-1:0] fpu_write_enable;
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wire [`NUM_FPU_BLOCKS-1:0][`NW_WIDTH-1:0] fpu_write_wid;
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@ -88,7 +88,7 @@ import VX_fpu_pkg::*;
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assign fpu_write_wid[i] = fpu_csr_if[i].write_wid;
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assign fpu_write_fflags[i] = fpu_csr_if[i].write_fflags;
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end
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always @(*) begin
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fcsr_n = fcsr;
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for (integer i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
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@ -96,7 +96,7 @@ import VX_fpu_pkg::*;
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fcsr_n[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] = fcsr[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0]
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| fpu_write_fflags[i];
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end
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end
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end
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if (write_enable) begin
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case (write_addr)
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`VX_CSR_FFLAGS: fcsr_n[write_wid][`FP_FLAGS_BITS-1:0] = write_data[`FP_FLAGS_BITS-1:0];
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@ -106,7 +106,7 @@ import VX_fpu_pkg::*;
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endcase
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end
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end
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for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin
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assign fpu_csr_if[i].read_frm = fcsr[fpu_csr_if[i].read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS];
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end
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@ -146,7 +146,7 @@ import VX_fpu_pkg::*;
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`VX_CSR_MSCRATCH: begin
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mscratch <= write_data;
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end
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default: begin
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default: begin
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`ASSERT(0, ("%t: *** invalid CSR write address: %0h (#%0d)", $time, write_addr, write_uuid));
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end
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endcase
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@ -163,7 +163,7 @@ import VX_fpu_pkg::*;
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read_data_ro_r = '0;
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read_data_rw_r = '0;
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read_addr_valid_r = 1;
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case (read_addr)
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case (read_addr)
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`VX_CSR_MVENDORID : read_data_ro_r = `XLEN'(`VENDOR_ID);
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`VX_CSR_MARCHID : read_data_ro_r = `XLEN'(`ARCHITECTURE_ID);
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`VX_CSR_MIMPID : read_data_ro_r = `XLEN'(`IMPLEMENTATION_ID);
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@ -171,25 +171,26 @@ import VX_fpu_pkg::*;
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`ifdef EXT_F_ENABLE
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`VX_CSR_FFLAGS : read_data_rw_r = `XLEN'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
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`VX_CSR_FRM : read_data_rw_r = `XLEN'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
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`VX_CSR_FCSR : read_data_rw_r = `XLEN'(fcsr[read_wid]);
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`VX_CSR_FCSR : read_data_rw_r = `XLEN'(fcsr[read_wid]);
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`endif
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`VX_CSR_MSCRATCH : read_data_rw_r = mscratch;
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`VX_CSR_WARP_ID : read_data_ro_r = `XLEN'(read_wid);
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`VX_CSR_CORE_ID : read_data_ro_r = `XLEN'(CORE_ID);
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`VX_CSR_THREAD_MASK: read_data_ro_r = `XLEN'(thread_masks[read_wid]);
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`VX_CSR_WARP_MASK : read_data_ro_r = `XLEN'(active_warps);
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`VX_CSR_ACTIVE_THREADS: read_data_ro_r = `XLEN'(thread_masks[read_wid]);
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`VX_CSR_ACTIVE_WARPS: read_data_ro_r = `XLEN'(active_warps);
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`VX_CSR_NUM_THREADS: read_data_ro_r = `XLEN'(`NUM_THREADS);
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`VX_CSR_NUM_WARPS : read_data_ro_r = `XLEN'(`NUM_WARPS);
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`VX_CSR_NUM_CORES : read_data_ro_r = `XLEN'(`NUM_CORES * `NUM_CLUSTERS);
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`VX_CSR_NUM_BARRIERS: read_data_ro_r = `XLEN'(`NUM_BARRIERS);
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`CSR_READ_64(`VX_CSR_MCYCLE, read_data_ro_r, cycles);
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`VX_CSR_MPM_RESERVED : read_data_ro_r = 'x;
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`VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x;
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`CSR_READ_64(`VX_CSR_MINSTRET, read_data_ro_r, commit_csr_if.instret);
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`VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x;
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`CSR_READ_64(`VX_CSR_MINSTRET, read_data_ro_r, commit_csr_if.instret);
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`VX_CSR_SATP,
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`VX_CSR_MSTATUS,
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`VX_CSR_MNSTATUS,
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@ -210,7 +211,7 @@ import VX_fpu_pkg::*;
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case (base_dcrs.mpm_class)
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`VX_DCR_MPM_CLASS_CORE: begin
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case (read_addr)
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// PERF: pipeline
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// PERF: pipeline
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`CSR_READ_64(`VX_CSR_MPM_SCHED_ID, read_data_ro_r, pipeline_perf_if.sched_idles);
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`CSR_READ_64(`VX_CSR_MPM_SCHED_ST, read_data_ro_r, pipeline_perf_if.sched_stalls);
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`CSR_READ_64(`VX_CSR_MPM_IBUF_ST, read_data_ro_r, pipeline_perf_if.ibf_stalls);
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@ -231,7 +232,7 @@ import VX_fpu_pkg::*;
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`CSR_READ_64(`VX_CSR_MPM_LOADS, read_data_ro_r, pipeline_perf_if.loads);
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`CSR_READ_64(`VX_CSR_MPM_STORES, read_data_ro_r, pipeline_perf_if.stores);
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`CSR_READ_64(`VX_CSR_MPM_IFETCH_LT, read_data_ro_r, pipeline_perf_if.ifetch_latency);
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`CSR_READ_64(`VX_CSR_MPM_LOAD_LT, read_data_ro_r, pipeline_perf_if.load_latency);
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`CSR_READ_64(`VX_CSR_MPM_LOAD_LT, read_data_ro_r, pipeline_perf_if.load_latency);
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default:;
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endcase
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end
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@ -248,17 +249,17 @@ import VX_fpu_pkg::*;
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`CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_W, read_data_ro_r, mem_perf_if.dcache.write_misses);
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`CSR_READ_64(`VX_CSR_MPM_DCACHE_BANK_ST, read_data_ro_r, mem_perf_if.dcache.bank_stalls);
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`CSR_READ_64(`VX_CSR_MPM_DCACHE_MSHR_ST, read_data_ro_r, mem_perf_if.dcache.mshr_stalls);
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// PERF: lmem
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// PERF: lmem
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`CSR_READ_64(`VX_CSR_MPM_LMEM_READS, read_data_ro_r, mem_perf_if.lmem.reads);
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`CSR_READ_64(`VX_CSR_MPM_LMEM_WRITES, read_data_ro_r, mem_perf_if.lmem.writes);
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`CSR_READ_64(`VX_CSR_MPM_LMEM_BANK_ST, read_data_ro_r, mem_perf_if.lmem.bank_stalls);
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// PERF: l2cache
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// PERF: l2cache
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_READS, read_data_ro_r, mem_perf_if.l2cache.reads);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_WRITES, read_data_ro_r, mem_perf_if.l2cache.writes);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_R, read_data_ro_r, mem_perf_if.l2cache.read_misses);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_W, read_data_ro_r, mem_perf_if.l2cache.write_misses);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_BANK_ST, read_data_ro_r, mem_perf_if.l2cache.bank_stalls);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MSHR_ST, read_data_ro_r, mem_perf_if.l2cache.mshr_stalls);
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`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MSHR_ST, read_data_ro_r, mem_perf_if.l2cache.mshr_stalls);
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// PERF: l3cache
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`CSR_READ_64(`VX_CSR_MPM_L3CACHE_READS, read_data_ro_r, mem_perf_if.l3cache.reads);
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`CSR_READ_64(`VX_CSR_MPM_L3CACHE_WRITES, read_data_ro_r, mem_perf_if.l3cache.writes);
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@ -178,17 +178,17 @@ inline int vx_core_id() {
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return ret;
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}
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// Return current thread mask
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inline int vx_thread_mask() {
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// Return active threads mask
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inline int vx_active_threads() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_THREAD_MASK));
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_ACTIVE_THREADS));
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return ret;
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}
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// Return active warps mask
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inline int vx_warp_mask() {
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inline int vx_active_warps() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_WARP_MASK));
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_ACTIVE_WARPS));
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return ret;
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}
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@ -213,6 +213,13 @@ inline int vx_num_cores() {
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return ret;
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}
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// Return the number of barriers
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inline int vx_num_barriers() {
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int ret;
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asm volatile ("csrr %0, %1" : "=r"(ret) : "i"(VX_CSR_NUM_BARRIERS));
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return ret;
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}
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// Return the hart identifier (thread id accross the processor)
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inline int vx_hart_id() {
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int ret;
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@ -358,11 +358,12 @@ Word Emulator::get_csr(uint32_t addr, uint32_t tid, uint32_t wid) {
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case VX_CSR_THREAD_ID: return tid;
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case VX_CSR_WARP_ID: return wid;
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case VX_CSR_CORE_ID: return core_->id();
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case VX_CSR_THREAD_MASK:return warps_.at(wid).tmask.to_ulong();
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case VX_CSR_WARP_MASK: return active_warps_.to_ulong();
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case VX_CSR_ACTIVE_THREADS:return warps_.at(wid).tmask.to_ulong();
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case VX_CSR_ACTIVE_WARPS:return active_warps_.to_ulong();
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case VX_CSR_NUM_THREADS:return arch_.num_threads();
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case VX_CSR_NUM_WARPS: return arch_.num_warps();
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case VX_CSR_NUM_CORES: return uint32_t(arch_.num_cores()) * arch_.num_clusters();
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case VX_CSR_NUM_BARRIERS:return arch_.num_barriers();
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case VX_CSR_MSCRATCH: return csr_mscratch_;
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CSR_READ_64(VX_CSR_MCYCLE, core_perf.cycles);
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CSR_READ_64(VX_CSR_MINSTRET, core_perf.instrs);
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@ -65,7 +65,7 @@ int test_local_memory() {
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int num_threads = std::min(vx_num_threads(), 8);
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int tmask = make_full_tmask(num_threads);
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vx_tmc(tmask);
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vx_tmc(tmask);
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do_lmem_wr();
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do_lmem_rd();
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vx_tmc_one();
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@ -87,7 +87,7 @@ int test_tmc() {
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int num_threads = std::min(vx_num_threads(), 8);
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int tmask = make_full_tmask(num_threads);
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vx_tmc(tmask);
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vx_tmc(tmask);
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do_tmc();
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vx_tmc_one();
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@ -146,7 +146,7 @@ int dvg_buffer[4];
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void __attribute__((noinline)) __attribute__((optimize("O1"))) do_divergence() {
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int tid = vx_thread_id();
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int cond1 = tid < 2;
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int sp1 = vx_split(cond1);
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int sp1 = vx_split(cond1);
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if (cond1) {
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{
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int cond2 = tid < 1;
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@ -244,9 +244,9 @@ void __attribute__((noinline)) do_serial() {
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}
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int test_serial() {
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PRINTF("Serial Test\n");
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PRINTF("Serial Test\n");
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int num_threads = std::min(vx_num_threads(), 8);
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int tmask = make_full_tmask(num_threads);
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int tmask = make_full_tmask(num_threads);
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vx_tmc(tmask);
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do_serial();
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vx_tmc_one();
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@ -258,10 +258,10 @@ int test_serial() {
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int tmask_buffer[8];
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int __attribute__((noinline)) do_tmask() {
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int __attribute__((noinline)) do_tmask() {
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int tid = vx_thread_id();
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int tmask = make_select_tmask(tid);
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int cur_tmask = vx_thread_mask();
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int cur_tmask = vx_active_threads();
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tmask_buffer[tid] = (cur_tmask == tmask) ? (65 + tid) : 0;
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return tid + 1;
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}
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@ -275,11 +275,11 @@ int test_tmask() {
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int num_threads = std::min(vx_num_threads(), 8);
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int tid = 0;
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l_start:
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l_start:
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int tmask = make_select_tmask(tid);
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vx_tmc(tmask);
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tid = do_tmask();
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if (tid < num_threads)
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vx_tmc(tmask);
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tid = do_tmask();
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if (tid < num_threads)
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goto l_start;
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vx_tmc_one();
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|
||||
|
|
@ -296,7 +296,7 @@ void barrier_kernel() {
|
|||
unsigned wid = vx_warp_id();
|
||||
for (int i = 0; i <= (wid * 256); ++i) {
|
||||
++barrier_stall;
|
||||
}
|
||||
}
|
||||
barrier_buffer[wid] = 65 + wid;
|
||||
vx_barrier(0, barrier_ctr);
|
||||
vx_tmc(0 == wid);
|
||||
|
|
@ -308,7 +308,7 @@ int test_barrier() {
|
|||
barrier_ctr = num_warps;
|
||||
barrier_stall = 0;
|
||||
vx_wspawn(num_warps, barrier_kernel);
|
||||
barrier_kernel();
|
||||
barrier_kernel();
|
||||
return check_error(barrier_buffer, 0, num_warps);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue