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minor updates

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This commit is contained in:
Blaise Tine 2022-07-31 10:10:59 -07:00
parent a645b5909e
commit bb2853e0c8
12 changed files with 42 additions and 31 deletions
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2
hw/afu/opae/vortex_afu.sv
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@ -49,7 +49,7 @@ localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8;
localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE); localparam CCI_ADDR_WIDTH = 32 - $clog2(CCI_DATA_SIZE);
localparam AVS_RD_QUEUE_SIZE = 64; localparam AVS_RD_QUEUE_SIZE = 32;
localparam _VX_MEM_TAG_WIDTH = `VX_MEM_TAG_WIDTH; localparam _VX_MEM_TAG_WIDTH = `VX_MEM_TAG_WIDTH;
localparam _AVS_REQ_TAGW_VX = _VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH); localparam _AVS_REQ_TAGW_VX = _VX_MEM_TAG_WIDTH + $clog2(LMEM_DATA_WIDTH) - $clog2(`VX_MEM_DATA_WIDTH);
localparam _AVS_REQ_TAGW_VX2 = `MAX(_VX_MEM_TAG_WIDTH, _AVS_REQ_TAGW_VX); localparam _AVS_REQ_TAGW_VX2 = `MAX(_VX_MEM_TAG_WIDTH, _AVS_REQ_TAGW_VX);

10
hw/rtl/VX_config.vh
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@ -471,7 +471,7 @@
// Miss Handling Register Size // Miss Handling Register Size
`ifndef DCACHE_MSHR_SIZE `ifndef DCACHE_MSHR_SIZE
`define DCACHE_MSHR_SIZE 32 `define DCACHE_MSHR_SIZE 16
`endif `endif
// Memory Request Queue Size // Memory Request Queue Size
@ -562,7 +562,7 @@
// Miss Handling Register Size // Miss Handling Register Size
`ifndef TCACHE_MSHR_SIZE `ifndef TCACHE_MSHR_SIZE
`define TCACHE_MSHR_SIZE 32 `define TCACHE_MSHR_SIZE 16
`endif `endif
// Memory Request Queue Size // Memory Request Queue Size
@ -690,7 +690,7 @@
// Miss Handling Register Size // Miss Handling Register Size
`ifndef OCACHE_MSHR_SIZE `ifndef OCACHE_MSHR_SIZE
`define OCACHE_MSHR_SIZE 32 `define OCACHE_MSHR_SIZE 16
`endif `endif
// Memory Request Queue Size // Memory Request Queue Size
@ -741,7 +741,7 @@
// Miss Handling Register Size // Miss Handling Register Size
`ifndef L2_MSHR_SIZE `ifndef L2_MSHR_SIZE
`define L2_MSHR_SIZE 64 `define L2_MSHR_SIZE 16
`endif `endif
// Memory Request Queue Size // Memory Request Queue Size
@ -792,7 +792,7 @@
// Miss Handling Register Size // Miss Handling Register Size
`ifndef L3_MSHR_SIZE `ifndef L3_MSHR_SIZE
`define L3_MSHR_SIZE 64 `define L3_MSHR_SIZE 16
`endif `endif
// Memory Request Queue Size // Memory Request Queue Size

2
hw/rtl/VX_core.sv
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@ -1,8 +1,10 @@
`include "VX_define.vh" `include "VX_define.vh"
`include "VX_gpu_types.vh" `include "VX_gpu_types.vh"
`include "VX_cache_types.vh"
`IGNORE_WARNINGS_BEGIN `IGNORE_WARNINGS_BEGIN
import VX_gpu_types::*; import VX_gpu_types::*;
import VX_cache_types::*;
`IGNORE_WARNINGS_END `IGNORE_WARNINGS_END
module VX_core #( module VX_core #(

21
hw/rtl/Vortex.sv
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@ -53,8 +53,7 @@ module Vortex (
`ifdef PERF_ENABLE `ifdef PERF_ENABLE
VX_perf_memsys_if perf_memsys_if[`NUM_CLUSTERS](); VX_perf_memsys_if perf_memsys_if[`NUM_CLUSTERS]();
VX_perf_memsys_if perf_memsys_total_if(); VX_perf_memsys_if perf_memsys_total_if();
VX_perf_cache_if perf_l3cache_if(); VX_perf_cache_if perf_l3cache_if();
`PERF_MEMSYS_ADD (perf_memsys_total_if, perf_memsys_if, `NUM_CLUSTERS);
`endif `endif
VX_mem_req_if #( VX_mem_req_if #(
@ -239,6 +238,24 @@ module Vortex (
`ifdef PERF_ENABLE `ifdef PERF_ENABLE
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, icache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, icache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, dcache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, smem_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_reads, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_writes, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_read_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_write_misses, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_bank_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`REDUCE_ADD (perf_memsys_total_if, perf_memsys_if, l2cache_mshr_stalls, `PERF_CTR_BITS, `NUM_CLUSTERS);
`ifdef L3_ENABLE `ifdef L3_ENABLE
assign perf_memsys_total_if.l3cache_reads = perf_l3cache_if.reads; assign perf_memsys_total_if.l3cache_reads = perf_l3cache_if.reads;
assign perf_memsys_total_if.l3cache_writes = perf_l3cache_if.writes; assign perf_memsys_total_if.l3cache_writes = perf_l3cache_if.writes;

1
hw/rtl/cache/VX_cache.sv vendored
View file

@ -545,7 +545,6 @@ module VX_cache #(
// per cycle: core_reads, core_writes // per cycle: core_reads, core_writes
wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; wire [$clog2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle;
wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; wire [$clog2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle;
wire [$clog2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle;
wire [NUM_REQS-1:0] perf_core_reads_per_req = core_req_valid & core_req_ready & ~core_req_rw; wire [NUM_REQS-1:0] perf_core_reads_per_req = core_req_valid & core_req_ready & ~core_req_rw;
wire [NUM_REQS-1:0] perf_core_writes_per_req = core_req_valid & core_req_ready & core_req_rw; wire [NUM_REQS-1:0] perf_core_writes_per_req = core_req_valid & core_req_ready & core_req_rw;

22
hw/rtl/cache/VX_cache_define.vh vendored
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@ -112,26 +112,4 @@
`REDUCE_ADD (dst, src, mem_stalls, `PERF_CTR_BITS, count); \ `REDUCE_ADD (dst, src, mem_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, crsp_stalls, `PERF_CTR_BITS, count) `REDUCE_ADD (dst, src, crsp_stalls, `PERF_CTR_BITS, count)
`define PERF_MEMSYS_ADD(dst, src, count) \
`REDUCE_ADD (dst, src, icache_reads, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, icache_read_misses, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_reads, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_writes, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_read_misses, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_write_misses, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_bank_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, dcache_mshr_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, smem_reads, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, smem_writes, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, smem_bank_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_reads, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_writes, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_read_misses, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_write_misses, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_bank_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, l2cache_mshr_stalls, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, mem_reads, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, mem_writes, `PERF_CTR_BITS, count); \
`REDUCE_ADD (dst, src, mem_latency, `PERF_CTR_BITS, count)
`endif `endif

5
hw/rtl/raster_unit/VX_raster_unit.sv
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@ -1,4 +1,9 @@
`include "VX_raster_define.vh" `include "VX_raster_define.vh"
`include "VX_cache_types.vh"
`IGNORE_WARNINGS_BEGIN
import VX_cache_types::*;
`IGNORE_WARNINGS_END
module VX_raster_unit #( module VX_raster_unit #(
parameter string INSTANCE_ID = "", parameter string INSTANCE_ID = "",

5
hw/rtl/rop_unit/VX_rop_unit.sv
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@ -1,4 +1,9 @@
`include "VX_rop_define.vh" `include "VX_rop_define.vh"
`include "VX_cache_types.vh"
`IGNORE_WARNINGS_BEGIN
import VX_cache_types::*;
`IGNORE_WARNINGS_END
module VX_rop_unit #( module VX_rop_unit #(
parameter string INSTANCE_ID = "", parameter string INSTANCE_ID = "",

5
hw/rtl/tex_unit/VX_tex_unit.sv
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@ -1,4 +1,9 @@
`include "VX_tex_define.vh" `include "VX_tex_define.vh"
`include "VX_cache_types.vh"
`IGNORE_WARNINGS_BEGIN
import VX_cache_types::*;
`IGNORE_WARNINGS_END
module VX_tex_unit #( module VX_tex_unit #(
parameter string INSTANCE_ID = "", parameter string INSTANCE_ID = "",

0
perf/cache/perf.sh → perf/cache/run.sh vendored
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0
perf/draw3d/perf.sh → perf/draw3d/run.sh
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0
perf/rop/perf.sh → perf/rop/run.sh
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