bug fixes

hw/rtl/core/VX_operands.sv

@@ -51,18 +51,16 @@ module VX_operands import VX_gpu_pkg::*; #(
     reg [`NUM_OPCS-1:0] select_opcs;
     always @(*) begin
         select_opcs = '1;
-        // SFU cannot handle multiple inflight WCTL instructions, should use same collector
-        if (`NUM_OPCS > 1 && SIMD_COUNT > 1
-         && scoreboard_if.data.ex_type == EX_SFU
-         && inst_sfu_is_wctl(scoreboard_if.data.op_type)) begin
+        // LSU cannot handle out of order LD/ST instructions: use same collector
+        if (`NUM_OPCS > 1 && scoreboard_if.data.ex_type == EX_LSU) begin
             // select collector 0
             for (int i = 0; i < `NUM_OPCS; ++i) begin
                 if (i != 0) select_opcs[i] = 0;
             end
         end
-        // LSU cannot handle out of order LD/ST instructions, should use same collector
-        if (`NUM_OPCS > 1
-         && scoreboard_if.data.ex_type == EX_LSU) begin
+        // SFU cannot handle multiple inflight WCTL instructions
+        // CSR access should be ordered as well: use same collector
+        if (`NUM_OPCS > 1 && scoreboard_if.data.ex_type == EX_SFU) begin
             // select collector 1
             for (int i = 0; i < `NUM_OPCS; ++i) begin
                 if (i != 1) select_opcs[i] = 0;

hw/rtl/core/VX_schedule.sv

@@ -52,9 +52,9 @@ module VX_schedule import VX_gpu_pkg::*; #(
     reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, thread_masks_n;
     reg [`NUM_WARPS-1:0][PC_BITS-1:0] warp_pcs, warp_pcs_n;
 
-    wire [NW_WIDTH-1:0]    schedule_wid;
+    wire [NW_WIDTH-1:0]     schedule_wid;
     wire [`NUM_THREADS-1:0] schedule_tmask;
-    wire [PC_BITS-1:0]     schedule_pc;
+    wire [PC_BITS-1:0]      schedule_pc;
     wire                    schedule_valid;
     wire                    schedule_ready;
 
@@ -62,9 +62,9 @@ module VX_schedule import VX_gpu_pkg::*; #(
     wire                    join_valid;
     wire                    join_is_dvg;
     wire                    join_is_else;
-    wire [NW_WIDTH-1:0]    join_wid;
+    wire [NW_WIDTH-1:0]     join_wid;
     wire [`NUM_THREADS-1:0] join_tmask;
-    wire [PC_BITS-1:0]     join_pc;
+    wire [PC_BITS-1:0]      join_pc;
 
     reg [PERF_CTR_BITS-1:0] cycles;