mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
minor opae hw fixed
This commit is contained in:
Blaise Tine
parent
6463cca529
commit
bc6b2969ef
3 changed files with 62 additions and 12 deletions
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@ -281,7 +281,6 @@ begin
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avs_writedata <= 0;
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avs_read <= 0;
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avs_write <= 0;
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avs_read_ctr <= 0;
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avs_write_ctr <= 0;
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end
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@ -323,9 +322,7 @@ begin
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STATE_RUN: begin
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if (vx_dram_req_read
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&& !avs_waitrequest
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&& !avs_raq_full
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&& !avs_rdq_full)
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&& !vx_dram_req_delay)
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begin
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avs_address <= (vx_dram_req_addr >> 6);
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avs_read <= 1;
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@ -333,7 +330,7 @@ begin
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end
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if (vx_dram_req_write
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&& !avs_waitrequest)
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&& !vx_dram_req_delay)
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begin
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avs_writedata <= {>>{vx_dram_req_data}};
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avs_address <= (vx_dram_req_addr >> 6);
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@ -351,7 +348,10 @@ begin
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end
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// Vortex DRAM requests stalling
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assign vx_dram_req_delay = !(avs_read || avs_write);
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assign vx_dram_req_delay = !((STATE_RUN == state)
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&& !avs_waitrequest
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&& !avs_raq_full
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&& !avs_rdq_full);
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// Vortex DRAM fill response
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always_comb
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@ -369,7 +369,7 @@ always_comb
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begin
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avs_raq_pop = vx_dram_fill_rsp || cci_write_req;
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avs_raq_din = avs_address;
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avs_raq_push = avs_write;
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avs_raq_push = avs_read;
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end
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VX_generic_queue_ll #(
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@ -463,10 +463,10 @@ logic cci_write_pending;
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always_comb
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begin
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cci_write_req = (STATE_READ == state)
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_pending
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&& cci_write_ctr < csr_data_size;
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&& !avs_rdq_empty
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&& !cp2af_sRxPort.c1TxAlmFull
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&& !cci_write_pending
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&& cci_write_ctr < csr_data_size;
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wr_hdr = t_ccip_c1_ReqMemHdr'(0);
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wr_hdr.address = csr_io_addr + cci_write_ctr;
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50
driver/hw/wave.do
Normal file
50
driver/hw/wave.do
Normal file
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@ -0,0 +1,50 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -label clk /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/clk
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add wave -noupdate -label reset /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/SoftReset
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add wave -noupdate -label state /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/state
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add wave -noupdate -label cci_write_pending /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_pending
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add wave -noupdate -label cci_write_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_ctr
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add wave -noupdate -label csr_data_size -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/csr_data_size
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add wave -noupdate -label avs_read_ctr -radix decimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read_ctr
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add wave -noupdate -label avs_waitrequest /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_waitrequest
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add wave -noupdate -label avs_address -radix hexadecimal -radixshowbase 0 /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_address
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add wave -noupdate -label avs_readdata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdata
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add wave -noupdate -label avs_writedata -radix hexadecimal /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_writedata
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add wave -noupdate -label avs_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_write
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add wave -noupdate -label avs_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_read
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add wave -noupdate -label avs_readdatavalid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_readdatavalid
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add wave -noupdate -label sRx.c0.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c0.rspValid
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add wave -noupdate -label sRx.c1.rspValid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cp2af_sRxPort.c1.rspValid
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add wave -noupdate -label sTx.c0.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c0.valid
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add wave -noupdate -label sTx.c1.valid /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/af2cp_sTxPort.c1.valid
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add wave -noupdate -label cci_write_req /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/cci_write_req
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add wave -noupdate -label avs_raq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_push
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add wave -noupdate -label avs_rdq_push /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_push
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add wave -noupdate -label avs_raq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_pop
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add wave -noupdate -label avs_rdq_pop /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_pop
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add wave -noupdate -label avs_raq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_full
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add wave -noupdate -label avs_rdq_full /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_full
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add wave -noupdate -label avs_raq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_raq_empty
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add wave -noupdate -label avs_rdq_empty /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/avs_rdq_empty
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add wave -noupdate -label vx_dram_req_write /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_write
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add wave -noupdate -label vx_dram_req_delay /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_delay
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add wave -noupdate -label vx_dram_req_read /ase_top/ase_top_generic/platform_shim_ccip_std_afu/ccip_std_afu/vortex_afu_inst/vx_dram_req_read
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {77894400 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 195
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ps
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update
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WaveRestoreZoom {77712056 ps} {78076744 ps}
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@ -18,7 +18,7 @@ run-fpga: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/opae:$(LD_LIBRARY_PATH) ./$(PROJECT)
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run-ase: $(PROJECT)
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ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT)
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ASE_LOG=0 LD_LIBRARY_PATH=../../sw/opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -t 1
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run-rtlsim: $(PROJECT)
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LD_LIBRARY_PATH=../../sw/rtlsim:$(LD_LIBRARY_PATH) ./$(PROJECT)
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