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Debugged issue with active_l

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Rishabh Ravi 2025-01-10 14:23:54 -05:00
parent 4046d5f687
commit be0270203b
1 changed files with 1 additions and 1 deletions
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hw/rtl/core/VX_alu_int.sv
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@ -146,7 +146,7 @@ module VX_alu_int #(
wire [NUM_LANES-1:0][`XLEN-1:0] maxLane, minLane;
reg [NUM_LANES-1:0][`XLEN-1:0] lane;
reg [NUM_LANES-1:0] p;
wire [NUM_LANES-1:0] active_l;
reg [NUM_LANES-1:0] active_l;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign b[i] = (alu_in2_imm[i]>>5)&(`XLEN'(5'b11111));