adding RTL uuigen

hw/dpi/util_dpi.cpp

@@ -47,8 +47,6 @@ extern "C" {
   void dpi_trace(int level, const char* format, ...);
   void dpi_trace_start();
   void dpi_trace_stop();
-
-  uint64_t dpi_uuid_gen(bool reset, int wid);
 }
 
 bool sim_trace_enabled();
@@ -204,17 +202,3 @@ void dpi_trace_start() {
 void dpi_trace_stop() {
   sim_trace_enable(false);
 }
-
-///////////////////////////////////////////////////////////////////////////////
-
-std::unordered_map<uint32_t, uint32_t> g_uuid_gens;
-
-uint64_t dpi_uuid_gen(bool reset, int wid) {
-  if (reset) {
-    g_uuid_gens.clear();
-    return 0;
-  }
-  uint32_t instr_uuid = g_uuid_gens[wid]++;
-  uint64_t uuid = (uint64_t(wid) << 32) | instr_uuid;
-  return uuid;
-}

hw/dpi/util_dpi.vh

@@ -30,6 +30,4 @@ import "DPI-C" function void dpi_trace(input int level, input string format /*ve
 import "DPI-C" function void dpi_trace_start();
 import "DPI-C" function void dpi_trace_stop();
 
-import "DPI-C" function longint dpi_uuid_gen(input logic reset, input int wid);
-
 `endif

hw/rtl/core/VX_schedule.sv

@@ -331,30 +331,23 @@ module VX_schedule import VX_gpu_pkg::*; #(
         schedule_data[schedule_wid][(`NUM_THREADS + `PC_BITS)-5:0]
     };
 
+    wire [`UUID_WIDTH-1:0] instr_uuid;
 `ifndef NDEBUG
-    localparam GNW_WIDTH = `LOG2UP(`NUM_CLUSTERS * `NUM_CORES * `NUM_WARPS);
+    VX_uuid_gen #(
-    reg [`UUID_WIDTH-1:0] instr_uuid;
+        .CORE_ID (CORE_ID)
-    wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << `NW_BITS) + GNW_WIDTH'(schedule_wid);
+    ) uuid_gen (
-`ifdef SV_DPI
+        .clk   (clk),
-    always @(posedge clk) begin
+        .reset (reset),
-        if (reset) begin
+        .incr  (schedule_fire),
-            instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(1, 32'd0));
+        .wid   (schedule_wid),
-        end else if (schedule_fire) begin
+        .uuid  (instr_uuid)
-            instr_uuid <= `UUID_WIDTH'(dpi_uuid_gen(0, 32'(g_wid)));
+    );
-        end
-    end
 `else
-    wire [GNW_WIDTH+16-1:0] w_uuid = {g_wid, 16'(schedule_pc)};
+    assign instr_uuid = '0;
-    always @(*) begin
-        instr_uuid = `UUID_WIDTH'(w_uuid);
-    end
-`endif
-`else
-    wire [`UUID_WIDTH-1:0] instr_uuid = '0;
 `endif
 
     VX_elastic_buffer #(
-        .DATAW (`NUM_THREADS + `PC_BITS + `NW_WIDTH),
+        .DATAW (`NUM_THREADS + `PC_BITS + `NW_WIDTH + `UUID_WIDTH),
         .SIZE  (2),  // need to buffer out ready_in
         .OUT_REG (1) // should be registered for BRAM acces in fetch unit
     ) out_buf (
@@ -362,14 +355,12 @@ module VX_schedule import VX_gpu_pkg::*; #(
         .reset     (reset),
         .valid_in  (schedule_valid),
         .ready_in  (schedule_ready),
-        .data_in   ({schedule_tmask, schedule_pc, schedule_wid}),
+        .data_in   ({schedule_tmask, schedule_pc, schedule_wid, instr_uuid}),
-        .data_out  ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid}),
+        .data_out  ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.uuid}),
         .valid_out (schedule_if.valid),
         .ready_out (schedule_if.ready)
     );
 
-    assign schedule_if.data.uuid = instr_uuid;
-
     // Track pending instructions per warp
 
     wire [`NUM_WARPS-1:0] pending_warp_empty;

hw/rtl/core/VX_uuid_gen.sv

@@ -0,0 +1,43 @@
+// Copyright © 2019-2023
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "VX_define.vh"
+
+module VX_uuid_gen import VX_gpu_pkg::*; #(
+    parameter CORE_ID = 0
+) (
+    input wire clk,
+    input wire reset,
+    input wire incr,
+    input wire [`NW_WIDTH-1:0] wid,
+    output wire [`UUID_WIDTH-1:0] uuid
+);
+    localparam GNW_WIDTH = `UUID_WIDTH - 32;
+    reg [31:0] uuid_cntrs [0:`NUM_WARPS-1];
+    reg [`NUM_WARPS-1:0] has_uuid_cntrs;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            has_uuid_cntrs <= '0;
+        end else if (incr) begin
+            has_uuid_cntrs[wid] <= 1;
+        end
+        if (incr) begin
+            uuid_cntrs[wid] <= has_uuid_cntrs[wid] ? (uuid_cntrs[wid] + 1) : 1;
+        end
+    end
+
+    wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << `NW_BITS) + GNW_WIDTH'(wid);
+    assign uuid = {g_wid, (has_uuid_cntrs[wid] ? uuid_cntrs[wid] : 0)};
+
+endmodule