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minor updates

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This commit is contained in:
Blaise Tine 2022-07-06 01:05:20 -04:00
parent fa6daabe35
commit c2643a66dd
6 changed files with 168 additions and 281 deletions
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20
ci/regression.sh
View file

@ -210,18 +210,18 @@ AXI_BUS=1 ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo
CONFIGS="-DL1_BLOCK_SIZE=64" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr --args="-n1"
# test cache banking
CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim
CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx
CONFIGS="-DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr
CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr
CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=io_addr
CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=sgemm
CONFIGS="-DSMEM_NUM_BANKS=2 -DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=sgemm
CONFIGS="-DDCACHE_NUM_BANKS=1" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm
CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm
CONFIGS="-DDCACHE_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=sgemm
# test cache multi-porting
CONFIGS="-DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=io_addr
CONFIGS="-DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=demo --debug=1 --args="-n1"
CONFIGS="-DL2_NUM_PORTS=2 -DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=io_addr
CONFIGS="-DDCACHE_NUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=4 --l2cache --app=io_addr
CONFIGS="-DDCACHE_NUM_PORTS=4" ./ci/blackbox.sh --driver=simx --cores=4 --l2cache --app=io_addr
CONFIGS="-DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm
CONFIGS="-DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=simx --cores=1 --app=sgemm
CONFIGS="-DDCACHE_NUM_PORTS=4" ./ci/blackbox.sh --driver=rtlsim --cores=1 --app=sgemm
CONFIGS="-DL2_NUM_PORTS=2 -DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=sgemm
CONFIGS="-DL2_NUM_PORTS=2 -DDCACHE_NUM_PORTS=2" ./ci/blackbox.sh --driver=simx --cores=2 --l2cache --app=sgemm
# test 128-bit MEM block
CONFIGS=-DMEM_BLOCK_SIZE=16 ./ci/blackbox.sh --driver=vlsim --cores=1 --app=demo

330
hw/rtl/cache/VX_req_dispatch.sv vendored
View file

@ -55,11 +55,10 @@ module VX_req_dispatch #(
`STATIC_ASSERT(NUM_PORTS <= WORDS_PER_LINE, ("invalid parameter"))
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
`UNUSED_VAR (reset)
wire [NUM_REQS-1:0][LINE_ADDR_WIDTH-1:0] core_req_line_addr;
wire [NUM_REQS-1:0][`UP(WORD_SEL_BITS)-1:0] core_req_wsel;
wire [NUM_REQS-1:0][`UP(BANK_SEL_BITS)-1:0] core_req_bid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (WORDS_PER_LINE > 1) begin
@ -67,223 +66,138 @@ module VX_req_dispatch #(
end else begin
assign core_req_wsel[i] = 0;
end
if (NUM_BANKS > 1) begin
assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
end else begin
assign core_req_bid[i] = 0;
end
assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH];
end
reg [NUM_BANKS-1:0] per_bank_core_req_valid_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(WORD_SEL_BITS)-1:0] per_bank_core_req_wsel_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_WIDTH-1:0] per_bank_core_req_data_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(REQ_SEL_BITS)-1:0] per_bank_core_req_idx_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][TAG_WIDTH-1:0] per_bank_core_req_tag_r;
reg [NUM_BANKS-1:0] per_bank_core_req_rw_r;
reg [NUM_BANKS-1:0][LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
reg [NUM_REQS-1:0] core_req_ready_r;
if ((NUM_BANKS > 1) || (NUM_PORTS > 1)) begin
if (NUM_REQS > 1) begin
if (NUM_PORTS > 1) begin
reg [NUM_BANKS-1:0][LINE_ADDR_WIDTH-1:0] per_bank_line_addr_r;
reg [NUM_BANKS-1:0] per_bank_rw_r;
wire [NUM_REQS-1:0] core_req_line_match;
always @(*) begin
per_bank_line_addr_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i];
per_bank_rw_r[core_req_bid[i]] = core_req_rw[i];
end
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_line_match[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]])
&& (core_req_rw[i] == per_bank_rw_r[core_req_bid[i]]);
end
if (NUM_PORTS < NUM_REQS) begin
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][NUM_REQS-1:0] req_select_table_r;
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_pmask_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_data_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_idx_r = 'x;
req_select_table_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i];
per_bank_core_req_idx_r[core_req_bid[i]][i % NUM_PORTS] = `UP(REQ_SEL_BITS)'(i);
per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i];
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i];
req_select_table_r[core_req_bid[i]][i % NUM_PORTS] = (1 << i);
end
end
end
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]]
&& core_req_line_match[i]
&& req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i];
end
end
end else begin
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_pmask_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_data_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_idx_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i];
per_bank_core_req_idx_r[core_req_bid[i]][i % NUM_PORTS] = `UP(REQ_SEL_BITS)'(i);
per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i];
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i];
end
end
end
always @(*) begin
for (integer i = 0; i < NUM_REQS; ++i) begin
core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]]
&& core_req_line_match[i];
end
end
end
end else begin
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_data_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_idx_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i];
per_bank_core_req_wsel_r[core_req_bid[i]] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]]= core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]] = core_req_data[i];
per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i];
per_bank_core_req_idx_r[core_req_bid[i]] = `UP(REQ_SEL_BITS)'(i);
end
end
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
end
wire [NUM_REQS-1:0][`UP(BANK_SEL_BITS)-1:0] core_req_bid;
for (genvar i = 0; i < NUM_REQS; ++i) begin
if (NUM_BANKS > 1) begin
always @(*) begin
core_req_ready_r = 0;
for (integer i = 0; i < NUM_BANKS; ++i) begin
if (per_bank_core_req_valid_r[i]) begin
core_req_ready_r[per_bank_core_req_idx_r[i]] = per_bank_core_req_ready[i];
end
end
end
assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS];
end else begin
always @(*) begin
core_req_ready_r = 0;
core_req_ready_r[per_bank_core_req_idx_r[0]] = per_bank_core_req_ready;
end
end
end
end else begin
if (NUM_BANKS > 1) begin
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_data_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_idx_r = 'x;
per_bank_core_req_valid_r[core_req_bid[0]] = core_req_valid;
per_bank_core_req_rw_r[core_req_bid[0]] = core_req_rw;
per_bank_core_req_addr_r[core_req_bid[0]] = core_req_line_addr;
per_bank_core_req_wsel_r[core_req_bid[0]] = core_req_wsel;
per_bank_core_req_byteen_r[core_req_bid[0]] = core_req_byteen;
per_bank_core_req_data_r[core_req_bid[0]] = core_req_data;
per_bank_core_req_tag_r[core_req_bid[0]] = core_req_tag;
per_bank_core_req_idx_r[core_req_bid[0]] = 0;
core_req_ready_r = per_bank_core_req_ready[core_req_bid[0]];
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
end
end else begin
`UNUSED_VAR (core_req_bid)
always @(*) begin
per_bank_core_req_valid_r = core_req_valid;
per_bank_core_req_rw_r = core_req_rw;
per_bank_core_req_addr_r = core_req_line_addr;
per_bank_core_req_wsel_r = core_req_wsel;
per_bank_core_req_byteen_r = core_req_byteen;
per_bank_core_req_data_r = core_req_data;
per_bank_core_req_tag_r = core_req_tag;
per_bank_core_req_idx_r = 0;
core_req_ready_r = per_bank_core_req_ready;
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
assign core_req_bid[i] = 0;
end
end
reg [NUM_BANKS-1:0][LINE_ADDR_WIDTH-1:0] per_bank_line_addr_r;
reg [NUM_BANKS-1:0] per_bank_rw_r;
wire [NUM_REQS-1:0] core_req_line_select;
always @(*) begin
per_bank_line_addr_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_line_addr_r[core_req_bid[i]] = core_req_line_addr[i];
per_bank_rw_r[core_req_bid[i]] = core_req_rw[i];
end
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_line_select[i] = (core_req_line_addr[i] == per_bank_line_addr_r[core_req_bid[i]])
&& (core_req_rw[i] == per_bank_rw_r[core_req_bid[i]]);
end
logic [NUM_BANKS-1:0] per_bank_core_req_valid_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(WORD_SEL_BITS)-1:0] per_bank_core_req_wsel_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_WIDTH-1:0] per_bank_core_req_data_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(REQ_SEL_BITS)-1:0] per_bank_core_req_idx_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][TAG_WIDTH-1:0] per_bank_core_req_tag_r;
logic [NUM_BANKS-1:0] per_bank_core_req_rw_r;
logic [NUM_BANKS-1:0][LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
logic [NUM_REQS-1:0] core_req_ready_r;
logic [NUM_BANKS-1:0][NUM_PORTS-1:0][NUM_REQS-1:0] req_select_table_r;
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_pmask_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
per_bank_core_req_byteen_r= 'x;
per_bank_core_req_data_r = 'x;
per_bank_core_req_tag_r = 'x;
per_bank_core_req_idx_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = (1 == NUM_PORTS) || core_req_line_select[i];
per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i];
per_bank_core_req_idx_r[core_req_bid[i]][i % NUM_PORTS] = `UP(REQ_SEL_BITS)'(i);
per_bank_core_req_tag_r[core_req_bid[i]][i % NUM_PORTS] = core_req_tag[i];
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i];
end
end
end
if (NUM_PORTS > 1) begin
always @(*) begin
req_select_table_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
req_select_table_r[core_req_bid[i]][i % NUM_PORTS] = (1 << i);
end
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]]
&& core_req_line_select[i]
&& ((NUM_REQS <= NUM_PORTS)
|| req_select_table_r[core_req_bid[i]][i % NUM_PORTS][i]);
end
end else begin
always @(*) begin
core_req_ready_r = '0;
req_select_table_r = '0;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
req_select_table_r[core_req_bid[i]][0] = (1 << i);
end
end
end
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_req_ready_r[i] = per_bank_core_req_ready[core_req_bid[i]]
&& req_select_table_r[core_req_bid[i]][0][i];
end
end
assign per_bank_core_req_valid = per_bank_core_req_valid_r;
assign per_bank_core_req_pmask = per_bank_core_req_pmask_r;
assign per_bank_core_req_rw = per_bank_core_req_rw_r;
assign per_bank_core_req_addr = per_bank_core_req_addr_r;
assign per_bank_core_req_wsel = per_bank_core_req_wsel_r;
assign per_bank_core_req_byteen = per_bank_core_req_byteen_r;
assign per_bank_core_req_data = per_bank_core_req_data_r;
assign per_bank_core_req_tag = per_bank_core_req_tag_r;
assign per_bank_core_req_idx = per_bank_core_req_idx_r;
assign core_req_ready = core_req_ready_r;
end else begin
assign per_bank_core_req_valid = core_req_valid;
assign per_bank_core_req_pmask = 1;
assign per_bank_core_req_rw = core_req_rw;
assign per_bank_core_req_addr = core_req_line_addr;
assign per_bank_core_req_wsel = core_req_wsel;
assign per_bank_core_req_byteen = core_req_byteen;
assign per_bank_core_req_data = core_req_data;
assign per_bank_core_req_tag = core_req_tag;
assign per_bank_core_req_idx = 0;
assign core_req_ready = per_bank_core_req_ready;
end
assign per_bank_core_req_valid = per_bank_core_req_valid_r;
assign per_bank_core_req_pmask = per_bank_core_req_pmask_r;
assign per_bank_core_req_rw = per_bank_core_req_rw_r;
assign per_bank_core_req_addr = per_bank_core_req_addr_r;
assign per_bank_core_req_wsel = per_bank_core_req_wsel_r;
assign per_bank_core_req_byteen = per_bank_core_req_byteen_r;
assign per_bank_core_req_data = per_bank_core_req_data_r;
assign per_bank_core_req_tag = per_bank_core_req_tag_r;
assign per_bank_core_req_idx = per_bank_core_req_idx_r;
assign core_req_ready = core_req_ready_r;
`ifdef PERF_ENABLE
reg [NUM_REQS-1:0] core_req_sel_r;

68
hw/rtl/cache/VX_rsp_merge.sv vendored
View file

@ -35,82 +35,74 @@ module VX_rsp_merge #(
if ((NUM_BANKS > 1) || (NUM_PORTS > 1)) begin
reg [NUM_REQS-1:0] core_rsp_valid_unqual;
reg [NUM_REQS-1:0][WORD_WIDTH-1:0] core_rsp_data_unqual;
reg [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_unqual;
reg [NUM_REQS-1:0][NUM_BANKS-1:0] per_req_banks_sel;
reg [NUM_REQS-1:0] core_rsp_valid_r;
reg [NUM_REQS-1:0][WORD_WIDTH-1:0] core_rsp_data_r;
reg [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_r;
reg [NUM_REQS-1:0][NUM_BANKS-1:0] bank_select_table_r;
always @(*) begin
core_rsp_valid_unqual = '0;
core_rsp_tag_unqual = 'x;
core_rsp_data_unqual = 'x;
per_req_banks_sel = '0;
core_rsp_valid_r = '0;
core_rsp_tag_r = 'x;
core_rsp_data_r = 'x;
bank_select_table_r = '0;
for (integer b = NUM_BANKS-1; b >= 0; --b) begin
if (per_bank_core_rsp_valid[b]) begin
for (integer p = 0; p < NUM_PORTS; ++p) begin
if ((NUM_PORTS == 1 || per_bank_core_rsp_pmask[b][p])) begin
core_rsp_valid_unqual[per_bank_core_rsp_idx[b][p]] = 1;
core_rsp_data_unqual[per_bank_core_rsp_idx[b][p]] = per_bank_core_rsp_data[b][p];
core_rsp_tag_unqual[per_bank_core_rsp_idx[b][p]] = per_bank_core_rsp_tag[b][p];
per_req_banks_sel[per_bank_core_rsp_idx[b][p]] = (1 << b);
core_rsp_valid_r[per_bank_core_rsp_idx[b][p]] = 1;
core_rsp_data_r[per_bank_core_rsp_idx[b][p]] = per_bank_core_rsp_data[b][p];
core_rsp_tag_r[per_bank_core_rsp_idx[b][p]] = per_bank_core_rsp_tag[b][p];
bank_select_table_r[per_bank_core_rsp_idx[b][p]] = (1 << b);
end
end
end
end
end
logic [NUM_BANKS-1:0] per_bank_rsp_ready_unqual;
if (NUM_PORTS > 1) begin
reg [NUM_BANKS-1:0] per_bank_rsp_ready_unqual1;
reg [NUM_BANKS-1:0] per_bank_rsp_ready_unqual2;
reg [NUM_BANKS-1:0] core_rsp_ready_any_r;
reg [NUM_BANKS-1:0] core_rsp_ready_all_r;
always @(*) begin
per_bank_rsp_ready_unqual1 = '0;
per_bank_rsp_ready_unqual2 = '1;
core_rsp_ready_any_r = '0;
core_rsp_ready_all_r = '1;
for (integer r = 0; r < NUM_REQS; ++r) begin
for (integer b = 0; b < NUM_BANKS; ++b) begin
if (per_req_banks_sel[r][b]) begin
per_bank_rsp_ready_unqual1[b] = 1'b1;
per_bank_rsp_ready_unqual2[b] &= core_rsp_ready[r];
if (bank_select_table_r[r][b]) begin
core_rsp_ready_any_r[b] = 1'b1;
core_rsp_ready_all_r[b] &= core_rsp_ready[r];
end
end
end
end
assign per_bank_rsp_ready_unqual = per_bank_rsp_ready_unqual1 & per_bank_rsp_ready_unqual2;
assign per_bank_core_rsp_ready = core_rsp_ready_any_r & core_rsp_ready_all_r;
end else begin
always @(*) begin
per_bank_rsp_ready_unqual = '0;
for (integer r = 0; r < NUM_REQS; ++r) begin
for (integer b = 0; b < NUM_BANKS; ++b) begin
if (per_req_banks_sel[r][b]) begin
per_bank_rsp_ready_unqual[b] = core_rsp_ready[r];
end
end
end
for (genvar b = 0; b < NUM_BANKS; ++b) begin
assign per_bank_core_rsp_ready[b] = bank_select_table_r[per_bank_core_rsp_idx[b]][b]
&& core_rsp_ready[per_bank_core_rsp_idx[b]];
end
end
assign core_rsp_valid = core_rsp_valid_unqual;
assign {core_rsp_data, core_rsp_tag} = {core_rsp_data_unqual, core_rsp_tag_unqual};
assign per_bank_core_rsp_ready = per_bank_rsp_ready_unqual;
assign core_rsp_valid = core_rsp_valid_r;
assign {core_rsp_data, core_rsp_tag} = {core_rsp_data_r, core_rsp_tag_r};
end else if (NUM_REQS > 1) begin
`UNUSED_VAR (per_bank_core_rsp_pmask)
reg [NUM_REQS-1:0] core_rsp_valid_unqual;
reg [NUM_REQS-1:0] core_rsp_valid_r;
always @(*) begin
core_rsp_valid_unqual = '0;
core_rsp_valid_unqual[per_bank_core_rsp_idx] = per_bank_core_rsp_valid;
core_rsp_valid_r = '0;
core_rsp_valid_r[per_bank_core_rsp_idx] = per_bank_core_rsp_valid;
end
assign core_rsp_valid = core_rsp_valid_unqual;
assign core_rsp_valid = core_rsp_valid_r;
assign core_rsp_data = {NUM_REQS{per_bank_core_rsp_data}};
assign core_rsp_tag = {NUM_REQS{per_bank_core_rsp_tag}};
assign per_bank_core_rsp_ready = core_rsp_ready[per_bank_core_rsp_idx];

2
hw/rtl/cache/VX_shared_mem.sv vendored
View file

@ -209,7 +209,7 @@ module VX_shared_mem #(
.DATAW (WORD_WIDTH + TAG_WIDTH),
.SKID (OUT_REG >> 1),
.OUT_REG (OUT_REG & 1)
) rsp_sbuf_out (
) rsp_sbuf (
.clk (clk),
.reset (reset),
.valid_in (rsp_valid_s[i]),

2
hw/rtl/raster_unit/VX_raster_mem.sv
View file

@ -258,7 +258,7 @@ module VX_raster_mem #(
.DATA_WIDTH (`RASTER_DATA_BITS),
.QUEUE_SIZE (`RASTER_MEM_QUEUE_SIZE),
.TAG_WIDTH (TAG_WIDTH),
.CORE_OUT_REG (1),
.CORE_OUT_REG (2),
.MEM_OUT_REG (3)
) mem_scheduler (
.clk (clk),

27
sim/rtlsim/processor.cpp
View file

@ -166,7 +166,8 @@ public:
#endif
// start device
this->start();
this->reset();
running_ = true;
// execute program
while (device_->busy) {
@ -181,7 +182,7 @@ public:
this->wait(5);
// stop device
this->stop();
running_ = false;
return exitcode;
}
@ -197,7 +198,7 @@ public:
private:
void reset() {
void reset() {
running_ = false;
print_bufs_.clear();
@ -237,28 +238,8 @@ private:
Verilated::assertOn(true);
this->cout_flush();
}
void start() {
device_->start = 1;
for (int i = 0; i < RESET_DELAY; ++i) {
device_->clk = 0;
this->eval();
device_->clk = 1;
this->eval();
}
device_->start = 0;
running_ = true;
this->cout_flush();
}
void stop() {
running_ = false;
}
void tick() {