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Fixed rtlsim of vote and shfl

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This commit is contained in:
Rishabh Ravi 2024-08-21 05:45:49 -04:00
parent 04f7892e3e
commit c4516898a8
3 changed files with 28 additions and 31 deletions
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21
hw/rtl/core/VX_alu_int.sv
View file

@ -118,18 +118,17 @@ module VX_alu_int #(
end
// VOTE
wire [NUM_LANES-1:0] active_t = NUM_LANES'(alu_in2[0] & `XLEN'(execute_if.data.tmask));
wire [NUM_LANES-1:0] active_t = (alu_in2[0][NUM_LANES-1:0] & (execute_if.data.tmask));
wire [NUM_LANES-1:0] is_pred;
wire [NUM_LANES-1:0] vote_in = (is_pred & active_t);
wire is_neg = alu_op[2];
wire vote_all = (is_neg) ? (vote_in == NUM_LANES'(1'b0)) : (vote_in == active_t);
wire vote_any = (is_neg) ? (vote_in != active_t) : (vote_in > NUM_LANES'(1'b0));
wire vote_uni = ((is_pred == active_t) || (is_pred == NUM_LANES'(1'b0)));
wire [NUM_LANES-1:0] vote_ballot;
wire vote_uni = ((vote_in == active_t) || (vote_in == NUM_LANES'(1'b0)));
wire [NUM_LANES-1:0] vote_ballot = vote_in;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign is_pred[i] = alu_in1[i][0];
assign vote_ballot[i] = (active_t[i] && is_pred[i]);
assign is_pred[i] = alu_in1[i][0] & alu_in2[0][i];
always @(*) begin
case (alu_op[1:0])
2'b00: vote_result[i] = `XLEN'(vote_all); // ALL, NONE
@ -147,12 +146,12 @@ module VX_alu_int #(
wire [NUM_LANES-1:0][`XLEN-1:0] maxLane, minLane;
reg [NUM_LANES-1:0][`XLEN-1:0] lane;
reg [NUM_LANES-1:0] p;
wire [NUM_LANES-1:0][`XLEN-1:0] active_l;
wire [NUM_LANES-1:0] active_l;
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign b[i] = (alu_in2_imm[i]>>4)&(`XLEN'(4'b1111));
assign segmask[i] = ((alu_in3[i] & `XLEN'(12'h0f0))>>4);
assign c[i] = (alu_in3[i] & `XLEN'(12'h00f));
assign b[i] = (alu_in2_imm[i]>>5)&(`XLEN'(5'b11111));
assign segmask[i] = ((alu_in3[i]>>5)&(`XLEN'(5'b11111)));
assign c[i] = (alu_in3[i] & `XLEN'(5'b11111));
assign maxLane[i] = ((`XLEN'(i) & segmask[i]) | (c[i] & ~(segmask[i])));
assign minLane[i] = (`XLEN'(i) & segmask[i]);
always @(*) begin
@ -181,8 +180,8 @@ module VX_alu_int #(
if(p[i] == 1'b0) begin
lane[i] = `XLEN'(i);
end
active_l[i] = lane[i] & alu_in2[i];
shfl_result[i] = (active_t[i] && (active_l[i] == `XLEN'(1'b1)) && (lane[i] < NUM_LANES)) ? alu_in1[$signed(lane[i])] : alu_in1[i];
active_l[i] = (lane[i] < NUM_LANES) ? alu_in2[0][$signed(lane[i])] : alu_in2[0][i];
shfl_result[i] = (active_t[i] && active_l[i]) ? ( (lane[i] < NUM_LANES) ? alu_in1[$signed(lane[i])] : alu_in1[i]) : `XLEN'(1'b0);
end
end

14
hw/rtl/core/VX_decode.sv
View file

@ -66,7 +66,7 @@ module VX_decode import VX_gpu_pkg::*; #(
wire [4:0] rd = instr[11:7];
wire [4:0] rs1 = instr[19:15];
wire [4:0] rs2 = instr[24:20];
wire [4:0] rs3 = instr[31:27];
wire [4:0] rs3 = (opcode == `INST_SHFL)? {3'b000,instr[31:30]} + instr[24:20] : instr[31:27];
`UNUSED_VAR (func2)
`UNUSED_VAR (func5)
@ -519,15 +519,14 @@ module VX_decode import VX_gpu_pkg::*; #(
end
`INST_VOTE: begin
ex_type = `EX_ALU;
//is_wstall = 1;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, u_12);
op_args.alu.xtype = `ALU_TYPE_OTHER;
op_args.alu.is_w = 1;
use_rd = 1;
`USED_IREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2); //membermask imm[23:20]
`USED_IREG (rs1);
`USED_IREG (rs2); //membermask imm[24:20]
case (func3)
3'b000: begin
op_type = `INST_OP_BITS'(`VOTE_ALL);
@ -552,16 +551,15 @@ module VX_decode import VX_gpu_pkg::*; #(
end
`INST_SHFL: begin
ex_type = `EX_ALU;
is_wstall = 1;
op_args.alu.use_imm = 1;
op_args.alu.imm = `SEXT(`IMM_BITS, u_12);
op_args.alu.xtype = `ALU_TYPE_OTHER;
op_args.alu.is_w = 1;
use_rd = 1;
`USED_IREG (rd);
`USED_FREG (rs1);
`USED_FREG (rs2); //membermask imm[23:20]
`USED_FREG (rs3); //c imm[31:27]
`USED_IREG (rs1);
`USED_IREG (rs2); //membermask imm[24:20]
`USED_IREG (rs3); //c offset imm[31:28]
case (func3)
3'b000: begin
op_type = `INST_OP_BITS'(`SHFL_BFLY);

24
hw/rtl/core/VX_trace.vh
View file

@ -132,18 +132,18 @@
end
end
`ALU_TYPE_OTHER: begin
case (op_type)
`VOTE_ALL: `TRACE(level, ("VOTE.ALL"));
`VOTE_ANY: `TRACE(level, ("VOTE.ANY"));
`VOTE_UNI: `TRACE(level, ("VOTE.UNI"));
`VOTE_BALLOT: `TRACE(level, ("VOTE.BALLOT"));
`SHFL_BFLY: `TRACE(level, ("SHFL.BFLY"));
`SHFL_UP: `TRACE(level, ("SHFL.UP"));
`SHFL_DOWN: `TRACE(level, ("SHFL.DOWN"));
`SHFL_IDX: `TRACE(level, ("SHFL.IDX"));
`VOTE_NONE: `TRACE(level, ("VOTE.NONE"));
`VOTE_NOT_ALL: `TRACE(level, ("VOTE.NOT.ALL"));
default: `TRACE(level, ("?"));
case(op_type)
`VOTE_ALL: `TRACE(level, ("VOTE_ALL"));
`VOTE_ANY: `TRACE(level, ("VOTE_ANY"));
`VOTE_UNI: `TRACE(level, ("VOTE_UNI"));
`VOTE_BALLOT: `TRACE(level, ("VOTE_BALLOT"));
`VOTE_NONE: `TRACE(level, ("VOTE_NONE"));
`VOTE_NOT_ALL: `TRACE(level, ("VOTE_NOT_ALL"));
`SHFL_BFLY: `TRACE(level, ("SHFL_BFLY"));
`SHFL_UP: `TRACE(level, ("SHFL_UP"));
`SHFL_DOWN: `TRACE(level, ("SHFL_DOWN"));
`SHFL_IDX: `TRACE(level, ("SHFL_IDX"));
default: `TRACE(level, ("?"));
endcase
end
default: `TRACE(level, ("?"));