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fpga fixes

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This commit is contained in:
Blaise Tine 2023-06-08 10:31:42 -07:00
parent 7466ad151d
commit c4c1d99ab6
26 changed files with 78 additions and 79 deletions
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1
hw/rtl/cache/VX_cache_req_if.sv vendored
View file

@ -1,5 +1,4 @@
`include "VX_cache_define.vh"
`include "VX_config.vh"
interface VX_cache_req_if #(
parameter NUM_REQS = 1,

1
hw/rtl/core/VX_alu_unit.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
module VX_alu_unit #(
parameter CORE_ID = 0

1
hw/rtl/core/VX_commit.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
module VX_commit #(
parameter CORE_ID = 0

1
hw/rtl/core/VX_csr_unit.sv
View file

@ -1,6 +1,5 @@
`include "VX_define.vh"
`include "VX_gpu_types.vh"
`include "VX_config.vh"
`IGNORE_WARNINGS_BEGIN
import VX_gpu_types::*;

1
hw/rtl/core/VX_decode.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
`ifndef NDEBUG
`include "VX_trace_info.vh"
`endif

3
hw/rtl/core/VX_dispatch.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
module VX_dispatch (
input wire clk,
@ -74,7 +73,7 @@ module VX_dispatch (
.reset (reset),
.valid_in (lsu_req_valid),
.ready_in (lsu_req_ready),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, lsu_op_type, lsu_is_fence, ibuffer_if.imm, dispatch_if.rd, dispatch_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_in ({dispatch_if.uuid, dispatch_if.wid, dispatch_if.tmask, dispatch_if.PC, lsu_op_type, lsu_is_fence, dispatch_if.imm, dispatch_if.rd, dispatch_if.wb, gpr_rsp_if.rs1_data, gpr_rsp_if.rs2_data}),
.data_out ({lsu_req_if.uuid, lsu_req_if.wid, lsu_req_if.tmask, lsu_req_if.PC, lsu_req_if.op_type, lsu_req_if.is_fence, lsu_req_if.offset, lsu_req_if.rd, lsu_req_if.wb, lsu_req_if.base_addr, lsu_req_if.store_data}),
.valid_out (lsu_req_if.valid),
.ready_out (lsu_req_if.ready)

1
hw/rtl/core/VX_lsu_unit.sv
View file

@ -1,6 +1,5 @@
`include "VX_define.vh"
`include "VX_gpu_types.vh"
`include "VX_config.vh"
`IGNORE_WARNINGS_BEGIN
import VX_gpu_types::*;

1
hw/rtl/interfaces/VX_gpr_rsp_if.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
interface VX_gpr_rsp_if ();

1
hw/rtl/interfaces/VX_mem_req_if.sv
View file

@ -1,5 +1,4 @@
`include "VX_define.vh"
`include "VX_config.vh"
interface VX_mem_req_if #(
parameter DATA_WIDTH = 1,

60
hw/scripts/gen_sources.sh
View file

@ -2,6 +2,7 @@
defines=()
includes=()
externs=()
output_file=""
global_file=""
@ -11,20 +12,6 @@ prepropressor=0
defines_str=""
includes_str=""
function absolute_path() {
if [ -d "$1" ]; then
(cd "$1"; pwd)
elif [ -f "$1" ]; then
if [[ $1 = /* ]]; then
echo "$1"
elif [[ $1 == */* ]]; then
echo "$(cd "${1%/*}"; pwd)/${1##*/}"
else
echo "$(pwd)/$1"
fi
fi
}
# parse command arguments
while getopts D:I:J:O:G:C:Ph flag
do
@ -35,11 +22,14 @@ do
I) includes+=( ${OPTARG} )
includes_str+="-I${OPTARG} "
;;
J) externs+=( ${OPTARG} )
includes_str+="-I${OPTARG} "
;;
O) output_file=( ${OPTARG} );;
G) global_file=( ${OPTARG} );;
C) copy_folder=( ${OPTARG} );;
P) prepropressor=1;;
h) echo "Usage: [-D<macro>] [-I<include-path>] [-O<output-file>] [-C<dest-folder>: copy to] [-G<global_header>] [-P: macro prepropressing] [-h help]"
h) echo "Usage: [-D<macro>] [-I<include-path>] [-J<external-path>] [-O<output-file>] [-C<dest-folder>: copy to] [-G<global_header>] [-P: macro prepropressing] [-h help]"
exit 0
;;
\?)
@ -65,14 +55,14 @@ if [ "$global_file" != "" ]; then
fi
if [ "$copy_folder" != "" ]; then
# copy source files
mkdir -p $copy_folder
# copy source files
mkdir -p $copy_folder
for dir in ${includes[@]}; do
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -o -name '*.vh' -o -name '*.svh' -o -name '*.hex' -type f); do
find "$dir" -maxdepth 1 -type f | while read -r file; do
if [ $prepropressor != 0 ]; then
verilator $defines_str $includes_str -E -P $(absolute_path $file) > $copy_folder/$(basename -- $file)
verilator $defines_str $includes_str -E -P $file > $copy_folder/$(basename -- $file)
else
cp $(absolute_path $file) $copy_folder
cp $file $copy_folder
fi
done
done
@ -87,25 +77,29 @@ if [ "$output_file" != "" ]; then
done
fi
if [ "$copy_folder" == "" ]; then
for dir in ${externs[@]}; do
echo "+incdir+$(realpath $dir)"
done
for dir in ${externs[@]}; do
find "$(realpath $dir)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) -print
done
if [ "$copy_folder" != "" ]; then
# dump include directories
for dir in ${includes[@]}; do
echo "+incdir+$dir"
done
echo "+incdir+$(realpath $copy_folder)"
# dump source files
for dir in ${includes[@]}; do
for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
echo $(absolute_path $file)
done
done
find "$(realpath $copy_folder)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) -print
else
# dump include directories
echo "+incdir+$copy_folder"
for dir in ${includes[@]}; do
echo "+incdir+$(realpath $dir)"
done
# dump source files
for file in $(find $copy_folder -maxdepth 1 -name '*.v' -o -name '*.sv' -type f); do
echo $(absolute_path $file)
for dir in ${includes[@]}; do
find "$(realpath $dir)" -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" \) -print
done
fi
} > $output_file

27
hw/syn/altera/NOTEBOOK
View file

@ -29,10 +29,10 @@ qsub-fpga
cd $PBS_O_WORKDIR
# Load the image onto an FPGA
fpgaconf vortex_afu.gbs
fpgaconf <build>/synth/vortex_afu.gbs
# If this says Multiple ports. Then use --bus with fpgaconf. #bus info can be found by fpgainfo port
fpgaconf --bus 0xaf vortex_afu.gbs
fpgaconf --bus 0xaf <build>/synth/vortex_afu.gbs
# get portid
fpgainfo port
@ -57,15 +57,15 @@ PREFIX=build_gfx NUM_CORES=1 CONFIGS="-DEXT_GFX_ENABLE -DEXT_F_DISABLE -DL1_DISA
PREFIX=build_gfx NUM_CORES=1 CONFIGS="-DEXT_RASTER_ENABLE -DEXT_F_DISABLE -DL1_DISABLE -DSM_DISABLE -DRCACHE_DISABLE -DNUM_WARPS=2 -DNUM_THREADS=2" TARGET=asesim make
# ASE tests
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/basic/basic -n1 -t0
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/basic/basic -n1 -t1
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/basic/basic -n16
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/demo/demo -n16
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/dogfood/dogfood -n16
./run_ase.sh build_arria10_ase_1c ../../../../tests/opencl/vecadd/vecadd
./run_ase.sh build_arria10_ase_1c ../../../../tests/opencl/sgemm/sgemm -n4
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/raster/raster -w8 -h8
./run_ase.sh build_arria10_ase_1c ../../../../tests/regression/draw3d/draw3d -w8 -h8
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/basic/basic -n1 -t0
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/basic/basic -n1 -t1
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/basic/basic -n16
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/demo/demo -n16
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/dogfood/dogfood -n16
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/opencl/vecadd/vecadd
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/opencl/sgemm/sgemm -n4
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/raster/raster -w8 -h8
./run_ase.sh build_arria10_ase_1c/synth ../../../../tests/regression/draw3d/draw3d -w8 -h8
# modify "vsim_run.tcl" to dump VCD trace
vcd file trace.vcd
@ -78,14 +78,15 @@ tar -zcvf output_files_1c.tar.gz `find ./build_fpga_1c -type f \( -iname \*.rpt
# compress log trace
tar -zcvf run.log.tar.gz run.log
tar -cvjf trace.vcd.tar.bz2 trace.vcd run.log
tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/work/run.log build_arria10_ase_1c/work/trace.vcd
tar -cvjf trace.vcd.tar.bz2 build_arria10_ase_1c/synth/work/run.log build_arria10_ase_1c/work/trace.vcd
# decompress log trace
tar -zxvf vortex.vcd.tar.gz
tar -xvf vortex.vcd.tar.bz2
# building FPGA images
PREFIX=build_gfx NUM_CORES=1 CONFIGS="-DEXT_GFX_ENABLE" TARGET=fpga make
make all
PREFIX=build_gfx NUM_CORES=2 CONFIGS="-DEXT_GFX_ENABLE" make
# running graphics benchmarks
TARGET=fpga ./ci/blackbox.sh --driver=opae --app=draw3d --args="-w512 -h512 -tvase.cgltrace"

35
hw/syn/altera/opae/Makefile
View file

@ -58,7 +58,7 @@ CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
@ -109,19 +109,32 @@ swconfig: vortex_afu.h
vortex_afu.h: vortex_afu.json
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
setup:
ifeq ($(TARGET), asesim)
afu_sim_setup -s setup.cfg $(BUILD_DIR)
else
afu_synth_setup -s setup.cfg $(BUILD_DIR)
endif
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -Osources.txt
$(BUILD_DIR)/setup.cfg:
mkdir -p $(BUILD_DIR); cp setup.cfg $(BUILD_DIR)/setup.cfg
build: ip-gen setup $(SCOPE_JSON)
$(BUILD_DIR)/vortex_afu.qsf:
mkdir -p $(BUILD_DIR); cp vortex_afu.qsf $(BUILD_DIR)/vortex_afu.qsf
$(BUILD_DIR)/vortex_afu.json:
mkdir -p $(BUILD_DIR); cp vortex_afu.json $(BUILD_DIR)/vortex_afu.json
sources: $(BUILD_DIR)/sources.txt
$(BUILD_DIR)/sources.txt:
mkdir -p $(BUILD_DIR); $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -C$(BUILD_DIR)/src -O$(BUILD_DIR)/sources.txt
setup: $(BUILD_DIR)/synth
$(BUILD_DIR)/synth: $(BUILD_DIR)/sources.txt $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/vortex_afu.qsf $(BUILD_DIR)/vortex_afu.json
ifeq ($(TARGET), asesim)
make -C $(BUILD_DIR) > $(BUILD_DIR)/build.log 2>&1 &
afu_sim_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
else
cd $(BUILD_DIR) && $(RUN_SYNTH)
afu_synth_setup -s $(BUILD_DIR)/setup.cfg $(BUILD_DIR)/synth
endif
build: ip-gen setup $(SCOPE_JSON)
ifeq ($(TARGET), asesim)
make -C $(BUILD_DIR)/synth > $(BUILD_DIR)/synth/build.log 2>&1 &
else
cd $(BUILD_DIR)/synth && $(RUN_SYNTH)
endif
gen-ast: $(BUILD_DIR)/vortex.xml

2
hw/syn/altera/quartus/core/Makefile
View file

@ -6,6 +6,6 @@ include ../../common.mk
CONFIGS += -DEXT_GFX_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

2
hw/syn/altera/quartus/fpu_unit/Makefile → hw/syn/altera/quartus/fpu/Makefile
View file

@ -4,5 +4,5 @@ SRC_FILE = $(PROJECT).sv
include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
RTL_INCLUDE = $(FPU_INCLUDE) -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(IP_CACHE_DIR)

0
hw/syn/altera/quartus/raster_unit/Makefile → hw/syn/altera/quartus/raster/Makefile
View file

0
hw/syn/altera/quartus/rop_unit/Makefile → hw/syn/altera/quartus/rop/Makefile
View file

2
hw/syn/altera/quartus/test/Makefile
View file

@ -6,6 +6,6 @@ include ../../common.mk
CONFIGS += -DEXT_GFX_ENABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
GFX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(GFX_INCLUDE)

0
hw/syn/altera/quartus/tex_unit/Makefile → hw/syn/altera/quartus/tex/Makefile
View file

2
hw/syn/altera/quartus/top-gfx/Makefile
View file

@ -16,6 +16,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DSM_DISABLE
#CONFIGS += -DRCACHE_DISABLE -DOCACHE_DISABLE -DTCACHE_DISABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex -I$(RTL_DIR)/raster -I$(RTL_DIR)/rop
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/top/Makefile
View file

@ -13,6 +13,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DL1_DISABLE
#CONFIGS += -DSM_DISABLE
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(AFU_DIR) -I$(AFU_DIR)/ccip -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/unittest/Makefile
View file

@ -4,6 +4,6 @@ SRC_FILE = $(PROJECT).sv
include ../../common.mk
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/altera/quartus/vortex/Makefile
View file

@ -16,6 +16,6 @@ CONFIGS += -DL2_ENABLE
#CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/cache -I$(IP_CACHE_DIR) $(FPU_INCLUDE) $(TEX_INCLUDE)

2
hw/syn/xilinx/test/Makefile
View file

@ -6,7 +6,7 @@ SCRIPT_DIR = ../../../scripts
THIRD_PARTY_DIR = ../../../../third_party
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop

4
hw/syn/xilinx/xrt/Makefile
View file

@ -77,7 +77,7 @@ CONFIGS_64c := -DNUM_CLUSTERS=4 -DNUM_CORES=16 -DL2_ENABLE
CONFIGS += $(CONFIGS_$(NUM_CORES)c)
# include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -I$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -I$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -I$(THIRD_PARTY_DIR)/fpnew/src
FPU_INCLUDE = -I$(RTL_DIR)/fpu -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/include -J$(THIRD_PARTY_DIR)/fpnew/src/common_cells/src -J$(THIRD_PARTY_DIR)/fpnew/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/fpnew/src
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
ROP_INCLUDE = -I$(RTL_DIR)/rop
@ -133,7 +133,7 @@ else
endif
# compilation flags
CFLAGS += -DSYNTHESIS -DVIVADO
CFLAGS += -DSYNTHESIS -DVIVADO -DCPU_DSP
CFLAGS += $(CONFIGS)
CFLAGS += $(RTL_INCLUDE)

2
third_party/cocogfx vendored

@ -1 +1 @@
Subproject commit e4656d62878e517e743e891d22628c9191dca6bc
Subproject commit 6448e68330ca00a64ab3184e3c5c95b59fe8b62a

2
third_party/fpnew vendored

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Subproject commit 3116391bf66660f806b45e212b9949c528b4e270
Subproject commit 0bfbeede0e01b2e44e41bb14c70a80efeffa1bbd