mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 13:27:29 -04:00
fixed SCOPE interface
This commit is contained in:
Blaise Tine
parent
31ffbe0d6a
commit
c63217f67d
11 changed files with 117 additions and 174 deletions
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@ -32,6 +32,12 @@ constexpr int ilog2(int n) {
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static constexpr int NW_BITS = ilog2(NUM_WARPS);
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#ifdef EXT_F_ENABLE
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static constexpr int NR_BITS = ilog2(64);
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#else
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static constexpr int NR_BITS = ilog2(32);
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#endif
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static const scope_signal_t scope_signals[] = {
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{ 32, "dram_req_addr" },
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@ -47,39 +53,32 @@ static const scope_signal_t scope_signals[] = {
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{ 16, "snp_req_tag" },
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{ 16, "snp_rsp_tag" },
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{ NW_BITS, "icache_req_warp_num" },
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{ NW_BITS, "icache_req_wid" },
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{ 32, "icache_req_addr" },
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{ NW_BITS, "icache_req_tag" },
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{ 32, "icache_rsp_data" },
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{ NW_BITS, "icache_rsp_tag" },
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{ NW_BITS, "dcache_req_warp_num" },
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{ 32, "dcache_req_curr_PC" },
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{ 64, "dcache_req_addr" },
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{ NW_BITS, "dcache_req_wid" },
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{ 32, "dcache_req_PC" },
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{ NUM_THREADS * 32, "dcache_req_addr" },
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{ 1, "dcache_req_rw" },
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{ 8, "dcache_req_byteen" },
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{ 64, "dcache_req_data" },
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{ NUM_THREADS * 4, "dcache_req_byteen" },
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{ NUM_THREADS * 32, "dcache_req_data" },
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{ NW_BITS, "dcache_req_tag" },
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{ 64, "dcache_rsp_data" },
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{ NUM_THREADS * 32, "dcache_rsp_data" },
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{ NW_BITS, "dcache_rsp_tag" },
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{ NW_BITS, "decode_warp_num" },
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{ 32, "decode_curr_PC" },
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{ 1, "decode_is_jal" },
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{ 5, "decode_rs1" },
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{ 5, "decode_rs2" },
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{ NW_BITS, "alu_req_wid" },
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{ 32, "alu_req_PC" },
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{ NR_BITS, "alu_req_rd" },
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{ NUM_THREADS * 32, "alu_req_a" },
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{ NUM_THREADS * 32, "alu_req_b" },
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{ NW_BITS, "execute_warp_num" },
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{ 32, "execute_curr_PC" },
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{ 5, "execute_rd" },
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{ 64, "execute_a" },
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{ 64, "execute_b" },
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{ NW_BITS, "writeback_warp_num" },
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{ 32, "writeback_curr_PC" },
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{ 2, "writeback_wb" },
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{ 5, "writeback_rd" },
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{ 64, "writeback_data" },
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{ NW_BITS, "writeback_wid" },
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{ 32, "writeback_PC" },
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{ NR_BITS, "writeback_rd" },
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{ NUM_THREADS * 32, "writeback_data" },
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{ 32, "bank_addr_st0" },
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{ 32, "bank_addr_st1" },
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@ -112,13 +111,9 @@ static const scope_signal_t scope_signals[] = {
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{ 1, "dcache_rsp_ready" },
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{ NUM_THREADS, "decode_valid" },
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{ NUM_THREADS, "execute_valid" },
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{ NUM_THREADS, "writeback_valid" },
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{ NUM_THREADS, "alu_req_valid" },
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{ NUM_THREADS, "writeback_valid" },
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{ 1, "schedule_delay" },
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{ 1, "mem_delay" },
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{ 1, "exec_delay" },
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{ 1, "gpr_delay" },
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{ 1, "busy" },
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{ 1, "bank_valid_st0" },
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@ -62,8 +62,8 @@ ifdef AFU
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TOP = vortex_afu_sim
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VL_FLAGS += -DNOPAE
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CFLAGS += -DNOPAE
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#VL_FLAGS += -DSCOPE
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#CFLAGS += -DSCOPE
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VL_FLAGS += -DSCOPE
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CFLAGS += -DSCOPE
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RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip
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endif
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@ -916,7 +916,7 @@ Vortex #() vortex (
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`SCOPE_SIGNALS_CORE_BIND
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`SCOPE_SIGNALS_CACHE_BIND
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`SCOPE_SIGNALS_PIPELINE_BIND
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`SCOPE_SIGNALS_BE_BIND
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`SCOPE_SIGNALS_EX_BIND
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.clk (clk),
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.reset (SoftReset | vx_reset),
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@ -1017,8 +1017,8 @@ localparam SCOPE_SR_DEPTH = 2;
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wire scope_changed = (scope_icache_req_valid && scope_icache_req_ready)
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|| (scope_icache_rsp_valid && scope_icache_rsp_ready)
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|| (scope_dcache_req_valid && scope_dcache_req_ready)
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|| (scope_dcache_rsp_valid && scope_dcache_rsp_ready)
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|| ((| scope_dcache_req_valid) && scope_dcache_req_ready)
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|| ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready)
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|| (scope_dram_req_valid && scope_dram_req_ready)
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|| (scope_dram_rsp_valid && scope_dram_rsp_ready)
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|| (scope_snp_req_valid && scope_snp_req_ready)
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@ -8,7 +8,7 @@ module VX_cluster #(
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`SCOPE_SIGNALS_CORE_IO
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`SCOPE_SIGNALS_CACHE_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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// Clock
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input wire clk,
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@ -144,7 +144,7 @@ module VX_cluster #(
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`SCOPE_SIGNALS_CORE_BIND
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`SCOPE_SIGNALS_CACHE_BIND
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`SCOPE_SIGNALS_PIPELINE_BIND
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`SCOPE_SIGNALS_BE_BIND
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`SCOPE_SIGNALS_EX_BIND
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.clk (clk),
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.reset (reset),
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@ -8,7 +8,7 @@ module VX_core #(
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`SCOPE_SIGNALS_CORE_IO
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`SCOPE_SIGNALS_CACHE_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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// Clock
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input wire clk,
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@ -183,7 +183,7 @@ module VX_core #(
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`SCOPE_SIGNALS_ISTAGE_BIND
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_PIPELINE_BIND
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`SCOPE_SIGNALS_BE_BIND
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`SCOPE_SIGNALS_EX_BIND
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.clk(clk),
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.reset(reset),
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@ -4,7 +4,7 @@ module VX_execute #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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input wire clk,
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input wire reset,
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@ -126,24 +126,16 @@ module VX_execute #(
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&& (`BR_OP(alu_req_if.op_type) == `BR_EBREAK
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|| `BR_OP(alu_req_if.op_type) == `BR_ECALL);
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`SCOPE_ASSIGN (scope_decode_valid, decode_if.valid);
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`SCOPE_ASSIGN (scope_decode_wid, decode_if.wid);
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`SCOPE_ASSIGN (scope_decode_curr_PC, decode_if.curr_PC);
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`SCOPE_ASSIGN (scope_decode_is_jal, decode_if.is_jal);
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`SCOPE_ASSIGN (scope_decode_rs1, decode_if.rs1);
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`SCOPE_ASSIGN (scope_decode_rs2, decode_if.rs2);
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`SCOPE_ASSIGN (scope_execute_valid, alu_req_if.valid);
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`SCOPE_ASSIGN (scope_execute_wid, alu_req_if.wid);
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`SCOPE_ASSIGN (scope_execute_curr_PC, alu_req_if.curr_PC);
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`SCOPE_ASSIGN (scope_execute_rd, alu_req_if.rd);
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`SCOPE_ASSIGN (scope_execute_a, alu_req_if.rs1_data);
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`SCOPE_ASSIGN (scope_execute_b, alu_req_if.rs2_data);
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`SCOPE_ASSIGN (scope_alu_req_valid, alu_req_if.valid);
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`SCOPE_ASSIGN (scope_alu_req_wid, alu_req_if.wid);
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`SCOPE_ASSIGN (scope_alu_req_PC, alu_req_if.curr_PC);
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`SCOPE_ASSIGN (scope_alu_req_rd, alu_req_if.rd);
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`SCOPE_ASSIGN (scope_alu_req_a, alu_req_if.rs1_data);
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`SCOPE_ASSIGN (scope_alu_req_b, alu_req_if.rs2_data);
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`SCOPE_ASSIGN (scope_writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN (scope_writeback_wid, writeback_if.wid);
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`SCOPE_ASSIGN (scope_writeback_curr_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN (scope_writeback_wb, writeback_if.wb);
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`SCOPE_ASSIGN (scope_writeback_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN (scope_writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN (scope_writeback_data, writeback_if.data);
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@ -3,6 +3,8 @@
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module VX_fetch #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_ISTAGE_IO
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input wire clk,
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input wire reset,
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@ -194,13 +194,13 @@ module VX_lsu_unit #(
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// scope registration
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`SCOPE_ASSIGN (scope_dcache_req_valid, dcache_req_if.valid);
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`SCOPE_ASSIGN (scope_dcache_req_addr, req_address);
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`SCOPE_ASSIGN (scope_dcache_req_rw, dcache_req_if.rw );
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`SCOPE_ASSIGN (scope_dcache_req_rw, req_rw);
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`SCOPE_ASSIGN (scope_dcache_req_byteen,dcache_req_if.byteen);
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`SCOPE_ASSIGN (scope_dcache_req_data, dcache_req_if.data);
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`SCOPE_ASSIGN (scope_dcache_req_tag, dcache_req_if.tag);
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`SCOPE_ASSIGN (scope_dcache_req_ready, dcache_req_if.ready);
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`SCOPE_ASSIGN (scope_dcache_req_wid, req_wid);
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`SCOPE_ASSIGN (scope_dcache_req_curr_PC, req_pc);
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`SCOPE_ASSIGN (scope_dcache_req_PC, req_curr_PC);
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`SCOPE_ASSIGN (scope_dcache_rsp_valid, dcache_rsp_if.valid);
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`SCOPE_ASSIGN (scope_dcache_rsp_data, dcache_rsp_if.data);
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@ -6,7 +6,7 @@ module VX_pipeline #(
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`SCOPE_SIGNALS_ISTAGE_IO
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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`SCOPE_SIGNALS_EX_IO
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// Clock
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input wire clk,
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@ -126,6 +126,7 @@ module VX_pipeline #(
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VX_fetch #(
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.CORE_ID(CORE_ID)
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) fetch (
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`SCOPE_SIGNALS_ISTAGE_BIND
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.clk (clk),
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.reset (reset),
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.icache_req_if (core_icache_req_if),
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@ -171,6 +172,7 @@ module VX_pipeline #(
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.CORE_ID(CORE_ID)
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) execute (
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_EX_BIND
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.clk (clk),
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.reset (reset),
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@ -245,10 +247,6 @@ module VX_pipeline #(
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assign core_icache_rsp_if.tag = icache_rsp_tag;
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assign icache_rsp_ready = core_icache_rsp_if.ready;
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`SCOPE_ASSIGN (scope_busy, busy);
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`SCOPE_ASSIGN (scope_schedule_delay, schedule_delay);
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`SCOPE_ASSIGN (scope_mem_delay, mem_delay);
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`SCOPE_ASSIGN (scope_exec_delay, exec_delay);
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`SCOPE_ASSIGN (scope_gpr_stage_delay, gpr_delay);
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`SCOPE_ASSIGN (scope_busy, busy);
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endmodule
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@ -21,7 +21,7 @@
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scope_icache_rsp_data, \
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scope_icache_rsp_tag, \
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scope_dcache_req_wid, \
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scope_dcache_req_curr_PC, \
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scope_dcache_req_PC, \
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scope_dcache_req_addr, \
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scope_dcache_req_rw, \
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scope_dcache_req_byteen, \
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@ -29,19 +29,13 @@
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scope_dcache_req_tag, \
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scope_dcache_rsp_data, \
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scope_dcache_rsp_tag, \
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scope_decode_wid, \
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scope_decode_curr_PC, \
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scope_decode_is_jal, \
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scope_decode_rs1, \
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scope_decode_rs2, \
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scope_execute_wid, \
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scope_execute_curr_PC, \
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scope_execute_rd, \
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scope_execute_a, \
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scope_execute_b, \
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scope_alu_req_wid, \
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scope_alu_req_PC, \
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scope_alu_req_rd, \
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scope_alu_req_a, \
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scope_alu_req_b, \
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scope_writeback_wid, \
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scope_writeback_curr_PC, \
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scope_writeback_wb, \
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scope_writeback_PC, \
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scope_writeback_rd, \
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scope_writeback_data, \
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scope_bank_addr_st0, \
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@ -70,13 +64,8 @@
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scope_dcache_req_ready, \
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scope_dcache_rsp_valid, \
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scope_dcache_rsp_ready, \
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scope_decode_valid, \
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scope_execute_valid, \
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scope_alu_req_valid, \
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scope_writeback_valid, \
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scope_schedule_delay, \
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scope_mem_delay, \
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scope_exec_delay, \
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scope_gpr_stage_delay, \
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scope_busy, \
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scope_bank_valid_st0, \
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scope_bank_valid_st1, \
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@ -113,41 +102,30 @@
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wire scope_icache_rsp_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_req_valid; \
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wire [`NW_BITS-1:0] scope_dcache_req_wid; \
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wire [31:0] scope_dcache_req_curr_PC; \
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wire [63:0] scope_dcache_req_addr; \
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wire [31:0] scope_dcache_req_PC; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr; \
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wire scope_dcache_req_rw; \
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wire [7:0] scope_dcache_req_byteen; \
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wire [63:0] scope_dcache_req_data; \
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wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
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wire scope_dcache_req_ready; \
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wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid; \
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wire [63:0] scope_dcache_rsp_data; \
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wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data; \
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wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
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wire scope_dcache_rsp_ready; \
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wire scope_busy; \
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wire scope_snp_rsp_ready; \
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wire scope_schedule_delay; \
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wire scope_mem_delay; \
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wire scope_exec_delay; \
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wire scope_gpr_stage_delay; \
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wire [`NUM_THREADS-1:0] scope_decode_valid; \
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wire [`NW_BITS-1:0] scope_decode_wid; \
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wire [31:0] scope_decode_curr_PC; \
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wire scope_decode_is_jal; \
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wire [`NR_BITS-1:0] scope_decode_rs1; \
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wire [`NR_BITS-1:0] scope_decode_rs2; \
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wire [`NUM_THREADS-1:0] scope_execute_valid; \
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wire [`NW_BITS-1:0] scope_execute_wid; \
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wire [31:0] scope_execute_curr_PC; \
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wire [`NR_BITS-1:0] scope_execute_rd; \
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wire [63:0] scope_execute_a; \
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wire [63:0] scope_execute_b; \
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wire [`NUM_THREADS-1:0] scope_writeback_valid; \
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wire [`NW_BITS-1:0] scope_writeback_wid; \
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wire [31:0] scope_writeback_curr_PC; \
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wire scope_writeback_wb; \
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wire scope_alu_req_valid; \
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wire [`NW_BITS-1:0] scope_alu_req_wid; \
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wire [31:0] scope_alu_req_PC; \
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wire [`NR_BITS-1:0] scope_alu_req_rd; \
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wire [`NUM_THREADS-1:0][31:0] scope_alu_req_a; \
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wire [`NUM_THREADS-1:0][31:0] scope_alu_req_b; \
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wire scope_writeback_valid; \
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wire [`NW_BITS-1:0] scope_writeback_wid; \
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wire [31:0] scope_writeback_PC; \
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wire [`NR_BITS-1:0] scope_writeback_rd; \
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wire [63:0] scope_writeback_data; \
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wire [`NUM_THREADS-1:0][31:0] scope_writeback_data; \
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wire scope_bank_valid_st0; \
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wire scope_bank_valid_st1; \
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wire scope_bank_valid_st2; \
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@ -174,15 +152,15 @@
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`define SCOPE_SIGNALS_LSU_IO \
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output wire [`NUM_THREADS-1:0] scope_dcache_req_valid, \
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output wire [`NW_BITS-1:0] scope_dcache_req_wid, \
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output wire [31:0] scope_dcache_req_curr_PC, \
|
||||
output wire [63:0] scope_dcache_req_addr, \
|
||||
output wire [31:0] scope_dcache_req_PC, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_addr, \
|
||||
output wire scope_dcache_req_rw, \
|
||||
output wire [7:0] scope_dcache_req_byteen, \
|
||||
output wire [63:0] scope_dcache_req_data, \
|
||||
output wire [`NUM_THREADS-1:0][3:0] scope_dcache_req_byteen, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_req_data, \
|
||||
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
|
||||
output wire scope_dcache_req_ready, \
|
||||
output wire [`NUM_THREADS-1:0] scope_dcache_rsp_valid, \
|
||||
output wire [63:0] scope_dcache_rsp_data, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_dcache_rsp_data, \
|
||||
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
|
||||
output wire scope_dcache_rsp_ready,
|
||||
|
||||
|
|
@ -202,35 +180,24 @@
|
|||
output wire scope_bank_stall_pipe,
|
||||
|
||||
`define SCOPE_SIGNALS_PIPELINE_IO \
|
||||
output wire scope_busy, \
|
||||
output wire scope_schedule_delay, \
|
||||
output wire scope_mem_delay, \
|
||||
output wire scope_exec_delay, \
|
||||
output wire scope_gpr_stage_delay,
|
||||
output wire scope_busy,
|
||||
|
||||
`define SCOPE_SIGNALS_BE_IO \
|
||||
output wire [`NUM_THREADS-1:0] scope_decode_valid, \
|
||||
output wire [`NW_BITS-1:0] scope_decode_wid, \
|
||||
output wire [31:0] scope_decode_curr_PC, \
|
||||
output wire scope_decode_is_jal, \
|
||||
output wire [`NR_BITS-1:0] scope_decode_rs1, \
|
||||
output wire [`NR_BITS-1:0] scope_decode_rs2, \
|
||||
output wire [`NUM_THREADS-1:0] scope_execute_valid, \
|
||||
output wire [`NW_BITS-1:0] scope_execute_wid, \
|
||||
output wire [31:0] scope_execute_curr_PC, \
|
||||
output wire [`NR_BITS-1:0] scope_execute_rd, \
|
||||
output wire [63:0] scope_execute_a, \
|
||||
output wire [63:0] scope_execute_b, \
|
||||
output wire [`NUM_THREADS-1:0] scope_writeback_valid, \
|
||||
output wire [`NW_BITS-1:0] scope_writeback_wid, \
|
||||
output wire [31:0] scope_writeback_curr_PC, \
|
||||
output wire scope_writeback_wb, \
|
||||
output wire [`NR_BITS-1:0] scope_writeback_rd, \
|
||||
output wire [63:0] scope_writeback_data,
|
||||
`define SCOPE_SIGNALS_EX_IO \
|
||||
output wire scope_alu_req_valid, \
|
||||
output wire [`NW_BITS-1:0] scope_alu_req_wid, \
|
||||
output wire [31:0] scope_alu_req_PC, \
|
||||
output wire [`NR_BITS-1:0] scope_alu_req_rd, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_alu_req_a, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_alu_req_b, \
|
||||
output wire scope_writeback_valid, \
|
||||
output wire [`NW_BITS-1:0] scope_writeback_wid, \
|
||||
output wire [31:0] scope_writeback_PC, \
|
||||
output wire [`NR_BITS-1:0] scope_writeback_rd, \
|
||||
output wire [`NUM_THREADS-1:0][31:0] scope_writeback_data,
|
||||
|
||||
`define SCOPE_SIGNALS_ISTAGE_BIND \
|
||||
.scope_icache_req_valid (scope_icache_req_valid), \
|
||||
.scope_icache_req_wid (scope_icache_req_wid), \
|
||||
.scope_icache_req_wid (scope_icache_req_wid), \
|
||||
.scope_icache_req_addr (scope_icache_req_addr), \
|
||||
.scope_icache_req_tag (scope_icache_req_tag), \
|
||||
.scope_icache_req_ready (scope_icache_req_ready), \
|
||||
|
|
@ -241,8 +208,8 @@
|
|||
|
||||
`define SCOPE_SIGNALS_LSU_BIND \
|
||||
.scope_dcache_req_valid (scope_dcache_req_valid), \
|
||||
.scope_dcache_req_wid (scope_dcache_req_wid), \
|
||||
.scope_dcache_req_curr_PC (scope_dcache_req_curr_PC), \
|
||||
.scope_dcache_req_wid (scope_dcache_req_wid), \
|
||||
.scope_dcache_req_PC (scope_dcache_req_PC), \
|
||||
.scope_dcache_req_addr (scope_dcache_req_addr), \
|
||||
.scope_dcache_req_rw (scope_dcache_req_rw), \
|
||||
.scope_dcache_req_byteen(scope_dcache_req_byteen), \
|
||||
|
|
@ -311,42 +278,31 @@
|
|||
assign scope_bank_stall_pipe = scope_per_bank_stall_pipe[0];
|
||||
|
||||
`define SCOPE_SIGNALS_CACHE_BANK_BIND \
|
||||
.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
|
||||
.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
|
||||
.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
|
||||
.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
|
||||
.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
|
||||
.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
|
||||
.scope_bank_valid_st0 (scope_per_bank_valid_st0[i]), \
|
||||
.scope_bank_valid_st1 (scope_per_bank_valid_st1[i]), \
|
||||
.scope_bank_valid_st2 (scope_per_bank_valid_st2[i]), \
|
||||
.scope_bank_addr_st0 (scope_per_bank_addr_st0[i]), \
|
||||
.scope_bank_addr_st1 (scope_per_bank_addr_st1[i]), \
|
||||
.scope_bank_addr_st2 (scope_per_bank_addr_st2[i]), \
|
||||
.scope_bank_is_mrvq_st1 (scope_per_bank_is_mrvq_st1[i]), \
|
||||
.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
|
||||
.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
|
||||
.scope_bank_miss_st1 (scope_per_bank_miss_st1[i]), \
|
||||
.scope_bank_dirty_st1 (scope_per_bank_dirty_st1[i]), \
|
||||
.scope_bank_force_miss_st1 (scope_per_bank_force_miss_st1[i]), \
|
||||
.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
|
||||
.scope_bank_stall_pipe (scope_per_bank_stall_pipe[i]),
|
||||
|
||||
`define SCOPE_SIGNALS_PIPELINE_BIND \
|
||||
.scope_busy (scope_busy), \
|
||||
.scope_schedule_delay (scope_schedule_delay), \
|
||||
.scope_mem_delay (scope_mem_delay), \
|
||||
.scope_exec_delay (scope_exec_delay), \
|
||||
.scope_gpr_stage_delay (scope_gpr_stage_delay),
|
||||
.scope_busy (scope_busy),
|
||||
|
||||
`define SCOPE_SIGNALS_BE_BIND \
|
||||
.scope_decode_valid (scope_decode_valid), \
|
||||
.scope_decode_wid (scope_decode_wid), \
|
||||
.scope_decode_curr_PC (scope_decode_curr_PC), \
|
||||
.scope_decode_is_jal (scope_decode_is_jal), \
|
||||
.scope_decode_rs1 (scope_decode_rs1), \
|
||||
.scope_decode_rs2 (scope_decode_rs2), \
|
||||
.scope_execute_valid (scope_execute_valid), \
|
||||
.scope_execute_wid (scope_execute_wid), \
|
||||
.scope_execute_curr_PC (scope_execute_curr_PC), \
|
||||
.scope_execute_rd (scope_execute_rd), \
|
||||
.scope_execute_a (scope_execute_a), \
|
||||
.scope_execute_b (scope_execute_b), \
|
||||
`define SCOPE_SIGNALS_EX_BIND \
|
||||
.scope_alu_req_valid (scope_alu_req_valid), \
|
||||
.scope_alu_req_wid (scope_alu_req_wid), \
|
||||
.scope_alu_req_PC (scope_alu_req_PC), \
|
||||
.scope_alu_req_rd (scope_alu_req_rd), \
|
||||
.scope_alu_req_a (scope_alu_req_a), \
|
||||
.scope_alu_req_b (scope_alu_req_b), \
|
||||
.scope_writeback_valid (scope_writeback_valid), \
|
||||
.scope_writeback_wid (scope_writeback_wid), \
|
||||
.scope_writeback_curr_PC(scope_writeback_curr_PC), \
|
||||
.scope_writeback_wb (scope_writeback_wb), \
|
||||
.scope_writeback_wid (scope_writeback_wid), \
|
||||
.scope_writeback_PC (scope_writeback_PC), \
|
||||
.scope_writeback_rd (scope_writeback_rd), \
|
||||
.scope_writeback_data (scope_writeback_data),
|
||||
|
||||
|
|
@ -357,14 +313,14 @@
|
|||
`define SCOPE_SIGNALS_CORE_IO
|
||||
`define SCOPE_SIGNALS_CACHE_IO
|
||||
`define SCOPE_SIGNALS_PIPELINE_IO
|
||||
`define SCOPE_SIGNALS_BE_IO
|
||||
`define SCOPE_SIGNALS_EX_IO
|
||||
|
||||
`define SCOPE_SIGNALS_ISTAGE_BIND
|
||||
`define SCOPE_SIGNALS_LSU_BIND
|
||||
`define SCOPE_SIGNALS_CORE_BIND
|
||||
`define SCOPE_SIGNALS_CACHE_BIND
|
||||
`define SCOPE_SIGNALS_PIPELINE_BIND
|
||||
`define SCOPE_SIGNALS_BE_BIND
|
||||
`define SCOPE_SIGNALS_EX_BIND
|
||||
|
||||
`define SCOPE_SIGNALS_CACHE_UNBIND
|
||||
`define SCOPE_SIGNALS_CACHE_BANK_SELECT
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ module Vortex (
|
|||
`SCOPE_SIGNALS_CORE_IO
|
||||
`SCOPE_SIGNALS_CACHE_IO
|
||||
`SCOPE_SIGNALS_PIPELINE_IO
|
||||
`SCOPE_SIGNALS_BE_IO
|
||||
`SCOPE_SIGNALS_EX_IO
|
||||
|
||||
// Clock
|
||||
input wire clk,
|
||||
|
|
@ -81,7 +81,7 @@ module Vortex (
|
|||
`SCOPE_SIGNALS_CORE_BIND
|
||||
`SCOPE_SIGNALS_CACHE_BIND
|
||||
`SCOPE_SIGNALS_PIPELINE_BIND
|
||||
`SCOPE_SIGNALS_BE_BIND
|
||||
`SCOPE_SIGNALS_EX_BIND
|
||||
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
|
@ -200,7 +200,7 @@ module Vortex (
|
|||
`SCOPE_SIGNALS_CORE_BIND
|
||||
`SCOPE_SIGNALS_CACHE_BIND
|
||||
`SCOPE_SIGNALS_PIPELINE_BIND
|
||||
`SCOPE_SIGNALS_BE_BIND
|
||||
`SCOPE_SIGNALS_EX_BIND
|
||||
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue