github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-24 13:57:17 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

fixed rop bug

Browse source
This commit is contained in:
Blaise Tine 2022-08-03 17:17:56 -07:00
parent 9143c19be3
commit c7e511ed1e
4 changed files with 13 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

1
hw/rtl/VX_core.sv
View file

@ -18,6 +18,7 @@
`endif
`IGNORE_WARNINGS_BEGIN
import VX_gpu_types::*;
`ifdef EXT_F_ENABLE
import VX_fpu_types::*;
`endif

12
hw/rtl/rop_unit/VX_rop_mem.sv
View file

@ -86,6 +86,7 @@ module VX_rop_mem #(
.result (m_y_pitch)
);
wire mask = req_ds_mask[i];
wire [31:0] baddr = dcrs.zbuf_addr + (req_pos_x[i] * 4);
wire [3:0] byteen = req_rw ? {stencil_byteen[i], depth_byteen} : 4'b1111;
wire [31:0] data = {req_stencil[i], req_depth[i]};
@ -98,8 +99,8 @@ module VX_rop_mem #(
.clk (clk),
.reset (reset),
.enable (mul_ready_in),
.data_in ({req_ds_mask[i], byteen, baddr, data}),
.data_out ({mreq_mask[i], mreq_byteen[i], baddr_s, mreq_data[i]})
.data_in ({mask, byteen, baddr, data}),
.data_out ({mreq_mask[i], mreq_byteen[i], baddr_s, mreq_data[i]})
);
wire [31:0] addr = baddr_s + m_y_pitch;
@ -125,6 +126,7 @@ module VX_rop_mem #(
.result (m_y_pitch)
);
wire mask = req_c_mask[i - NUM_LANES];
wire [31:0] baddr = dcrs.cbuf_addr + (req_pos_x[i - NUM_LANES] * 4);
wire [3:0] byteen = req_rw ? color_byteen : 4'b1111;
wire [31:0] data = req_color[i - NUM_LANES];
@ -137,8 +139,8 @@ module VX_rop_mem #(
.clk (clk),
.reset (reset),
.enable (mul_ready_in),
.data_in ({req_c_mask[i - NUM_LANES], byteen, baddr, data}),
.data_out ({mreq_mask[i], mreq_byteen[i], baddr_s, mreq_data[i]})
.data_in ({mask, byteen, baddr, data}),
.data_out ({mreq_mask[i], mreq_byteen[i], baddr_s, mreq_data[i]})
);
wire [31:0] addr = baddr_s + m_y_pitch;
@ -161,7 +163,7 @@ module VX_rop_mem #(
wire mreq_stall = mreq_valid_r && ~mreq_ready_r;
assign mul_ready_in = ~mreq_stall || ~mreq_valid;
assign mul_ready_in = ~(mreq_valid && mreq_stall);
assign req_ready = mul_ready_in;

10
hw/rtl/rop_unit/VX_rop_unit.sv
View file

@ -246,16 +246,16 @@ module VX_rop_unit #(
assign ds_write_mask[i] = ds_rsp_mask[i] && (stencil_writeen || (depth_writeen && ds_pass_out[i]));
assign blend_write_mask[i] = blend_rsp_mask[i] && blend_writeen && (~ds_enable || ds_pass_out[i]);
assign color_bypass_mask[i] = rop_req_if.mask[i] && color_writeen;
assign ds_color_write_mask[i] = ds_rsp_mask[i] && color_writeen && ds_pass_out[i];
assign ds_color_write_mask[i] = ds_rsp_mask[i] && ds_pass_out[i];
end
assign mem_req_valid = ds_blend_write || ds_blend_read || color_write;
assign mem_req_ds_mask = ds_valid_out ? ds_write_mask : ds_read_mask;
assign mem_req_c_mask = blend_enable ? (blend_valid_out ? blend_write_mask : blend_read_mask) : (ds_color_writeen ? ds_color_write_mask : color_bypass_mask);
assign mem_req_c_mask = write_bypass ? color_bypass_mask : (blend_valid_out ? blend_write_mask : (ds_valid_out ? ds_color_write_mask : blend_read_mask));
assign mem_req_rw = ds_blend_write || write_bypass;
assign mem_req_face = ds_write_face;
assign mem_req_pos_x = ds_blend_write ? (ds_enable ? ds_write_pos_x : blend_write_pos_x) : rop_req_if.pos_x;
assign mem_req_pos_y = ds_blend_write ? (ds_enable ? ds_write_pos_y : blend_write_pos_y) : rop_req_if.pos_y;
assign mem_req_pos_x = ds_valid_out ? ds_write_pos_x : (blend_valid_out ? blend_write_pos_x : rop_req_if.pos_x);
assign mem_req_pos_y = ds_valid_out ? ds_write_pos_y : (blend_valid_out ? blend_write_pos_y : rop_req_if.pos_y);
assign mem_req_color = blend_enable ? blend_color_out : (ds_enable ? ds_write_color : rop_req_if.color);
assign mem_req_depth = ds_depth_out;
assign mem_req_stencil = ds_stencil_out;
@ -465,4 +465,4 @@ module VX_rop_unit_top #(
.cache_rsp_if (cache_rsp_if)
);
endmodule
endmodule

1
hw/syn/altera/quartus/project.tcl
View file

@ -32,7 +32,6 @@ set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
#set_global_assignment -name OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON