mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 05:47:35 -04:00
minor FPU RTL fixes
This commit is contained in:
Blaise Tine
parent
66b8a27d8f
commit
c806babd1b
5 changed files with 35 additions and 179 deletions
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@ -1,155 +0,0 @@
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rv32ud-p-fadd.hex ✅
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rv32ud-p-fclass.hex ✅
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rv32ud-p-fcmp.hex ✅
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rv32ud-p-fcvt.hex ✅
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rv32ud-p-fcvt_w.hex ✅
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rv32ud-p-fdiv.hex ✅
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rv32ud-p-fmadd.hex ✅
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rv32ud-p-fmin.hex ✅
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rv32ud-p-ldst.hex ✅
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rv32ud-p-recoding.hex ✅
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rv32uf-p-fadd.hex ✅
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rv32uf-p-fclass.hex ✅
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rv32uf-p-fcmp.hex ✅
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rv32uf-p-fcvt.hex ✅
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rv32uf-p-fcvt_w.hex ✅
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rv32uf-p-fdiv.hex ✅
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rv32uf-p-fmadd.hex ✅
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rv32uf-p-fmin.hex ✅
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rv32uf-p-ldst.hex ✅
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rv32uf-p-move.hex ✅
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rv32uf-p-recoding.hex ✅
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rv32ui-p-add.hex ✅
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rv32ui-p-addi.hex ✅
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rv32ui-p-and.hex ✅
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rv32ui-p-andi.hex ✅
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rv32ui-p-auipc.hex ✅
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rv32ui-p-beq.hex ✅
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rv32ui-p-bge.hex ✅
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rv32ui-p-bgeu.hex ✅
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rv32ui-p-blt.hex ✅
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rv32ui-p-bltu.hex ✅
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rv32ui-p-bne.hex ✅
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rv32ui-p-fence_i.hex ✅
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rv32ui-p-jal.hex ✅
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rv32ui-p-jalr.hex ✅
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rv32ui-p-lb.hex ✅
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rv32ui-p-lbu.hex ✅
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rv32ui-p-lh.hex ✅
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rv32ui-p-lhu.hex ✅
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rv32ui-p-lui.hex ✅
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rv32ui-p-lw.hex ✅
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rv32ui-p-or.hex ✅
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rv32ui-p-ori.hex ✅
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rv32ui-p-sb.hex ✅
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rv32ui-p-sh.hex ✅
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rv32ui-p-simple.hex ✅
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rv32ui-p-sll.hex ✅
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rv32ui-p-slli.hex ✅
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rv32ui-p-slt.hex ✅
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rv32ui-p-slti.hex ✅
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rv32ui-p-sltiu.hex ✅
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rv32ui-p-sltu.hex ✅
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rv32ui-p-sra.hex ✅
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rv32ui-p-srai.hex ✅
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rv32ui-p-srl.hex ✅
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rv32ui-p-srli.hex ✅
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rv32ui-p-sub.hex ✅
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rv32ui-p-sw.hex ✅
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rv32ui-p-xor.hex ✅
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rv32ui-p-xori.hex ✅
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rv32um-p-div.hex ✅
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rv32um-p-divu.hex ✅
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rv32um-p-mul.hex ✅
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rv32um-p-mulh.hex ✅
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rv32um-p-mulhsu.hex ✅
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rv32um-p-mulhu.hex ✅
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rv32um-p-rem.hex ✅
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rv32um-p-remu.hex ✅
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rv64ud-p-fadd.hex ❌
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rv64ud-p-fclass.hex ❌
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rv64ud-p-fcmp.hex ❌
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rv64ud-p-fcvt.hex ❌
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rv64ud-p-fcvt_w.hex ❌
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rv64ud-p-fdiv.hex ❌
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rv64ud-p-fmadd.hex ❌
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rv64ud-p-fmin.hex ❌
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rv64ud-p-ldst.hex ❌ exitcode=13
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rv64ud-p-move.hex ❌
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rv64ud-p-recoding.hex ❌
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rv64ud-p-structural.hex ❌
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rv64uf-p-fadd.hex ❌ exitcode=7
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rv64uf-p-fclass.hex ✅
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rv64uf-p-fcmp.hex ✅
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rv64uf-p-fcvt.hex ❌ exitcode=7
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rv64uf-p-fcvt_w.hex ❌ exitcode=5
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rv64uf-p-fdiv.hex ❌ exitcode=7
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rv64uf-p-fmadd.hex ❌ exitcode=9
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rv64uf-p-fmin.hex ❌ exitcode=7
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rv64uf-p-ldst.hex ❌ exitcode=5
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rv64uf-p-move.hex ❌ exitcode=23
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rv64uf-p-recoding.hex ✅
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rv64ui-p-add.hex ✅
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rv64ui-p-addi.hex ✅
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rv64ui-p-addiw.hex ✅
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rv64ui-p-addw.hex ✅
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rv64ui-p-and.hex ✅
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rv64ui-p-andi.hex ✅
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rv64ui-p-auipc.hex ✅
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rv64ui-p-beq.hex ✅
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rv64ui-p-bge.hex ✅
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rv64ui-p-bgeu.hex ✅
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rv64ui-p-blt.hex ✅
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rv64ui-p-bltu.hex ✅
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rv64ui-p-bne.hex ✅
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rv64ui-p-fence_i.hex ❌ exitcode=5
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rv64ui-p-jal.hex ✅
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rv64ui-p-jalr.hex ✅
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rv64ui-p-lb.hex ✅
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rv64ui-p-lbu.hex ✅
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rv64ui-p-ld.hex ✅
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rv64ui-p-lh.hex ✅
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rv64ui-p-lhu.hex ✅
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rv64ui-p-lui.hex ✅
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rv64ui-p-lw.hex ✅
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rv64ui-p-lwu.hex ✅
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rv64ui-p-or.hex ✅
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rv64ui-p-ori.hex ✅
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rv64ui-p-sb.hex ✅
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rv64ui-p-sd.hex ✅
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rv64ui-p-sh.hex ❌ exitcode=7
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rv64ui-p-simple.hex ✅
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rv64ui-p-sll.hex ✅
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rv64ui-p-slli.hex ✅
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rv64ui-p-slliw.hex ✅
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rv64ui-p-sllw.hex ✅
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rv64ui-p-slt.hex ✅
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rv64ui-p-slti.hex ✅
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rv64ui-p-sltiu.hex ✅
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rv64ui-p-sltu.hex ✅
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rv64ui-p-sra.hex ✅
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rv64ui-p-srai.hex ✅
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rv64ui-p-sraiw.hex ❌ exitcode=5
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rv64ui-p-sraw.hex ❌ exitcode=5
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rv64ui-p-srl.hex ✅
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rv64ui-p-srli.hex ✅
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rv64ui-p-srliw.hex ❌ exitcode=7
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rv64ui-p-srlw.hex ❌ exitcode=7
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rv64ui-p-sub.hex ✅
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rv64ui-p-subw.hex ✅
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rv64ui-p-sw.hex ❌ exitcode=7
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rv64ui-p-xor.hex ✅
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rv64ui-p-xori.hex ✅
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rv64um-p-div.hex ✅
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rv64um-p-divu.hex ✅
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rv64um-p-divuw.hex ✅
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rv64um-p-divw.hex ✅
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rv64um-p-mul.hex ✅
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rv64um-p-mulh.hex ❌ exitcode=15
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rv64um-p-mulhsu.hex ❌ exitcode=15
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rv64um-p-mulhu.hex ✅
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rv64um-p-mulw.hex ✅
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rv64um-p-rem.hex ✅
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rv64um-p-remu.hex ✅
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rv64um-p-remuw.hex ❌ exitcode=5
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rv64um-p-remw.hex ❌ exitcode=5
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@ -136,11 +136,11 @@
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0: `TRACE(level, ("SGNJ")); \
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1: `TRACE(level, ("SGNJN")); \
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2: `TRACE(level, ("SGNJX")); \
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3: `TRACE(level, ("MIN")); \
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4: `TRACE(level, ("MAX")); \
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5: `TRACE(level, ("MVXW")); \
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6: `TRACE(level, ("MVWX")); \
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7: `TRACE(level, ("CLASS")); \
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3: `TRACE(level, ("CLASS")); \
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4: `TRACE(level, ("FMV.X.W")); \
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5: `TRACE(level, ("FMV.W.X")); \
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6: `TRACE(level, ("MIN")); \
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7: `TRACE(level, ("MAX")); \
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8: `TRACE(level, ("FLE")); \
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9: `TRACE(level, ("FLT")); \
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10: `TRACE(level, ("FEQ")); \
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@ -314,7 +314,7 @@ module VX_decode #(
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`INST_FNMSUB,
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`INST_FNMADD: begin
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ex_type = `EX_FPU;
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op_type = `INST_OP_BITS'({2'b10, opcode[3:2]});
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op_type = `INST_OP_BITS'({2'b11, opcode[3:2]});
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op_mod = `INST_MOD_BITS'(func3);
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use_rd = 1;
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`USED_FREG (rd);
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@ -63,7 +63,8 @@ module VX_fpu_agent #(
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wire [`INST_MOD_BITS-1:0] req_op_mod;
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assign fpu_to_csr_if.read_wid = fpu_agent_if.wid;
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assign req_op_mod = (fpu_agent_if.op_type != `INST_FPU_NCP
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&& fpu_agent_if.op_mod[2:0] == `INST_FRM_DYN) ? {1'b0, fpu_to_csr_if.read_frm} : fpu_agent_if.op_mod;
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&& fpu_agent_if.op_mod[2:0] == `INST_FRM_DYN) ? {fpu_agent_if.op_mod[`INST_MOD_BITS-1:`INST_FRM_BITS], fpu_to_csr_if.read_frm} :
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fpu_agent_if.op_mod;
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// submit FPU request
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@ -33,20 +33,23 @@ module VX_fpu_fpnew #(
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input wire ready_out,
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output wire valid_out
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);
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localparam FOP_BITS = fpnew_pkg::OP_BITS;
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localparam FMTF_BITS = fpnew_pkg::FP_FORMAT_BITS;
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localparam FMTI_BITS = fpnew_pkg::INT_FORMAT_BITS;
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localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT);
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`ifdef XLEN_64
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`ifdef FLEN_32
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`define ISA_RV64F
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`endif
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`endif
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localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{
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Width: `XLEN,
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EnableVectors: 1'b0,
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EnableNanBox: 1'b1,
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FpFmtMask: 5'b10000,
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EnableNanBox: 1'b0,
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`ifdef XLEN_64
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FpFmtMask: 5'b11000,
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IntFmtMask: 4'b0011
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`else
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FpFmtMask: 5'b10000,
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IntFmtMask: 4'b0010
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`endif
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};
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@ -73,11 +76,11 @@ module VX_fpu_fpnew #(
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wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result;
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fpnew_pkg::status_t [NUM_LANES-1:0] fpu_status;
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reg [FOP_BITS-1:0] fpu_op;
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reg [fpnew_pkg::OP_BITS-1:0] fpu_op;
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reg [`INST_FRM_BITS-1:0] fpu_rnd;
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reg fpu_op_mod;
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reg fpu_has_fflags, fpu_has_fflags_out;
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reg [FMTF_BITS-1:0] fpu_src_fmt, fpu_dst_fmt, fpu_int_fmt;
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reg [fpnew_pkg::FP_FORMAT_BITS-1:0] fpu_src_fmt, fpu_dst_fmt, fpu_int_fmt;
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wire is_fp_w = op_mod[3];
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@ -118,19 +121,26 @@ module VX_fpu_fpnew #(
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`INST_FPU_CVTXWU:begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = 1; end
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`INST_FPU_NCP: begin
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case (op_mod)
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0: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RNE; fpu_has_fflags = 0; end // FSGNJ
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1: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RTZ; fpu_has_fflags = 0; end // FSGNJN
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2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RDN; fpu_has_fflags = 0; end // FSGNJX
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0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, op_mod[1:0]}; fpu_has_fflags = 0; end // FSGNJ
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3: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS
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4: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_op_mod = 1; fpu_has_fflags = 0; end // FMV.X.W
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5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = `INST_FRM_RUP; fpu_has_fflags = 0; end // FMV.W.X
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6: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RNE; end // MIN
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7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = `INST_FRM_RTZ; end // MAX
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default: begin fpu_op = fpnew_pkg::CMP; fpu_has_fflags = 0; end // CMP (8,9,10)
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4: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = 1; fpu_has_fflags = 0; end // FMV.X.W
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5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_has_fflags = 0; end // FMV.W.X
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6: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = 3'b000; end // MIN
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7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = 3'b001; end // MAX
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default: begin fpu_op = fpnew_pkg::CMP; fpu_rnd = {1'b0, op_mod[1:0]}; end // CMP (8,9,10)
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endcase
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end
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default:;
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endcase
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endcase
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`ifdef ISA_RV64F
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// apply nan-boxing to floating-point operands
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if (op_type != `INST_FPU_CVTXW && op_type != `INST_FPU_CVTXWU) begin
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fpu_operands[0] |= 64'hffffffff00000000;
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end
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fpu_operands[1] |= 64'hffffffff00000000;
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fpu_operands[2] |= 64'hffffffff00000000;
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`endif
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end
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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